Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	246761	1			T1	3		T3	5		T10	13
all_pins[1]	246761	1			T1	3		T3	5		T10	13
all_pins[2]	246761	1			T1	3		T3	5		T10	13
all_pins[3]	246761	1			T1	3		T3	5		T10	13

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	787656	1			T1	11		T3	18		T10	44
values[0x1]	199388	1			T1	1		T3	2		T10	8
transitions[0x0=>0x1]	131952	1			T3	1		T10	3		T13	9
transitions[0x1=>0x0]	132215	1			T1	1		T3	2		T10	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	194952	1			T1	2		T3	3		T10	12
all_pins[0]	values[0x1]	51809	1			T1	1		T3	2		T10	1
all_pins[0]	transitions[0x0=>0x1]	51228	1			T3	1		T13	4		T17	5
all_pins[0]	transitions[0x1=>0x0]	48108	1			T10	1		T13	5		T17	11
all_pins[1]	values[0x0]	196312	1			T1	3		T3	5		T10	10
all_pins[1]	values[0x1]	50449	1			T10	3		T13	4		T17	10
all_pins[1]	transitions[0x0=>0x1]	27878	1			T10	2		T13	2		T17	8
all_pins[1]	transitions[0x1=>0x0]	29238	1			T1	1		T3	2		T13	3
all_pins[2]	values[0x0]	198057	1			T1	3		T3	5		T10	10
all_pins[2]	values[0x1]	48704	1			T10	3		T13	5		T17	6
all_pins[2]	transitions[0x0=>0x1]	26499	1			T10	1		T13	2		T17	3
all_pins[2]	transitions[0x1=>0x0]	28244	1			T10	1		T13	1		T17	7
all_pins[3]	values[0x0]	198335	1			T1	3		T3	5		T10	12
all_pins[3]	values[0x1]	48426	1			T10	1		T13	5		T17	11
all_pins[3]	transitions[0x0=>0x1]	26347	1			T13	1		T17	7		T15	1
all_pins[3]	transitions[0x1=>0x0]	26625	1			T10	2		T13	1		T17	2