Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	61187	1			T262	286		T335	308		T336	289
accum_cnt_1000	144648	1			T59	5		T63	7		T122	71
accum_cnt_100	18546	1			T44	10		T59	33		T63	2
accum_cnt_50	49387	1			T10	2		T13	6		T17	16
accum_cnt_10	147477	1			T3	2		T10	27		T13	24
accum_cnt_0	278993	1			T1	4		T3	6		T10	19

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	182670	1			T1	1		T3	2		T10	12
class_index[0x1]	182670	1			T1	1		T3	2		T10	12
class_index[0x2]	182670	1			T1	1		T3	2		T10	12
class_index[0x3]	182670	1			T1	1		T3	2		T10	12

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	19154	1			T336	267		T330	125		T337	198
class_index[0x0]	accum_cnt_1000	39905	1			T59	3		T84	26		T38	20
class_index[0x0]	accum_cnt_100	5165	1			T44	10		T59	15		T63	2
class_index[0x0]	accum_cnt_50	13165	1			T32	7		T53	9		T44	15
class_index[0x0]	accum_cnt_10	33222	1			T3	2		T10	8		T13	2
class_index[0x0]	accum_cnt_0	63736	1			T1	1		T10	4		T11	20
class_index[0x1]	accum_cnt_2000	13825	1			T335	308		T306	163		T116	395
class_index[0x1]	accum_cnt_1000	34580	1			T122	25		T84	28		T226	15
class_index[0x1]	accum_cnt_100	4216	1			T122	23		T84	14		T226	21
class_index[0x1]	accum_cnt_50	12949	1			T27	10		T28	6		T31	6
class_index[0x1]	accum_cnt_10	34604	1			T10	10		T13	14		T15	8
class_index[0x1]	accum_cnt_0	76780	1			T1	1		T3	2		T10	2
class_index[0x2]	accum_cnt_2000	13688	1			T336	22		T148	104		T74	117
class_index[0x2]	accum_cnt_1000	32454	1			T59	2		T63	7		T122	26
class_index[0x2]	accum_cnt_100	4881	1			T59	18		T122	20		T146	6
class_index[0x2]	accum_cnt_50	9071	1			T13	6		T58	7		T59	12
class_index[0x2]	accum_cnt_10	44029	1			T10	1		T13	7		T15	9
class_index[0x2]	accum_cnt_0	72796	1			T1	1		T3	2		T10	11
class_index[0x3]	accum_cnt_2000	14520	1			T262	286		T338	212		T339	222
class_index[0x3]	accum_cnt_1000	37709	1			T122	20		T244	26		T84	24
class_index[0x3]	accum_cnt_100	4284	1			T122	24		T244	22		T84	19
class_index[0x3]	accum_cnt_50	14202	1			T10	2		T17	16		T53	7
class_index[0x3]	accum_cnt_10	35622	1			T10	8		T13	1		T17	10
class_index[0x3]	accum_cnt_0	65681	1			T1	1		T3	2		T10	2