Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3347	1			T63	120		T228	1		T261	44
alert[0x1]	2475	1			T50	11		T340	1		T37	1
alert[0x2]	5513	1			T61	7		T146	1		T123	3
alert[0x3]	8906	1			T50	12		T302	1		T341	1
alert[0x4]	8404	1			T60	47		T146	53		T102	18
alert[0x5]	2950	1			T66	4		T50	67		T340	1
alert[0x6]	5156	1			T342	1		T66	1		T102	16
alert[0x7]	5847	1			T27	6		T63	20		T66	29
alert[0x8]	11371	1			T28	1		T343	1		T340	1
alert[0x9]	2568	1			T28	4		T146	2		T261	3
alert[0xa]	5136	1			T61	1		T50	33		T71	6
alert[0xb]	3091	1			T344	1		T342	1		T102	1
alert[0xc]	5131	1			T18	1		T344	1		T343	1
alert[0xd]	3921	1			T28	3		T123	2		T340	1
alert[0xe]	1071	1			T20	1		T66	3		T50	2
alert[0xf]	4783	1			T63	7		T66	10		T50	157
alert[0x10]	2136	1			T19	1		T66	12		T340	1
alert[0x11]	6439	1			T342	1		T343	1		T271	1
alert[0x12]	4921	1			T19	1		T50	3		T40	13
alert[0x13]	4122	1			T60	4		T50	3		T105	1
alert[0x14]	3141	1			T60	1		T64	11		T261	2
alert[0x15]	2664	1			T19	1		T342	1		T66	2
alert[0x16]	2504	1			T18	2		T342	1		T50	2
alert[0x17]	4790	1			T60	3		T146	1		T344	2
alert[0x18]	2959	1			T64	6		T50	3		T340	1
alert[0x19]	2983	1			T54	24		T60	2		T63	1
alert[0x1a]	1590	1			T63	13		T64	2		T66	9
alert[0x1b]	5174	1			T144	7		T340	1		T102	24
alert[0x1c]	3079	1			T27	1		T28	1		T60	12
alert[0x1d]	2063	1			T81	2		T123	5		T66	1
alert[0x1e]	2037	1			T50	1		T271	1		T313	1
alert[0x1f]	1544	1			T54	1		T19	1		T344	1
alert[0x20]	975	1			T28	15		T54	1		T50	2
alert[0x21]	1162	1			T81	29		T302	2		T271	1
alert[0x22]	1466	1			T228	1		T66	151		T343	1
alert[0x23]	4954	1			T28	1		T228	2		T144	56
alert[0x24]	4881	1			T66	7		T340	1		T345	1
alert[0x25]	4440	1			T28	9		T18	1		T63	14
alert[0x26]	3084	1			T64	7		T50	3		T302	1
alert[0x27]	10340	1			T64	2		T343	1		T40	19
alert[0x28]	8387	1			T228	1		T261	1		T144	24
alert[0x29]	2009	1			T28	84		T60	3		T261	3
alert[0x2a]	4000	1			T66	1		T340	1		T113	11
alert[0x2b]	7361	1			T60	71		T34	89		T113	28
alert[0x2c]	2070	1			T60	9		T343	1		T102	9
alert[0x2d]	11105	1			T20	1		T344	2		T66	28
alert[0x2e]	1550	1			T27	2		T146	3		T50	1
alert[0x2f]	5982	1			T63	2		T20	1		T343	1
alert[0x30]	2410	1			T18	1		T64	1		T66	4
alert[0x31]	2762	1			T60	1		T302	1		T271	1
alert[0x32]	7552	1			T37	1		T106	2		T34	79
alert[0x33]	7790	1			T28	7		T344	1		T346	1
alert[0x34]	6001	1			T63	6		T66	1		T347	1
alert[0x35]	3724	1			T146	5		T343	1		T340	1
alert[0x36]	1671	1			T60	2		T345	1		T271	1
alert[0x37]	8058	1			T19	1		T20	1		T146	20
alert[0x38]	5893	1			T63	4		T20	1		T64	3
alert[0x39]	2004	1			T27	15		T342	1		T261	39
alert[0x3a]	4320	1			T344	1		T66	18		T50	3
alert[0x3b]	6091	1			T66	22		T346	1		T302	1
alert[0x3c]	2206	1			T60	4		T342	2		T261	2
alert[0x3d]	6016	1			T66	7		T50	251		T37	1
alert[0x3e]	2516	1			T27	15		T63	1		T261	4
alert[0x3f]	2874	1			T63	20		T64	1		T344	1
alert[0x40]	4010	1			T50	21		T341	1		T106	54

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	52597	1			T61	4		T18	3		T19	1
class_i[0x1]	90895	1			T27	35		T54	26		T60	159
class_i[0x2]	73230	1			T27	4		T61	4		T18	1
class_i[0x3]	64758	1			T28	125		T18	1		T63	22

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

280828

1

T27

39

T28

125

T54

26

alert_ping_fail

652

1

T18

5

T19

6

T20

5

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3342	1			T63	120		T261	44		T40	21
alert_integrity_fail	alert[0x1]	2464	1			T50	11		T37	1		T262	2
alert_integrity_fail	alert[0x2]	5500	1			T61	7		T146	1		T123	3
alert_integrity_fail	alert[0x3]	8899	1			T50	12		T33	3		T154	185
alert_integrity_fail	alert[0x4]	8398	1			T60	47		T146	53		T102	18
alert_integrity_fail	alert[0x5]	2936	1			T66	4		T50	67		T102	4
alert_integrity_fail	alert[0x6]	5141	1			T66	1		T102	16		T119	6
alert_integrity_fail	alert[0x7]	5837	1			T27	6		T63	20		T66	29
alert_integrity_fail	alert[0x8]	11361	1			T28	1		T34	9		T153	2
alert_integrity_fail	alert[0x9]	2558	1			T28	4		T146	2		T261	3
alert_integrity_fail	alert[0xa]	5127	1			T61	1		T50	33		T71	6
alert_integrity_fail	alert[0xb]	3083	1			T102	1		T223	2		T34	97
alert_integrity_fail	alert[0xc]	5117	1			T34	3		T107	2		T337	199
alert_integrity_fail	alert[0xd]	3914	1			T28	3		T123	2		T348	2
alert_integrity_fail	alert[0xe]	1058	1			T66	3		T50	2		T348	8
alert_integrity_fail	alert[0xf]	4769	1			T63	7		T66	10		T50	157
alert_integrity_fail	alert[0x10]	2129	1			T66	12		T37	67		T349	7
alert_integrity_fail	alert[0x11]	6427	1			T71	72		T34	1		T132	1
alert_integrity_fail	alert[0x12]	4907	1			T50	3		T40	13		T71	25
alert_integrity_fail	alert[0x13]	4108	1			T60	4		T50	3		T105	1
alert_integrity_fail	alert[0x14]	3127	1			T60	1		T64	11		T261	2
alert_integrity_fail	alert[0x15]	2650	1			T66	2		T40	2		T107	11
alert_integrity_fail	alert[0x16]	2485	1			T50	2		T350	4		T70	2
alert_integrity_fail	alert[0x17]	4780	1			T60	3		T146	1		T50	1
alert_integrity_fail	alert[0x18]	2950	1			T64	6		T50	3		T351	1
alert_integrity_fail	alert[0x19]	2976	1			T54	24		T60	2		T63	1
alert_integrity_fail	alert[0x1a]	1579	1			T63	13		T64	2		T66	9
alert_integrity_fail	alert[0x1b]	5169	1			T144	7		T102	24		T132	216
alert_integrity_fail	alert[0x1c]	3073	1			T27	1		T28	1		T60	12
alert_integrity_fail	alert[0x1d]	2055	1			T81	2		T123	5		T66	1
alert_integrity_fail	alert[0x1e]	2022	1			T50	1		T34	11		T337	82
alert_integrity_fail	alert[0x1f]	1530	1			T54	1		T40	4		T132	1
alert_integrity_fail	alert[0x20]	964	1			T28	15		T54	1		T50	2
alert_integrity_fail	alert[0x21]	1152	1			T81	29		T71	1		T34	16
alert_integrity_fail	alert[0x22]	1458	1			T66	151		T70	7		T106	2
alert_integrity_fail	alert[0x23]	4947	1			T28	1		T144	56		T70	1
alert_integrity_fail	alert[0x24]	4868	1			T66	7		T40	6		T262	1
alert_integrity_fail	alert[0x25]	4432	1			T28	9		T63	14		T66	8
alert_integrity_fail	alert[0x26]	3077	1			T64	7		T50	3		T40	1
alert_integrity_fail	alert[0x27]	10335	1			T64	2		T40	19		T262	4
alert_integrity_fail	alert[0x28]	8378	1			T261	1		T144	24		T40	1
alert_integrity_fail	alert[0x29]	2005	1			T28	84		T60	3		T261	3
alert_integrity_fail	alert[0x2a]	3995	1			T66	1		T113	11		T154	22
alert_integrity_fail	alert[0x2b]	7353	1			T60	71		T34	89		T113	28
alert_integrity_fail	alert[0x2c]	2059	1			T60	9		T102	9		T34	72
alert_integrity_fail	alert[0x2d]	11097	1			T66	28		T348	1		T40	171
alert_integrity_fail	alert[0x2e]	1541	1			T27	2		T146	3		T50	1
alert_integrity_fail	alert[0x2f]	5975	1			T63	2		T71	6		T34	4
alert_integrity_fail	alert[0x30]	2395	1			T64	1		T66	4		T50	3
alert_integrity_fail	alert[0x31]	2755	1			T60	1		T262	1		T106	1
alert_integrity_fail	alert[0x32]	7544	1			T37	1		T106	2		T34	79
alert_integrity_fail	alert[0x33]	7775	1			T28	7		T40	7		T106	4
alert_integrity_fail	alert[0x34]	5989	1			T63	6		T66	1		T262	1
alert_integrity_fail	alert[0x35]	3710	1			T146	5		T70	5		T106	36
alert_integrity_fail	alert[0x36]	1663	1			T60	2		T106	1		T34	1
alert_integrity_fail	alert[0x37]	8047	1			T146	20		T66	1		T40	1
alert_integrity_fail	alert[0x38]	5884	1			T63	4		T64	3		T105	3
alert_integrity_fail	alert[0x39]	1994	1			T27	15		T261	39		T50	45
alert_integrity_fail	alert[0x3a]	4308	1			T66	18		T50	3		T119	4
alert_integrity_fail	alert[0x3b]	6074	1			T66	22		T303	6		T135	61
alert_integrity_fail	alert[0x3c]	2196	1			T60	4		T261	2		T66	2
alert_integrity_fail	alert[0x3d]	6005	1			T66	7		T50	251		T37	1
alert_integrity_fail	alert[0x3e]	2505	1			T27	15		T63	1		T261	4
alert_integrity_fail	alert[0x3f]	2871	1			T63	20		T64	1		T34	1
alert_integrity_fail	alert[0x40]	4006	1			T50	21		T106	54		T351	7
alert_ping_fail	alert[0x0]	5	1			T228	1		T302	1		T352	1
alert_ping_fail	alert[0x1]	11	1			T340	1		T347	1		T353	1
alert_ping_fail	alert[0x2]	13	1			T302	1		T354	1		T355	1
alert_ping_fail	alert[0x3]	7	1			T302	1		T341	1		T356	1
alert_ping_fail	alert[0x4]	6	1			T307	1		T357	1		T358	1
alert_ping_fail	alert[0x5]	14	1			T340	1		T271	1		T328	1
alert_ping_fail	alert[0x6]	15	1			T342	1		T347	1		T359	1
alert_ping_fail	alert[0x7]	10	1			T359	1		T313	1		T355	1
alert_ping_fail	alert[0x8]	10	1			T343	1		T340	1		T271	1
alert_ping_fail	alert[0x9]	10	1			T302	2		T271	1		T352	1
alert_ping_fail	alert[0xa]	9	1			T307	1		T357	1		T358	1
alert_ping_fail	alert[0xb]	8	1			T344	1		T342	1		T341	1
alert_ping_fail	alert[0xc]	14	1			T18	1		T344	1		T343	1
alert_ping_fail	alert[0xd]	7	1			T340	1		T341	1		T360	1
alert_ping_fail	alert[0xe]	13	1			T20	1		T302	1		T341	1
alert_ping_fail	alert[0xf]	14	1			T343	1		T346	1		T271	1
alert_ping_fail	alert[0x10]	7	1			T19	1		T340	1		T347	1
alert_ping_fail	alert[0x11]	12	1			T342	1		T343	1		T271	1
alert_ping_fail	alert[0x12]	14	1			T19	1		T271	1		T359	1
alert_ping_fail	alert[0x13]	14	1			T313	1		T355	1		T307	1
alert_ping_fail	alert[0x14]	14	1			T343	1		T313	1		T355	1
alert_ping_fail	alert[0x15]	14	1			T19	1		T342	1		T302	1
alert_ping_fail	alert[0x16]	19	1			T18	2		T342	1		T345	1
alert_ping_fail	alert[0x17]	10	1			T344	2		T340	1		T271	1
alert_ping_fail	alert[0x18]	9	1			T340	1		T353	2		T352	1
alert_ping_fail	alert[0x19]	7	1			T344	1		T341	1		T359	1
alert_ping_fail	alert[0x1a]	11	1			T343	1		T361	1		T352	1
alert_ping_fail	alert[0x1b]	5	1			T340	1		T341	1		T362	1
alert_ping_fail	alert[0x1c]	6	1			T271	1		T341	1		T354	1
alert_ping_fail	alert[0x1d]	8	1			T346	1		T341	1		T359	1
alert_ping_fail	alert[0x1e]	15	1			T271	1		T313	1		T354	1
alert_ping_fail	alert[0x1f]	14	1			T19	1		T344	1		T345	1
alert_ping_fail	alert[0x20]	11	1			T340	1		T363	1		T359	1
alert_ping_fail	alert[0x21]	10	1			T302	2		T271	1		T307	1
alert_ping_fail	alert[0x22]	8	1			T228	1		T343	1		T340	1
alert_ping_fail	alert[0x23]	7	1			T228	2		T302	1		T354	1
alert_ping_fail	alert[0x24]	13	1			T340	1		T345	1		T341	1
alert_ping_fail	alert[0x25]	8	1			T18	1		T19	1		T302	1
alert_ping_fail	alert[0x26]	7	1			T302	1		T313	1		T358	1
alert_ping_fail	alert[0x27]	5	1			T343	1		T363	1		T313	1
alert_ping_fail	alert[0x28]	9	1			T228	1		T328	1		T352	1
alert_ping_fail	alert[0x29]	4	1			T343	1		T307	1		T364	1
alert_ping_fail	alert[0x2a]	5	1			T340	1		T352	1		T365	1
alert_ping_fail	alert[0x2b]	8	1			T360	1		T352	1		T364	1
alert_ping_fail	alert[0x2c]	11	1			T343	1		T313	1		T354	1
alert_ping_fail	alert[0x2d]	8	1			T20	1		T344	2		T340	1
alert_ping_fail	alert[0x2e]	9	1			T341	1		T353	1		T307	1
alert_ping_fail	alert[0x2f]	7	1			T20	1		T343	1		T347	1
alert_ping_fail	alert[0x30]	15	1			T18	1		T346	1		T347	1
alert_ping_fail	alert[0x31]	7	1			T302	1		T271	1		T313	1
alert_ping_fail	alert[0x32]	8	1			T360	1		T366	1		T365	1
alert_ping_fail	alert[0x33]	15	1			T344	1		T346	1		T345	1
alert_ping_fail	alert[0x34]	12	1			T347	1		T341	1		T359	1
alert_ping_fail	alert[0x35]	14	1			T343	1		T340	1		T313	1
alert_ping_fail	alert[0x36]	8	1			T345	1		T271	1		T359	1
alert_ping_fail	alert[0x37]	11	1			T19	1		T20	1		T302	1
alert_ping_fail	alert[0x38]	9	1			T20	1		T344	1		T302	1
alert_ping_fail	alert[0x39]	10	1			T342	1		T363	1		T354	1
alert_ping_fail	alert[0x3a]	12	1			T344	1		T313	1		T355	1
alert_ping_fail	alert[0x3b]	17	1			T346	1		T302	1		T271	1
alert_ping_fail	alert[0x3c]	10	1			T342	2		T346	1		T355	2
alert_ping_fail	alert[0x3d]	11	1			T271	1		T359	1		T361	1
alert_ping_fail	alert[0x3e]	11	1			T347	1		T341	1		T361	1
alert_ping_fail	alert[0x3f]	3	1			T344	1		T342	1		T367	1
alert_ping_fail	alert[0x40]	4	1			T341	1		T362	1		T365	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	52387	1			T61	4		T64	20		T144	99
alert_integrity_fail	class_i[0x1]	90755	1			T27	35		T54	26		T60	159
alert_integrity_fail	class_i[0x2]	73061	1			T27	4		T61	4		T63	186
alert_integrity_fail	class_i[0x3]	64625	1			T28	125		T63	22		T64	8
alert_ping_fail	class_i[0x0]	210	1			T18	3		T19	1		T228	2
alert_ping_fail	class_i[0x1]	140	1			T19	1		T20	5		T228	1
alert_ping_fail	class_i[0x2]	169	1			T18	1		T19	3		T228	1
alert_ping_fail	class_i[0x3]	133	1			T18	1		T19	1		T228	1