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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.24 99.99 98.68 97.09 100.00 100.00 99.38 99.52


Total test records in report: 808
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T777 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.2210687492 Aug 25 12:46:59 PM UTC 24 Aug 25 12:47:02 PM UTC 24 17247389 ps
T778 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3078850963 Aug 25 12:46:52 PM UTC 24 Aug 25 12:47:02 PM UTC 24 28521823 ps
T779 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.2591534341 Aug 25 12:47:01 PM UTC 24 Aug 25 12:47:04 PM UTC 24 8699688 ps
T780 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.1217699811 Aug 25 12:47:03 PM UTC 24 Aug 25 12:47:06 PM UTC 24 11182877 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.3625953746 Aug 25 12:47:03 PM UTC 24 Aug 25 12:47:07 PM UTC 24 11012129 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.3797466044 Aug 25 12:47:05 PM UTC 24 Aug 25 12:47:08 PM UTC 24 10981221 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.2375803907 Aug 25 12:47:07 PM UTC 24 Aug 25 12:47:11 PM UTC 24 17474265 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.2891616961 Aug 25 12:47:07 PM UTC 24 Aug 25 12:47:11 PM UTC 24 12467863 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.2986657152 Aug 25 12:47:09 PM UTC 24 Aug 25 12:47:13 PM UTC 24 24903715 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.1837342697 Aug 25 12:47:12 PM UTC 24 Aug 25 12:47:15 PM UTC 24 8423528 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.4154242 Aug 25 12:47:12 PM UTC 24 Aug 25 12:47:15 PM UTC 24 7581814 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.3948609649 Aug 25 12:47:14 PM UTC 24 Aug 25 12:47:17 PM UTC 24 11958798 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.3291717356 Aug 25 12:47:16 PM UTC 24 Aug 25 12:47:19 PM UTC 24 21554020 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.2643296823 Aug 25 12:47:16 PM UTC 24 Aug 25 12:47:19 PM UTC 24 111201970 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.3347745154 Aug 25 12:47:18 PM UTC 24 Aug 25 12:47:21 PM UTC 24 9481369 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.4076775488 Aug 25 12:43:21 PM UTC 24 Aug 25 12:47:22 PM UTC 24 3807621114 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2729659853 Aug 25 12:46:50 PM UTC 24 Aug 25 12:47:22 PM UTC 24 692309704 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.1745096557 Aug 25 12:47:20 PM UTC 24 Aug 25 12:47:24 PM UTC 24 13454060 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.3247360696 Aug 25 12:47:20 PM UTC 24 Aug 25 12:47:24 PM UTC 24 11294751 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.2907096246 Aug 25 12:47:22 PM UTC 24 Aug 25 12:47:25 PM UTC 24 15442945 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.771876879 Aug 25 12:47:23 PM UTC 24 Aug 25 12:47:26 PM UTC 24 8665122 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.725560601 Aug 25 12:47:23 PM UTC 24 Aug 25 12:47:26 PM UTC 24 8875195 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.2420415297 Aug 25 12:47:25 PM UTC 24 Aug 25 12:47:28 PM UTC 24 9868651 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.215791913 Aug 25 12:47:25 PM UTC 24 Aug 25 12:47:28 PM UTC 24 8398202 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.3189402487 Aug 25 12:47:25 PM UTC 24 Aug 25 12:47:28 PM UTC 24 9686375 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.2590213360 Aug 25 12:47:26 PM UTC 24 Aug 25 12:47:30 PM UTC 24 11807584 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.2705483963 Aug 25 12:47:27 PM UTC 24 Aug 25 12:47:31 PM UTC 24 19435005 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.3000190624 Aug 25 12:47:30 PM UTC 24 Aug 25 12:47:33 PM UTC 24 9651702 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.1947695073 Aug 25 12:47:30 PM UTC 24 Aug 25 12:47:33 PM UTC 24 6150474 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.3019204709 Aug 25 12:47:30 PM UTC 24 Aug 25 12:47:33 PM UTC 24 19156825 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.2974030481 Aug 25 12:47:31 PM UTC 24 Aug 25 12:47:34 PM UTC 24 19116258 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.900251244 Aug 25 12:47:32 PM UTC 24 Aug 25 12:47:35 PM UTC 24 8342022 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3181380515 Aug 25 12:46:48 PM UTC 24 Aug 25 12:47:43 PM UTC 24 2763976730 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3257063437 Aug 25 12:36:14 PM UTC 24 Aug 25 12:48:26 PM UTC 24 6266886378 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.868210736 Aug 25 12:40:48 PM UTC 24 Aug 25 12:49:00 PM UTC 24 3924869621 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3867503889 Aug 25 12:42:21 PM UTC 24 Aug 25 12:49:20 PM UTC 24 2537888185 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.649497008 Aug 25 12:44:40 PM UTC 24 Aug 25 12:49:39 PM UTC 24 4467315050 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.701701896 Aug 25 12:45:29 PM UTC 24 Aug 25 12:50:08 PM UTC 24 10076405164 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1757743343 Aug 25 12:42:37 PM UTC 24 Aug 25 12:50:15 PM UTC 24 2171488504 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1297191659 Aug 25 12:46:29 PM UTC 24 Aug 25 12:50:26 PM UTC 24 7112541860 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3298174524 Aug 25 12:40:38 PM UTC 24 Aug 25 12:50:53 PM UTC 24 9062964205 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3792875199 Aug 25 12:34:32 PM UTC 24 Aug 25 12:51:20 PM UTC 24 26344482925 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.144391955 Aug 25 12:41:57 PM UTC 24 Aug 25 12:51:54 PM UTC 24 68572106458 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3975778604 Aug 25 12:38:12 PM UTC 24 Aug 25 12:52:08 PM UTC 24 7950832798 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3770223848 Aug 25 12:40:10 PM UTC 24 Aug 25 12:54:00 PM UTC 24 26835440765 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2878536328 Aug 25 12:39:44 PM UTC 24 Aug 25 12:54:19 PM UTC 24 6396043936 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1053086049 Aug 25 12:41:10 PM UTC 24 Aug 25 12:55:47 PM UTC 24 27036044789 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2204838112 Aug 25 12:31:10 PM UTC 24 Aug 25 12:56:04 PM UTC 24 50461735890 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1510056630 Aug 25 12:43:45 PM UTC 24 Aug 25 12:57:44 PM UTC 24 12148582758 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.201017840 Aug 25 12:41:37 PM UTC 24 Aug 25 12:58:53 PM UTC 24 4778111255 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.4226802310 Aug 25 12:44:36 PM UTC 24 Aug 25 12:59:01 PM UTC 24 16889550756 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.33261417 Aug 25 12:37:32 PM UTC 24 Aug 25 01:07:25 PM UTC 24 49381093671 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1788960070 Aug 25 12:38:51 PM UTC 24 Aug 25 01:09:15 PM UTC 24 15803676227 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2467198025 Aug 25 12:43:20 PM UTC 24 Aug 25 01:12:29 PM UTC 24 25260968775 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1495207059 Aug 25 12:45:19 PM UTC 24 Aug 25 01:13:22 PM UTC 24 12155157332 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3341360808 Aug 25 12:41:52 PM UTC 24 Aug 25 01:13:48 PM UTC 24 31224121608 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2169697093 Aug 25 12:46:18 PM UTC 24 Aug 25 01:14:35 PM UTC 24 14565808918 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.632779621 Aug 25 12:42:17 PM UTC 24 Aug 25 01:14:52 PM UTC 24 63863168830 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_classes.2837612736
Short name T13
Test name
Test status
Simulation time 185909861 ps
CPU time 25.7 seconds
Started Aug 25 11:11:53 AM UTC 24
Finished Aug 25 11:12:20 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837612736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2837612736
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/3.alert_handler_sec_cm.694847335
Short name T51
Test name
Test status
Simulation time 686133510 ps
CPU time 18.6 seconds
Started Aug 25 11:12:58 AM UTC 24
Finished Aug 25 11:13:17 AM UTC 24
Peak memory 297316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694847335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.694847335
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_classes.1278401724
Short name T55
Test name
Test status
Simulation time 2407864884 ps
CPU time 66.79 seconds
Started Aug 25 11:12:17 AM UTC 24
Finished Aug 25 11:13:26 AM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278401724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1278401724
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy_stress.2794893358
Short name T21
Test name
Test status
Simulation time 117386217 ps
CPU time 13.16 seconds
Started Aug 25 11:12:51 AM UTC 24
Finished Aug 25 11:13:06 AM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794893358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2794893358
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all_with_rand_reset.1903557644
Short name T37
Test name
Test status
Simulation time 15836602382 ps
CPU time 251.9 seconds
Started Aug 25 11:21:27 AM UTC 24
Finished Aug 25 11:25:43 AM UTC 24
Peak memory 279480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1903557644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.a
lert_handler_stress_all_with_rand_reset.1903557644
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_intr_timeout.1374306958
Short name T16
Test name
Test status
Simulation time 217568768 ps
CPU time 11.77 seconds
Started Aug 25 11:12:20 AM UTC 24
Finished Aug 25 11:12:33 AM UTC 24
Peak memory 263264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374306958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1374306958
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1485610461
Short name T202
Test name
Test status
Simulation time 549419155 ps
CPU time 72.73 seconds
Started Aug 25 12:31:47 PM UTC 24
Finished Aug 25 12:33:02 PM UTC 24
Peak memory 250392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485610461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1485610461
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all_with_rand_reset.195563126
Short name T66
Test name
Test status
Simulation time 1526560605 ps
CPU time 283.69 seconds
Started Aug 25 11:16:26 AM UTC 24
Finished Aug 25 11:21:15 AM UTC 24
Peak memory 279748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=195563126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.ale
rt_handler_stress_all_with_rand_reset.195563126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all_with_rand_reset.2162777777
Short name T40
Test name
Test status
Simulation time 6470278697 ps
CPU time 353.58 seconds
Started Aug 25 11:20:12 AM UTC 24
Finished Aug 25 11:26:11 AM UTC 24
Peak memory 281600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2162777777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.a
lert_handler_stress_all_with_rand_reset.2162777777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/1.alert_handler_sig_int_fail.2589925051
Short name T27
Test name
Test status
Simulation time 565363976 ps
CPU time 47.18 seconds
Started Aug 25 11:11:56 AM UTC 24
Finished Aug 25 11:12:45 AM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589925051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2589925051
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.269305014
Short name T165
Test name
Test status
Simulation time 6604622486 ps
CPU time 343.38 seconds
Started Aug 25 12:34:34 PM UTC 24
Finished Aug 25 12:40:23 PM UTC 24
Peak memory 279460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269305014 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.269305014
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all_with_rand_reset.3853701171
Short name T113
Test name
Test status
Simulation time 4037365345 ps
CPU time 445.32 seconds
Started Aug 25 11:38:02 AM UTC 24
Finished Aug 25 11:45:35 AM UTC 24
Peak memory 279872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3853701171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.a
lert_handler_stress_all_with_rand_reset.3853701171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg.4219364536
Short name T331
Test name
Test status
Simulation time 58640806944 ps
CPU time 1867.81 seconds
Started Aug 25 11:16:12 AM UTC 24
Finished Aug 25 11:47:47 AM UTC 24
Peak memory 297784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219364536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.4219364536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_alert_accum.3132353848
Short name T59
Test name
Test status
Simulation time 6540007119 ps
CPU time 140.6 seconds
Started Aug 25 11:11:37 AM UTC 24
Finished Aug 25 11:14:00 AM UTC 24
Peak memory 263324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132353848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3132353848
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all.3227616777
Short name T285
Test name
Test status
Simulation time 94642916620 ps
CPU time 4580.18 seconds
Started Aug 25 11:32:23 AM UTC 24
Finished Aug 25 12:49:45 PM UTC 24
Peak memory 304676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227616777 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all.3227616777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/21.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_classes.446727649
Short name T149
Test name
Test status
Simulation time 144735890 ps
CPU time 25.42 seconds
Started Aug 25 12:06:24 PM UTC 24
Finished Aug 25 12:06:51 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446727649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.446727649
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/36.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2578371929
Short name T172
Test name
Test status
Simulation time 6367492152 ps
CPU time 285.66 seconds
Started Aug 25 12:41:26 PM UTC 24
Finished Aug 25 12:46:17 PM UTC 24
Peak memory 279592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578371929 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.2578371929
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg.2561042377
Short name T396
Test name
Test status
Simulation time 45609056154 ps
CPU time 2112.4 seconds
Started Aug 25 11:58:11 AM UTC 24
Finished Aug 25 12:33:54 PM UTC 24
Peak memory 299832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561042377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2561042377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/31.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2467198025
Short name T201
Test name
Test status
Simulation time 25260968775 ps
CPU time 1724.73 seconds
Started Aug 25 12:43:20 PM UTC 24
Finished Aug 25 01:12:29 PM UTC 24
Peak memory 279528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467198025 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shad
ow_reg_errors_with_csr_rw.2467198025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/0.alert_handler_ping_timeout.3302887582
Short name T302
Test name
Test status
Simulation time 25115194982 ps
CPU time 771.54 seconds
Started Aug 25 11:11:39 AM UTC 24
Finished Aug 25 11:24:42 AM UTC 24
Peak memory 269192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302887582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3302887582
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy.1602761074
Short name T337
Test name
Test status
Simulation time 19418691834 ps
CPU time 1540.3 seconds
Started Aug 25 11:18:14 AM UTC 24
Finished Aug 25 11:44:17 AM UTC 24
Peak memory 295816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602761074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1602761074
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2499649483
Short name T169
Test name
Test status
Simulation time 14640532009 ps
CPU time 418.85 seconds
Started Aug 25 12:38:59 PM UTC 24
Finished Aug 25 12:46:05 PM UTC 24
Peak memory 279528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499649483 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.2499649483
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_alerts.488577834
Short name T12
Test name
Test status
Simulation time 2415765336 ps
CPU time 32.65 seconds
Started Aug 25 11:11:50 AM UTC 24
Finished Aug 25 11:12:25 AM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488577834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.488577834
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/15.alert_handler_ping_timeout.2607047532
Short name T313
Test name
Test status
Simulation time 20697510056 ps
CPU time 566.4 seconds
Started Aug 25 11:22:47 AM UTC 24
Finished Aug 25 11:32:22 AM UTC 24
Peak memory 269196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607047532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2607047532
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_intr_test.2516449323
Short name T397
Test name
Test status
Simulation time 54577663 ps
CPU time 2.38 seconds
Started Aug 25 12:37:49 PM UTC 24
Finished Aug 25 12:37:53 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516449323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2516449323
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.4226802310
Short name T189
Test name
Test status
Simulation time 16889550756 ps
CPU time 853.01 seconds
Started Aug 25 12:44:36 PM UTC 24
Finished Aug 25 12:59:01 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226802310 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shad
ow_reg_errors_with_csr_rw.4226802310
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_intg_err.4280783834
Short name T208
Test name
Test status
Simulation time 894007872 ps
CPU time 103.49 seconds
Started Aug 25 12:38:23 PM UTC 24
Finished Aug 25 12:40:09 PM UTC 24
Peak memory 252580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280783834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.4280783834
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg.4155056010
Short name T333
Test name
Test status
Simulation time 23275950781 ps
CPU time 2335.56 seconds
Started Aug 25 11:12:04 AM UTC 24
Finished Aug 25 11:51:31 AM UTC 24
Peak memory 288216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155056010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.4155056010
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/8.alert_handler_sig_int_fail.564264209
Short name T146
Test name
Test status
Simulation time 971949120 ps
CPU time 80.19 seconds
Started Aug 25 11:16:03 AM UTC 24
Finished Aug 25 11:17:26 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564264209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.564264209
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/10.alert_handler_ping_timeout.1737025983
Short name T341
Test name
Test status
Simulation time 26347823284 ps
CPU time 686.17 seconds
Started Aug 25 11:18:14 AM UTC 24
Finished Aug 25 11:29:49 AM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737025983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1737025983
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all.3654995264
Short name T74
Test name
Test status
Simulation time 45080477393 ps
CPU time 2334.86 seconds
Started Aug 25 11:14:44 AM UTC 24
Finished Aug 25 11:54:10 AM UTC 24
Peak memory 318256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654995264 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all.3654995264
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.868210736
Short name T171
Test name
Test status
Simulation time 3924869621 ps
CPU time 484.61 seconds
Started Aug 25 12:40:48 PM UTC 24
Finished Aug 25 12:49:00 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868210736 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.868210736
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_classes.1153711531
Short name T58
Test name
Test status
Simulation time 1823127696 ps
CPU time 47.81 seconds
Started Aug 25 11:13:02 AM UTC 24
Finished Aug 25 11:13:51 AM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153711531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1153711531
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/22.alert_handler_ping_timeout.547691999
Short name T360
Test name
Test status
Simulation time 52535807032 ps
CPU time 753.33 seconds
Started Aug 25 11:35:46 AM UTC 24
Finished Aug 25 11:48:29 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547691999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.547691999
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg.984297072
Short name T328
Test name
Test status
Simulation time 44712940681 ps
CPU time 1448.03 seconds
Started Aug 25 11:14:32 AM UTC 24
Finished Aug 25 11:39:01 AM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984297072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.984297072
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.4290769251
Short name T167
Test name
Test status
Simulation time 1953929057 ps
CPU time 245.96 seconds
Started Aug 25 12:31:31 PM UTC 24
Finished Aug 25 12:35:42 PM UTC 24
Peak memory 269088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290769251 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.4290769251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/0.alert_handler_sec_cm.2758776842
Short name T4
Test name
Test status
Simulation time 2311791718 ps
CPU time 41.07 seconds
Started Aug 25 11:11:46 AM UTC 24
Finished Aug 25 11:12:29 AM UTC 24
Peak memory 295468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758776842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2758776842
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3257063437
Short name T180
Test name
Test status
Simulation time 6266886378 ps
CPU time 720.87 seconds
Started Aug 25 12:36:14 PM UTC 24
Finished Aug 25 12:48:26 PM UTC 24
Peak memory 279656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257063437 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shado
w_reg_errors_with_csr_rw.3257063437
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all_with_rand_reset.930647302
Short name T71
Test name
Test status
Simulation time 4707182293 ps
CPU time 696.32 seconds
Started Aug 25 11:26:14 AM UTC 24
Finished Aug 25 11:38:01 AM UTC 24
Peak memory 283576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=930647302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.al
ert_handler_stress_all_with_rand_reset.930647302
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_classes.1921044412
Short name T17
Test name
Test status
Simulation time 936020948 ps
CPU time 43.52 seconds
Started Aug 25 11:11:35 AM UTC 24
Finished Aug 25 11:12:20 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921044412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1921044412
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg.2413930110
Short name T377
Test name
Test status
Simulation time 52288340080 ps
CPU time 2419.87 seconds
Started Aug 25 11:23:57 AM UTC 24
Finished Aug 25 12:04:51 PM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413930110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2413930110
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg.1795404603
Short name T390
Test name
Test status
Simulation time 43913079621 ps
CPU time 3179.44 seconds
Started Aug 25 12:03:25 PM UTC 24
Finished Aug 25 12:57:03 PM UTC 24
Peak memory 298468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795404603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1795404603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/34.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/5.alert_handler_ping_timeout.3683300814
Short name T342
Test name
Test status
Simulation time 24708381876 ps
CPU time 343.61 seconds
Started Aug 25 11:13:53 AM UTC 24
Finished Aug 25 11:19:41 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683300814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3683300814
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/9.alert_handler_ping_timeout.2291211963
Short name T343
Test name
Test status
Simulation time 38508982752 ps
CPU time 372.15 seconds
Started Aug 25 11:17:24 AM UTC 24
Finished Aug 25 11:23:43 AM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291211963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2291211963
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_classes.2824319462
Short name T78
Test name
Test status
Simulation time 6015361958 ps
CPU time 89.81 seconds
Started Aug 25 11:16:36 AM UTC 24
Finished Aug 25 11:18:09 AM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824319462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2824319462
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2685068601
Short name T179
Test name
Test status
Simulation time 1630320008 ps
CPU time 168.88 seconds
Started Aug 25 12:43:56 PM UTC 24
Finished Aug 25 12:46:48 PM UTC 24
Peak memory 279328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685068601 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.2685068601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.33261417
Short name T188
Test name
Test status
Simulation time 49381093671 ps
CPU time 1767.81 seconds
Started Aug 25 12:37:32 PM UTC 24
Finished Aug 25 01:07:25 PM UTC 24
Peak memory 279532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33261417 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_
reg_errors_with_csr_rw.33261417
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_intr_test.2239222821
Short name T404
Test name
Test status
Simulation time 15900283 ps
CPU time 2.37 seconds
Started Aug 25 12:42:13 PM UTC 24
Finished Aug 25 12:42:16 PM UTC 24
Peak memory 250536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239222821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2239222821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg.2821109165
Short name T314
Test name
Test status
Simulation time 34632104752 ps
CPU time 1344.54 seconds
Started Aug 25 11:19:53 AM UTC 24
Finished Aug 25 11:42:37 AM UTC 24
Peak memory 285828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821109165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2821109165
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_rw.4129592986
Short name T233
Test name
Test status
Simulation time 331767122 ps
CPU time 9.73 seconds
Started Aug 25 12:37:59 PM UTC 24
Finished Aug 25 12:38:10 PM UTC 24
Peak memory 250460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129592986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.4129592986
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all.1119042146
Short name T90
Test name
Test status
Simulation time 8706829100 ps
CPU time 365.09 seconds
Started Aug 25 11:16:23 AM UTC 24
Finished Aug 25 11:22:34 AM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119042146 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all.1119042146
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all.3298633179
Short name T43
Test name
Test status
Simulation time 145564905894 ps
CPU time 2382.12 seconds
Started Aug 25 11:19:12 AM UTC 24
Finished Aug 25 11:59:25 AM UTC 24
Peak memory 301880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298633179 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all.3298633179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg.984844586
Short name T384
Test name
Test status
Simulation time 137748588915 ps
CPU time 3062.84 seconds
Started Aug 25 12:18:16 PM UTC 24
Finished Aug 25 01:09:58 PM UTC 24
Peak memory 302204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984844586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.984844586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/43.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/6.alert_handler_ping_timeout.1233259222
Short name T340
Test name
Test status
Simulation time 33833422852 ps
CPU time 545.48 seconds
Started Aug 25 11:14:32 AM UTC 24
Finished Aug 25 11:23:45 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233259222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1233259222
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/6.alert_handler_sig_int_fail.3095173264
Short name T63
Test name
Test status
Simulation time 2560002648 ps
CPU time 71.31 seconds
Started Aug 25 11:14:26 AM UTC 24
Finished Aug 25 11:15:40 AM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095173264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3095173264
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3792875199
Short name T182
Test name
Test status
Simulation time 26344482925 ps
CPU time 993.94 seconds
Started Aug 25 12:34:32 PM UTC 24
Finished Aug 25 12:51:20 PM UTC 24
Peak memory 285664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792875199 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shado
w_reg_errors_with_csr_rw.3792875199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all.3381728488
Short name T289
Test name
Test status
Simulation time 56600895683 ps
CPU time 1281.2 seconds
Started Aug 25 11:24:59 AM UTC 24
Finished Aug 25 11:46:38 AM UTC 24
Peak memory 279424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381728488 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all.3381728488
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg.470187697
Short name T371
Test name
Test status
Simulation time 34583541447 ps
CPU time 3167.05 seconds
Started Aug 25 11:41:50 AM UTC 24
Finished Aug 25 12:35:18 PM UTC 24
Peak memory 304992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470187697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.470187697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/24.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.632779621
Short name T200
Test name
Test status
Simulation time 63863168830 ps
CPU time 1929.25 seconds
Started Aug 25 12:42:17 PM UTC 24
Finished Aug 25 01:14:52 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632779621 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shado
w_reg_errors_with_csr_rw.632779621
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_intr_timeout.2838114988
Short name T15
Test name
Test status
Simulation time 325263906 ps
CPU time 31.48 seconds
Started Aug 25 11:11:54 AM UTC 24
Finished Aug 25 11:12:27 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838114988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2838114988
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all.2775566151
Short name T48
Test name
Test status
Simulation time 44091150819 ps
CPU time 4711.64 seconds
Started Aug 25 12:14:35 PM UTC 24
Finished Aug 25 01:34:08 PM UTC 24
Peak memory 321060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775566151 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all.2775566151
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/40.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all.1841583091
Short name T136
Test name
Test status
Simulation time 48560113181 ps
CPU time 2029.65 seconds
Started Aug 25 11:39:56 AM UTC 24
Finished Aug 25 12:14:15 PM UTC 24
Peak memory 301880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841583091 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all.1841583091
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/23.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all.904021850
Short name T300
Test name
Test status
Simulation time 58602180946 ps
CPU time 4828.97 seconds
Started Aug 25 12:15:40 PM UTC 24
Finished Aug 25 01:37:06 PM UTC 24
Peak memory 304672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904021850 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all.904021850
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/41.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_alert_accum.2982241697
Short name T122
Test name
Test status
Simulation time 4924163541 ps
CPU time 177.44 seconds
Started Aug 25 11:13:39 AM UTC 24
Finished Aug 25 11:16:40 AM UTC 24
Peak memory 269532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982241697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2982241697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3409043958
Short name T212
Test name
Test status
Simulation time 287859118 ps
CPU time 14.16 seconds
Started Aug 25 12:37:49 PM UTC 24
Finished Aug 25 12:38:05 PM UTC 24
Peak memory 250396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409043958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3409043958
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all.2483098476
Short name T298
Test name
Test status
Simulation time 50972212277 ps
CPU time 4390.92 seconds
Started Aug 25 11:37:19 AM UTC 24
Finished Aug 25 12:51:29 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483098476 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all.2483098476
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/22.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1495207059
Short name T199
Test name
Test status
Simulation time 12155157332 ps
CPU time 1659.87 seconds
Started Aug 25 12:45:19 PM UTC 24
Finished Aug 25 01:13:22 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495207059 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shad
ow_reg_errors_with_csr_rw.1495207059
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/0.alert_handler_alert_accum_saturation.969224254
Short name T2
Test name
Test status
Simulation time 57229960 ps
CPU time 4.3 seconds
Started Aug 25 11:11:44 AM UTC 24
Finished Aug 25 11:11:49 AM UTC 24
Peak memory 263568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969224254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.969224254
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/1.alert_handler_alert_accum_saturation.3009830452
Short name T14
Test name
Test status
Simulation time 49904264 ps
CPU time 4.17 seconds
Started Aug 25 11:12:11 AM UTC 24
Finished Aug 25 11:12:17 AM UTC 24
Peak memory 263500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009830452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3009830452
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/13.alert_handler_alert_accum_saturation.3107241334
Short name T139
Test name
Test status
Simulation time 43601087 ps
CPU time 5.35 seconds
Started Aug 25 11:21:25 AM UTC 24
Finished Aug 25 11:21:32 AM UTC 24
Peak memory 263172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107241334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3107241334
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/2.alert_handler_alert_accum_saturation.4082851704
Short name T26
Test name
Test status
Simulation time 45175953 ps
CPU time 3.69 seconds
Started Aug 25 11:12:30 AM UTC 24
Finished Aug 25 11:12:35 AM UTC 24
Peak memory 263500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082851704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.4082851704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg.1872766467
Short name T334
Test name
Test status
Simulation time 188358277353 ps
CPU time 1608.27 seconds
Started Aug 25 11:22:04 AM UTC 24
Finished Aug 25 11:49:14 AM UTC 24
Peak memory 299832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872766467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1872766467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg.308757932
Short name T385
Test name
Test status
Simulation time 157839348634 ps
CPU time 3178.58 seconds
Started Aug 25 11:22:54 AM UTC 24
Finished Aug 25 12:16:34 PM UTC 24
Peak memory 288212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308757932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.308757932
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_classes.1162515564
Short name T35
Test name
Test status
Simulation time 5981412313 ps
CPU time 79.05 seconds
Started Aug 25 11:40:28 AM UTC 24
Finished Aug 25 11:41:49 AM UTC 24
Peak memory 269504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162515564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1162515564
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/24.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg.2386877730
Short name T392
Test name
Test status
Simulation time 10734008299 ps
CPU time 1495.3 seconds
Started Aug 25 12:01:57 PM UTC 24
Finished Aug 25 12:27:14 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386877730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2386877730
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/33.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all_with_rand_reset.1267363165
Short name T290
Test name
Test status
Simulation time 2384571075 ps
CPU time 371.71 seconds
Started Aug 25 12:18:51 PM UTC 24
Finished Aug 25 12:25:08 PM UTC 24
Peak memory 285616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1267363165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.a
lert_handler_stress_all_with_rand_reset.1267363165
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1658081996
Short name T186
Test name
Test status
Simulation time 8370963814 ps
CPU time 256.8 seconds
Started Aug 25 12:40:20 PM UTC 24
Finished Aug 25 12:44:42 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658081996 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.1658081996
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all.2783092071
Short name T101
Test name
Test status
Simulation time 14981366089 ps
CPU time 681.18 seconds
Started Aug 25 11:11:42 AM UTC 24
Finished Aug 25 11:23:13 AM UTC 24
Peak memory 279352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783092071 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all.2783092071
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all_with_rand_reset.4130296521
Short name T47
Test name
Test status
Simulation time 18127102095 ps
CPU time 828.43 seconds
Started Aug 25 12:17:29 PM UTC 24
Finished Aug 25 12:31:30 PM UTC 24
Peak memory 285616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4130296521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.a
lert_handler_stress_all_with_rand_reset.4130296521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/5.alert_handler_sig_int_fail.3477044175
Short name T61
Test name
Test status
Simulation time 997334167 ps
CPU time 39.92 seconds
Started Aug 25 11:13:51 AM UTC 24
Finished Aug 25 11:14:33 AM UTC 24
Peak memory 262520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477044175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3477044175
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.144391955
Short name T183
Test name
Test status
Simulation time 68572106458 ps
CPU time 587.08 seconds
Started Aug 25 12:41:57 PM UTC 24
Finished Aug 25 12:51:54 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144391955 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.144391955
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3865256996
Short name T266
Test name
Test status
Simulation time 4275179508 ps
CPU time 451.67 seconds
Started Aug 25 12:32:05 PM UTC 24
Finished Aug 25 12:39:43 PM UTC 24
Peak memory 250600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865256996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3865256996
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_intr_test.464809524
Short name T205
Test name
Test status
Simulation time 8450213 ps
CPU time 2.42 seconds
Started Aug 25 12:31:51 PM UTC 24
Finished Aug 25 12:31:55 PM UTC 24
Peak memory 248280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464809524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.464809524
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all_with_rand_reset.4016503251
Short name T102
Test name
Test status
Simulation time 2344137788 ps
CPU time 425.91 seconds
Started Aug 25 11:19:17 AM UTC 24
Finished Aug 25 11:26:30 AM UTC 24
Peak memory 285952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4016503251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.a
lert_handler_stress_all_with_rand_reset.4016503251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy.3639036587
Short name T533
Test name
Test status
Simulation time 495970796930 ps
CPU time 2585.49 seconds
Started Aug 25 11:21:08 AM UTC 24
Finished Aug 25 12:04:49 PM UTC 24
Peak memory 295744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639036587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3639036587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy.3473751937
Short name T311
Test name
Test status
Simulation time 38484900824 ps
CPU time 2632.64 seconds
Started Aug 25 11:26:49 AM UTC 24
Finished Aug 25 12:11:19 PM UTC 24
Peak memory 301632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473751937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3473751937
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/20.alert_handler_ping_timeout.726631841
Short name T307
Test name
Test status
Simulation time 87275676176 ps
CPU time 605.12 seconds
Started Aug 25 11:28:30 AM UTC 24
Finished Aug 25 11:38:45 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726631841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.726631841
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/20.alert_handler_sig_int_fail.2647985621
Short name T104
Test name
Test status
Simulation time 1067970025 ps
CPU time 56.31 seconds
Started Aug 25 11:28:02 AM UTC 24
Finished Aug 25 11:29:00 AM UTC 24
Peak memory 262940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647985621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2647985621
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/21.alert_handler_sig_int_fail.2527867251
Short name T105
Test name
Test status
Simulation time 348459974 ps
CPU time 31.62 seconds
Started Aug 25 11:30:28 AM UTC 24
Finished Aug 25 11:31:01 AM UTC 24
Peak memory 263264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527867251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2527867251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg.1349986283
Short name T374
Test name
Test status
Simulation time 20247530654 ps
CPU time 2347.65 seconds
Started Aug 25 11:35:54 AM UTC 24
Finished Aug 25 12:15:32 PM UTC 24
Peak memory 301880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349986283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1349986283
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/22.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg.885689878
Short name T129
Test name
Test status
Simulation time 10171112384 ps
CPU time 1191.95 seconds
Started Aug 25 11:46:39 AM UTC 24
Finished Aug 25 12:06:47 PM UTC 24
Peak memory 285492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885689878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.885689878
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/26.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/30.alert_handler_sig_int_fail.112762513
Short name T287
Test name
Test status
Simulation time 3314937272 ps
CPU time 38.03 seconds
Started Aug 25 11:55:30 AM UTC 24
Finished Aug 25 11:56:10 AM UTC 24
Peak memory 263296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112762513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.112762513
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all.2585856041
Short name T295
Test name
Test status
Simulation time 188702644782 ps
CPU time 3964.75 seconds
Started Aug 25 12:00:11 PM UTC 24
Finished Aug 25 01:07:07 PM UTC 24
Peak memory 304868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585856041 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all.2585856041
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/32.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/9.alert_handler_sig_int_fail.939004728
Short name T64
Test name
Test status
Simulation time 1075673118 ps
CPU time 49.65 seconds
Started Aug 25 11:17:08 AM UTC 24
Finished Aug 25 11:17:59 AM UTC 24
Peak memory 269276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939004728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.939004728
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_alerts.3694361139
Short name T39
Test name
Test status
Simulation time 353186012 ps
CPU time 47.08 seconds
Started Aug 25 11:25:17 AM UTC 24
Finished Aug 25 11:26:06 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694361139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3694361139
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.39514339
Short name T164
Test name
Test status
Simulation time 8594636914 ps
CPU time 263.91 seconds
Started Aug 25 12:33:03 PM UTC 24
Finished Aug 25 12:37:31 PM UTC 24
Peak memory 283620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39514339 -assert nopostproc +UVM_TESTNAME=alert_handler_ba
se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.39514339
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2246273425
Short name T215
Test name
Test status
Simulation time 38626074 ps
CPU time 5.79 seconds
Started Aug 25 12:42:24 PM UTC 24
Finished Aug 25 12:42:31 PM UTC 24
Peak memory 250388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246273425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2246273425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2809087673
Short name T214
Test name
Test status
Simulation time 21636327 ps
CPU time 4.06 seconds
Started Aug 25 12:36:35 PM UTC 24
Finished Aug 25 12:36:40 PM UTC 24
Peak memory 250532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809087673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2809087673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1038336136
Short name T216
Test name
Test status
Simulation time 297880079 ps
CPU time 6.95 seconds
Started Aug 25 12:41:29 PM UTC 24
Finished Aug 25 12:41:37 PM UTC 24
Peak memory 250388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038336136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1038336136
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3479029684
Short name T213
Test name
Test status
Simulation time 3543922182 ps
CPU time 93.7 seconds
Started Aug 25 12:41:44 PM UTC 24
Finished Aug 25 12:43:20 PM UTC 24
Peak memory 252700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479029684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3479029684
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1827814697
Short name T222
Test name
Test status
Simulation time 2537304794 ps
CPU time 106.01 seconds
Started Aug 25 12:42:51 PM UTC 24
Finished Aug 25 12:44:39 PM UTC 24
Peak memory 252512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827814697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1827814697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3976606666
Short name T219
Test name
Test status
Simulation time 107182555 ps
CPU time 10.85 seconds
Started Aug 25 12:43:29 PM UTC 24
Finished Aug 25 12:43:42 PM UTC 24
Peak memory 250392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976606666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3976606666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3905588719
Short name T209
Test name
Test status
Simulation time 4991009202 ps
CPU time 119.79 seconds
Started Aug 25 12:44:13 PM UTC 24
Finished Aug 25 12:46:15 PM UTC 24
Peak memory 262804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905588719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3905588719
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.800499006
Short name T218
Test name
Test status
Simulation time 2707851198 ps
CPU time 57.28 seconds
Started Aug 25 12:45:50 PM UTC 24
Finished Aug 25 12:46:49 PM UTC 24
Peak memory 252704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800499006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.800499006
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_intg_err.212659298
Short name T210
Test name
Test status
Simulation time 49627913 ps
CPU time 4.73 seconds
Started Aug 25 12:39:12 PM UTC 24
Finished Aug 25 12:39:18 PM UTC 24
Peak memory 250392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212659298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.212659298
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2487063850
Short name T217
Test name
Test status
Simulation time 895525942 ps
CPU time 114.35 seconds
Started Aug 25 12:40:53 PM UTC 24
Finished Aug 25 12:42:50 PM UTC 24
Peak memory 250396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487063850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2487063850
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2213367370
Short name T229
Test name
Test status
Simulation time 3666083777 ps
CPU time 193 seconds
Started Aug 25 12:32:10 PM UTC 24
Finished Aug 25 12:35:26 PM UTC 24
Peak memory 252508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213367370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2213367370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2781084747
Short name T206
Test name
Test status
Simulation time 88485855 ps
CPU time 6.54 seconds
Started Aug 25 12:31:55 PM UTC 24
Finished Aug 25 12:32:03 PM UTC 24
Peak memory 262760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781084747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2781084747
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.394600659
Short name T221
Test name
Test status
Simulation time 118550834 ps
CPU time 9.46 seconds
Started Aug 25 12:32:33 PM UTC 24
Finished Aug 25 12:32:43 PM UTC 24
Peak memory 250456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394600659 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_r
w_with_rand_reset.394600659
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_rw.3954753356
Short name T220
Test name
Test status
Simulation time 19898164 ps
CPU time 3.94 seconds
Started Aug 25 12:32:04 PM UTC 24
Finished Aug 25 12:32:09 PM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954753356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3954753356
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1689707636
Short name T236
Test name
Test status
Simulation time 382625014 ps
CPU time 39.68 seconds
Started Aug 25 12:32:26 PM UTC 24
Finished Aug 25 12:33:08 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689707636 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.1689707636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2204838112
Short name T196
Test name
Test status
Simulation time 50461735890 ps
CPU time 1472.14 seconds
Started Aug 25 12:31:10 PM UTC 24
Finished Aug 25 12:56:04 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204838112 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shado
w_reg_errors_with_csr_rw.2204838112
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_errors.976974347
Short name T702
Test name
Test status
Simulation time 96328332 ps
CPU time 11.87 seconds
Started Aug 25 12:31:33 PM UTC 24
Finished Aug 25 12:31:46 PM UTC 24
Peak memory 268952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976974347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.976974347
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3584825430
Short name T232
Test name
Test status
Simulation time 2376710592 ps
CPU time 218.1 seconds
Started Aug 25 12:33:56 PM UTC 24
Finished Aug 25 12:37:39 PM UTC 24
Peak memory 250528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584825430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3584825430
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1525092985
Short name T714
Test name
Test status
Simulation time 6806331017 ps
CPU time 388.62 seconds
Started Aug 25 12:33:53 PM UTC 24
Finished Aug 25 12:40:28 PM UTC 24
Peak memory 250600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525092985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1525092985
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3180934335
Short name T241
Test name
Test status
Simulation time 63579602 ps
CPU time 12.97 seconds
Started Aug 25 12:33:38 PM UTC 24
Finished Aug 25 12:33:52 PM UTC 24
Peak memory 262620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180934335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3180934335
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2991665571
Short name T245
Test name
Test status
Simulation time 55197272 ps
CPU time 16.12 seconds
Started Aug 25 12:34:32 PM UTC 24
Finished Aug 25 12:34:49 PM UTC 24
Peak memory 254496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991665571 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_
rw_with_rand_reset.2991665571
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_rw.1113694845
Short name T242
Test name
Test status
Simulation time 111723007 ps
CPU time 15.18 seconds
Started Aug 25 12:33:40 PM UTC 24
Finished Aug 25 12:33:56 PM UTC 24
Peak memory 252372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113694845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1113694845
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_intr_test.3211224696
Short name T207
Test name
Test status
Simulation time 9640221 ps
CPU time 2.06 seconds
Started Aug 25 12:33:35 PM UTC 24
Finished Aug 25 12:33:39 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211224696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3211224696
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2523658914
Short name T237
Test name
Test status
Simulation time 1514368770 ps
CPU time 34.13 seconds
Started Aug 25 12:33:58 PM UTC 24
Finished Aug 25 12:34:33 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523658914 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.2523658914
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.514878103
Short name T166
Test name
Test status
Simulation time 2395816854 ps
CPU time 480.97 seconds
Started Aug 25 12:32:45 PM UTC 24
Finished Aug 25 12:40:53 PM UTC 24
Peak memory 279460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514878103 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow
_reg_errors_with_csr_rw.514878103
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_errors.1077502189
Short name T273
Test name
Test status
Simulation time 622655660 ps
CPU time 23.61 seconds
Started Aug 25 12:33:09 PM UTC 24
Finished Aug 25 12:33:34 PM UTC 24
Peak memory 262824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077502189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1077502189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_intg_err.965684195
Short name T203
Test name
Test status
Simulation time 1646574014 ps
CPU time 59.37 seconds
Started Aug 25 12:33:30 PM UTC 24
Finished Aug 25 12:34:32 PM UTC 24
Peak memory 252440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965684195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.965684195
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.764358314
Short name T728
Test name
Test status
Simulation time 261918584 ps
CPU time 9.96 seconds
Started Aug 25 12:41:36 PM UTC 24
Finished Aug 25 12:41:47 PM UTC 24
Peak memory 252704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764358314 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_mem_
rw_with_rand_reset.764358314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_rw.2421964899
Short name T727
Test name
Test status
Simulation time 763910056 ps
CPU time 12.78 seconds
Started Aug 25 12:41:32 PM UTC 24
Finished Aug 25 12:41:46 PM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421964899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2421964899
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_intr_test.3140247536
Short name T723
Test name
Test status
Simulation time 9903934 ps
CPU time 2.04 seconds
Started Aug 25 12:41:32 PM UTC 24
Finished Aug 25 12:41:35 PM UTC 24
Peak memory 250408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140247536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3140247536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.233535944
Short name T733
Test name
Test status
Simulation time 178105623 ps
CPU time 37.52 seconds
Started Aug 25 12:41:33 PM UTC 24
Finished Aug 25 12:42:12 PM UTC 24
Peak memory 262676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233535944 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outstanding.233535944
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1053086049
Short name T194
Test name
Test status
Simulation time 27036044789 ps
CPU time 863.9 seconds
Started Aug 25 12:41:10 PM UTC 24
Finished Aug 25 12:55:47 PM UTC 24
Peak memory 283552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053086049 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shad
ow_reg_errors_with_csr_rw.1053086049
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_errors.1281430856
Short name T732
Test name
Test status
Simulation time 302381394 ps
CPU time 37.3 seconds
Started Aug 25 12:41:29 PM UTC 24
Finished Aug 25 12:42:07 PM UTC 24
Peak memory 268896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281430856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1281430856
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3028482880
Short name T734
Test name
Test status
Simulation time 172029473 ps
CPU time 22.1 seconds
Started Aug 25 12:41:49 PM UTC 24
Finished Aug 25 12:42:13 PM UTC 24
Peak memory 254544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028482880 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_mem
_rw_with_rand_reset.3028482880
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_rw.1462289310
Short name T731
Test name
Test status
Simulation time 97401795 ps
CPU time 11.7 seconds
Started Aug 25 12:41:47 PM UTC 24
Finished Aug 25 12:42:00 PM UTC 24
Peak memory 252380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462289310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1462289310
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_intr_test.559936624
Short name T729
Test name
Test status
Simulation time 6047513 ps
CPU time 2.27 seconds
Started Aug 25 12:41:45 PM UTC 24
Finished Aug 25 12:41:48 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559936624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.559936624
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3099601646
Short name T738
Test name
Test status
Simulation time 1346371140 ps
CPU time 32.63 seconds
Started Aug 25 12:41:48 PM UTC 24
Finished Aug 25 12:42:22 PM UTC 24
Peak memory 260764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099601646 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outstanding.3099601646
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.387260219
Short name T181
Test name
Test status
Simulation time 10788643791 ps
CPU time 162.59 seconds
Started Aug 25 12:41:38 PM UTC 24
Finished Aug 25 12:44:24 PM UTC 24
Peak memory 269288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387260219 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.387260219
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.201017840
Short name T192
Test name
Test status
Simulation time 4778111255 ps
CPU time 1019.99 seconds
Started Aug 25 12:41:37 PM UTC 24
Finished Aug 25 12:58:53 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201017840 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shado
w_reg_errors_with_csr_rw.201017840
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_errors.3910721958
Short name T730
Test name
Test status
Simulation time 57647403 ps
CPU time 13.58 seconds
Started Aug 25 12:41:42 PM UTC 24
Finished Aug 25 12:41:56 PM UTC 24
Peak memory 262824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910721958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3910721958
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2137995580
Short name T741
Test name
Test status
Simulation time 542237066 ps
CPU time 7.29 seconds
Started Aug 25 12:42:16 PM UTC 24
Finished Aug 25 12:42:25 PM UTC 24
Peak memory 252500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137995580 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_mem
_rw_with_rand_reset.2137995580
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_rw.1017384666
Short name T740
Test name
Test status
Simulation time 52911799 ps
CPU time 7.62 seconds
Started Aug 25 12:42:14 PM UTC 24
Finished Aug 25 12:42:23 PM UTC 24
Peak memory 250328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017384666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1017384666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.349290180
Short name T749
Test name
Test status
Simulation time 2068750893 ps
CPU time 70.05 seconds
Started Aug 25 12:42:15 PM UTC 24
Finished Aug 25 12:43:27 PM UTC 24
Peak memory 262812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349290180 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outstanding.349290180
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3341360808
Short name T198
Test name
Test status
Simulation time 31224121608 ps
CPU time 1889.77 seconds
Started Aug 25 12:41:52 PM UTC 24
Finished Aug 25 01:13:48 PM UTC 24
Peak memory 279464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341360808 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shad
ow_reg_errors_with_csr_rw.3341360808
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_errors.1271550666
Short name T736
Test name
Test status
Simulation time 119993165 ps
CPU time 13.71 seconds
Started Aug 25 12:42:01 PM UTC 24
Finished Aug 25 12:42:16 PM UTC 24
Peak memory 266848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271550666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1271550666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1963173480
Short name T735
Test name
Test status
Simulation time 21904692 ps
CPU time 3.83 seconds
Started Aug 25 12:42:09 PM UTC 24
Finished Aug 25 12:42:14 PM UTC 24
Peak memory 250524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963173480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1963173480
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3871733024
Short name T745
Test name
Test status
Simulation time 340231934 ps
CPU time 17.62 seconds
Started Aug 25 12:42:31 PM UTC 24
Finished Aug 25 12:42:51 PM UTC 24
Peak memory 268956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871733024 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_mem
_rw_with_rand_reset.3871733024
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_rw.1366127234
Short name T742
Test name
Test status
Simulation time 123261633 ps
CPU time 8.63 seconds
Started Aug 25 12:42:26 PM UTC 24
Finished Aug 25 12:42:36 PM UTC 24
Peak memory 252372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366127234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1366127234
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_intr_test.2997855707
Short name T400
Test name
Test status
Simulation time 26185422 ps
CPU time 2.36 seconds
Started Aug 25 12:42:24 PM UTC 24
Finished Aug 25 12:42:27 PM UTC 24
Peak memory 250408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997855707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2997855707
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.998351589
Short name T743
Test name
Test status
Simulation time 159617399 ps
CPU time 18.43 seconds
Started Aug 25 12:42:28 PM UTC 24
Finished Aug 25 12:42:48 PM UTC 24
Peak memory 260628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998351589 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outstanding.998351589
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3867503889
Short name T173
Test name
Test status
Simulation time 2537888185 ps
CPU time 412.99 seconds
Started Aug 25 12:42:21 PM UTC 24
Finished Aug 25 12:49:20 PM UTC 24
Peak memory 285600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867503889 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.3867503889
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_errors.2998816632
Short name T744
Test name
Test status
Simulation time 1836595112 ps
CPU time 24.7 seconds
Started Aug 25 12:42:23 PM UTC 24
Finished Aug 25 12:42:49 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998816632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2998816632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.303094044
Short name T750
Test name
Test status
Simulation time 130168125 ps
CPU time 13.89 seconds
Started Aug 25 12:43:13 PM UTC 24
Finished Aug 25 12:43:29 PM UTC 24
Peak memory 252576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303094044 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_mem_
rw_with_rand_reset.303094044
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_rw.950514780
Short name T747
Test name
Test status
Simulation time 201738750 ps
CPU time 9.55 seconds
Started Aug 25 12:42:55 PM UTC 24
Finished Aug 25 12:43:06 PM UTC 24
Peak memory 252376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950514780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.950514780
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_intr_test.975180172
Short name T746
Test name
Test status
Simulation time 6774616 ps
CPU time 2.29 seconds
Started Aug 25 12:42:51 PM UTC 24
Finished Aug 25 12:42:54 PM UTC 24
Peak memory 250244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975180172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.975180172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1765634710
Short name T752
Test name
Test status
Simulation time 175077607 ps
CPU time 35.47 seconds
Started Aug 25 12:43:06 PM UTC 24
Finished Aug 25 12:43:43 PM UTC 24
Peak memory 262812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765634710 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outstanding.1765634710
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1675760406
Short name T170
Test name
Test status
Simulation time 2110062978 ps
CPU time 234.53 seconds
Started Aug 25 12:42:49 PM UTC 24
Finished Aug 25 12:46:47 PM UTC 24
Peak memory 279328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675760406 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.1675760406
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1757743343
Short name T191
Test name
Test status
Simulation time 2171488504 ps
CPU time 451.29 seconds
Started Aug 25 12:42:37 PM UTC 24
Finished Aug 25 12:50:15 PM UTC 24
Peak memory 279392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757743343 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shad
ow_reg_errors_with_csr_rw.1757743343
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_errors.903015691
Short name T748
Test name
Test status
Simulation time 381294512 ps
CPU time 21.23 seconds
Started Aug 25 12:42:50 PM UTC 24
Finished Aug 25 12:43:12 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903015691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.903015691
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4052746858
Short name T756
Test name
Test status
Simulation time 196667842 ps
CPU time 26.49 seconds
Started Aug 25 12:43:44 PM UTC 24
Finished Aug 25 12:44:12 PM UTC 24
Peak memory 264788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052746858 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_mem
_rw_with_rand_reset.4052746858
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_rw.3269233167
Short name T753
Test name
Test status
Simulation time 64427736 ps
CPU time 5.07 seconds
Started Aug 25 12:43:38 PM UTC 24
Finished Aug 25 12:43:44 PM UTC 24
Peak memory 250460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269233167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3269233167
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_intr_test.1962385281
Short name T751
Test name
Test status
Simulation time 9818633 ps
CPU time 2.26 seconds
Started Aug 25 12:43:34 PM UTC 24
Finished Aug 25 12:43:37 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962385281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1962385281
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1344298378
Short name T755
Test name
Test status
Simulation time 95770611 ps
CPU time 16.11 seconds
Started Aug 25 12:43:43 PM UTC 24
Finished Aug 25 12:44:00 PM UTC 24
Peak memory 262672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344298378 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outstanding.1344298378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.4076775488
Short name T178
Test name
Test status
Simulation time 3807621114 ps
CPU time 236.38 seconds
Started Aug 25 12:43:21 PM UTC 24
Finished Aug 25 12:47:22 PM UTC 24
Peak memory 279528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076775488 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.4076775488
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_errors.1229562716
Short name T754
Test name
Test status
Simulation time 947974378 ps
CPU time 24.83 seconds
Started Aug 25 12:43:28 PM UTC 24
Finished Aug 25 12:43:55 PM UTC 24
Peak memory 262888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229562716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1229562716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1351200639
Short name T760
Test name
Test status
Simulation time 66441259 ps
CPU time 13.07 seconds
Started Aug 25 12:44:30 PM UTC 24
Finished Aug 25 12:44:44 PM UTC 24
Peak memory 264784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351200639 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_mem
_rw_with_rand_reset.1351200639
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.2005073733
Short name T759
Test name
Test status
Simulation time 81030979 ps
CPU time 7.47 seconds
Started Aug 25 12:44:27 PM UTC 24
Finished Aug 25 12:44:35 PM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005073733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2005073733
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.687676358
Short name T758
Test name
Test status
Simulation time 12583210 ps
CPU time 2.66 seconds
Started Aug 25 12:44:25 PM UTC 24
Finished Aug 25 12:44:28 PM UTC 24
Peak memory 250536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687676358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.687676358
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.184491779
Short name T761
Test name
Test status
Simulation time 93139963 ps
CPU time 24.52 seconds
Started Aug 25 12:44:29 PM UTC 24
Finished Aug 25 12:44:55 PM UTC 24
Peak memory 262748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184491779 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outstanding.184491779
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1510056630
Short name T187
Test name
Test status
Simulation time 12148582758 ps
CPU time 826.5 seconds
Started Aug 25 12:43:45 PM UTC 24
Finished Aug 25 12:57:44 PM UTC 24
Peak memory 279528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510056630 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shad
ow_reg_errors_with_csr_rw.1510056630
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.99708743
Short name T757
Test name
Test status
Simulation time 427563064 ps
CPU time 23.53 seconds
Started Aug 25 12:44:01 PM UTC 24
Finished Aug 25 12:44:26 PM UTC 24
Peak memory 262824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99708743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handle
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.99708743
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2793893972
Short name T766
Test name
Test status
Simulation time 62469006 ps
CPU time 16.83 seconds
Started Aug 25 12:45:10 PM UTC 24
Finished Aug 25 12:45:28 PM UTC 24
Peak memory 262736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793893972 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_mem
_rw_with_rand_reset.2793893972
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.3048048275
Short name T764
Test name
Test status
Simulation time 195306909 ps
CPU time 8.5 seconds
Started Aug 25 12:45:00 PM UTC 24
Finished Aug 25 12:45:09 PM UTC 24
Peak memory 250220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048048275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3048048275
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.958584350
Short name T763
Test name
Test status
Simulation time 36450442 ps
CPU time 2.13 seconds
Started Aug 25 12:44:56 PM UTC 24
Finished Aug 25 12:44:59 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958584350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.958584350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3075916695
Short name T767
Test name
Test status
Simulation time 886782622 ps
CPU time 37.23 seconds
Started Aug 25 12:45:00 PM UTC 24
Finished Aug 25 12:45:39 PM UTC 24
Peak memory 260628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075916695 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outstanding.3075916695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.649497008
Short name T177
Test name
Test status
Simulation time 4467315050 ps
CPU time 294.06 seconds
Started Aug 25 12:44:40 PM UTC 24
Finished Aug 25 12:49:39 PM UTC 24
Peak memory 279460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649497008 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.649497008
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.1043282994
Short name T762
Test name
Test status
Simulation time 680200654 ps
CPU time 14.88 seconds
Started Aug 25 12:44:42 PM UTC 24
Finished Aug 25 12:44:58 PM UTC 24
Peak memory 266852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043282994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1043282994
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2761122304
Short name T765
Test name
Test status
Simulation time 159851962 ps
CPU time 31.16 seconds
Started Aug 25 12:44:45 PM UTC 24
Finished Aug 25 12:45:18 PM UTC 24
Peak memory 262676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761122304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2761122304
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1560884851
Short name T771
Test name
Test status
Simulation time 86552837 ps
CPU time 9.75 seconds
Started Aug 25 12:46:17 PM UTC 24
Finished Aug 25 12:46:28 PM UTC 24
Peak memory 252636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560884851 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_mem
_rw_with_rand_reset.1560884851
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.4041411206
Short name T770
Test name
Test status
Simulation time 33373783 ps
CPU time 5.02 seconds
Started Aug 25 12:46:10 PM UTC 24
Finished Aug 25 12:46:16 PM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041411206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.4041411206
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.592424871
Short name T769
Test name
Test status
Simulation time 7283813 ps
CPU time 2.06 seconds
Started Aug 25 12:46:06 PM UTC 24
Finished Aug 25 12:46:09 PM UTC 24
Peak memory 248552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592424871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.592424871
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3830395199
Short name T774
Test name
Test status
Simulation time 517039744 ps
CPU time 37.93 seconds
Started Aug 25 12:46:16 PM UTC 24
Finished Aug 25 12:46:56 PM UTC 24
Peak memory 262748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830395199 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outstanding.3830395199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.701701896
Short name T185
Test name
Test status
Simulation time 10076405164 ps
CPU time 273.7 seconds
Started Aug 25 12:45:29 PM UTC 24
Finished Aug 25 12:50:08 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701701896 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.701701896
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.1182212808
Short name T768
Test name
Test status
Simulation time 148222547 ps
CPU time 8.39 seconds
Started Aug 25 12:45:39 PM UTC 24
Finished Aug 25 12:45:49 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182212808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1182212808
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3078850963
Short name T778
Test name
Test status
Simulation time 28521823 ps
CPU time 8.59 seconds
Started Aug 25 12:46:52 PM UTC 24
Finished Aug 25 12:47:02 PM UTC 24
Peak memory 252636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078850963 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_mem
_rw_with_rand_reset.3078850963
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.3988019588
Short name T775
Test name
Test status
Simulation time 21209674 ps
CPU time 6.26 seconds
Started Aug 25 12:46:50 PM UTC 24
Finished Aug 25 12:46:58 PM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988019588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3988019588
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.1940143545
Short name T773
Test name
Test status
Simulation time 8731000 ps
CPU time 1.97 seconds
Started Aug 25 12:46:49 PM UTC 24
Finished Aug 25 12:46:52 PM UTC 24
Peak memory 248780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940143545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1940143545
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2729659853
Short name T792
Test name
Test status
Simulation time 692309704 ps
CPU time 30.69 seconds
Started Aug 25 12:46:50 PM UTC 24
Finished Aug 25 12:47:22 PM UTC 24
Peak memory 260764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729659853 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outstanding.2729659853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1297191659
Short name T176
Test name
Test status
Simulation time 7112541860 ps
CPU time 231.59 seconds
Started Aug 25 12:46:29 PM UTC 24
Finished Aug 25 12:50:26 PM UTC 24
Peak memory 269288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297191659 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.1297191659
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2169697093
Short name T410
Test name
Test status
Simulation time 14565808918 ps
CPU time 1672.5 seconds
Started Aug 25 12:46:18 PM UTC 24
Finished Aug 25 01:14:35 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169697093 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shad
ow_reg_errors_with_csr_rw.2169697093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.266437887
Short name T772
Test name
Test status
Simulation time 51792020 ps
CPU time 5.94 seconds
Started Aug 25 12:46:42 PM UTC 24
Finished Aug 25 12:46:49 PM UTC 24
Peak memory 262888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266437887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.266437887
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3181380515
Short name T808
Test name
Test status
Simulation time 2763976730 ps
CPU time 53.02 seconds
Started Aug 25 12:46:48 PM UTC 24
Finished Aug 25 12:47:43 PM UTC 24
Peak memory 250512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181380515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3181380515
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1970392815
Short name T240
Test name
Test status
Simulation time 1130955405 ps
CPU time 259.19 seconds
Started Aug 25 12:35:38 PM UTC 24
Finished Aug 25 12:40:02 PM UTC 24
Peak memory 252456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970392815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1970392815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1595562511
Short name T737
Test name
Test status
Simulation time 56836989527 ps
CPU time 396.49 seconds
Started Aug 25 12:35:37 PM UTC 24
Finished Aug 25 12:42:20 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595562511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1595562511
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1473697721
Short name T230
Test name
Test status
Simulation time 52799573 ps
CPU time 7.56 seconds
Started Aug 25 12:35:27 PM UTC 24
Finished Aug 25 12:35:36 PM UTC 24
Peak memory 262624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473697721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1473697721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.4262152476
Short name T407
Test name
Test status
Simulation time 345463734 ps
CPU time 16.03 seconds
Started Aug 25 12:36:13 PM UTC 24
Finished Aug 25 12:36:30 PM UTC 24
Peak memory 266840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262152476 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_
rw_with_rand_reset.4262152476
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_rw.2076622581
Short name T243
Test name
Test status
Simulation time 33965393 ps
CPU time 6.7 seconds
Started Aug 25 12:35:28 PM UTC 24
Finished Aug 25 12:35:36 PM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076622581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2076622581
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_intr_test.2860802905
Short name T259
Test name
Test status
Simulation time 23313653 ps
CPU time 2.36 seconds
Started Aug 25 12:35:24 PM UTC 24
Finished Aug 25 12:35:28 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860802905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2860802905
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2185684500
Short name T231
Test name
Test status
Simulation time 91364308 ps
CPU time 27.42 seconds
Started Aug 25 12:35:43 PM UTC 24
Finished Aug 25 12:36:12 PM UTC 24
Peak memory 260628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185684500 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.2185684500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_errors.4054919778
Short name T703
Test name
Test status
Simulation time 850811985 ps
CPU time 31.75 seconds
Started Aug 25 12:34:50 PM UTC 24
Finished Aug 25 12:35:24 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054919778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.4054919778
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2013587271
Short name T204
Test name
Test status
Simulation time 490105673 ps
CPU time 70.95 seconds
Started Aug 25 12:35:20 PM UTC 24
Finished Aug 25 12:36:33 PM UTC 24
Peak memory 252444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013587271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2013587271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.1965575314
Short name T776
Test name
Test status
Simulation time 17887972 ps
CPU time 2.16 seconds
Started Aug 25 12:46:57 PM UTC 24
Finished Aug 25 12:47:00 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965575314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1965575314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/20.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.2210687492
Short name T777
Test name
Test status
Simulation time 17247389 ps
CPU time 2.04 seconds
Started Aug 25 12:46:59 PM UTC 24
Finished Aug 25 12:47:02 PM UTC 24
Peak memory 250536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210687492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2210687492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/21.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.2591534341
Short name T779
Test name
Test status
Simulation time 8699688 ps
CPU time 2.5 seconds
Started Aug 25 12:47:01 PM UTC 24
Finished Aug 25 12:47:04 PM UTC 24
Peak memory 250408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591534341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2591534341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/22.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.3625953746
Short name T781
Test name
Test status
Simulation time 11012129 ps
CPU time 2.73 seconds
Started Aug 25 12:47:03 PM UTC 24
Finished Aug 25 12:47:07 PM UTC 24
Peak memory 248308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625953746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3625953746
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/23.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.1217699811
Short name T780
Test name
Test status
Simulation time 11182877 ps
CPU time 2.24 seconds
Started Aug 25 12:47:03 PM UTC 24
Finished Aug 25 12:47:06 PM UTC 24
Peak memory 250428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217699811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1217699811
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/24.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.3797466044
Short name T782
Test name
Test status
Simulation time 10981221 ps
CPU time 1.95 seconds
Started Aug 25 12:47:05 PM UTC 24
Finished Aug 25 12:47:08 PM UTC 24
Peak memory 248780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797466044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3797466044
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/25.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.2891616961
Short name T784
Test name
Test status
Simulation time 12467863 ps
CPU time 2.82 seconds
Started Aug 25 12:47:07 PM UTC 24
Finished Aug 25 12:47:11 PM UTC 24
Peak memory 250396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891616961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2891616961
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/26.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.2375803907
Short name T783
Test name
Test status
Simulation time 17474265 ps
CPU time 2.27 seconds
Started Aug 25 12:47:07 PM UTC 24
Finished Aug 25 12:47:11 PM UTC 24
Peak memory 250384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375803907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2375803907
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/27.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.2986657152
Short name T785
Test name
Test status
Simulation time 24903715 ps
CPU time 2.51 seconds
Started Aug 25 12:47:09 PM UTC 24
Finished Aug 25 12:47:13 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986657152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2986657152
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/28.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.4154242
Short name T787
Test name
Test status
Simulation time 7581814 ps
CPU time 2.44 seconds
Started Aug 25 12:47:12 PM UTC 24
Finished Aug 25 12:47:15 PM UTC 24
Peak memory 250332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_S
EQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.4154242
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/29.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1914332293
Short name T235
Test name
Test status
Simulation time 2475148923 ps
CPU time 124.02 seconds
Started Aug 25 12:36:51 PM UTC 24
Finished Aug 25 12:38:58 PM UTC 24
Peak memory 252648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914332293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1914332293
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1999797310
Short name T739
Test name
Test status
Simulation time 6805788064 ps
CPU time 330.87 seconds
Started Aug 25 12:36:46 PM UTC 24
Finished Aug 25 12:42:22 PM UTC 24
Peak memory 252512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999797310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1999797310
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2404087394
Short name T265
Test name
Test status
Simulation time 129441056 ps
CPU time 19.39 seconds
Started Aug 25 12:36:39 PM UTC 24
Finished Aug 25 12:36:59 PM UTC 24
Peak memory 262616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404087394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2404087394
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1661773830
Short name T408
Test name
Test status
Simulation time 247724043 ps
CPU time 19.72 seconds
Started Aug 25 12:37:26 PM UTC 24
Finished Aug 25 12:37:48 PM UTC 24
Peak memory 262880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661773830 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_
rw_with_rand_reset.1661773830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_rw.105735379
Short name T705
Test name
Test status
Simulation time 97745526 ps
CPU time 8.26 seconds
Started Aug 25 12:36:41 PM UTC 24
Finished Aug 25 12:36:50 PM UTC 24
Peak memory 252444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105735379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.105735379
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_intr_test.2197452040
Short name T398
Test name
Test status
Simulation time 6444178 ps
CPU time 2.24 seconds
Started Aug 25 12:36:35 PM UTC 24
Finished Aug 25 12:36:38 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197452040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2197452040
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.554496698
Short name T234
Test name
Test status
Simulation time 627997887 ps
CPU time 77.24 seconds
Started Aug 25 12:37:00 PM UTC 24
Finished Aug 25 12:38:20 PM UTC 24
Peak memory 260628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554496698 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.554496698
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1030036898
Short name T174
Test name
Test status
Simulation time 2526531328 ps
CPU time 293.12 seconds
Started Aug 25 12:36:32 PM UTC 24
Finished Aug 25 12:41:31 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030036898 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.1030036898
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_errors.2238463410
Short name T704
Test name
Test status
Simulation time 100502208 ps
CPU time 11.68 seconds
Started Aug 25 12:36:32 PM UTC 24
Finished Aug 25 12:36:45 PM UTC 24
Peak memory 262952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238463410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2238463410
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.1837342697
Short name T786
Test name
Test status
Simulation time 8423528 ps
CPU time 2.32 seconds
Started Aug 25 12:47:12 PM UTC 24
Finished Aug 25 12:47:15 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837342697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1837342697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/30.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.3948609649
Short name T788
Test name
Test status
Simulation time 11958798 ps
CPU time 2.31 seconds
Started Aug 25 12:47:14 PM UTC 24
Finished Aug 25 12:47:17 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948609649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3948609649
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/31.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.2643296823
Short name T790
Test name
Test status
Simulation time 111201970 ps
CPU time 2.24 seconds
Started Aug 25 12:47:16 PM UTC 24
Finished Aug 25 12:47:19 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643296823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2643296823
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/32.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.3291717356
Short name T789
Test name
Test status
Simulation time 21554020 ps
CPU time 1.97 seconds
Started Aug 25 12:47:16 PM UTC 24
Finished Aug 25 12:47:19 PM UTC 24
Peak memory 248716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291717356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3291717356
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/33.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.3347745154
Short name T791
Test name
Test status
Simulation time 9481369 ps
CPU time 1.92 seconds
Started Aug 25 12:47:18 PM UTC 24
Finished Aug 25 12:47:21 PM UTC 24
Peak memory 248844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347745154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3347745154
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/34.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.3247360696
Short name T794
Test name
Test status
Simulation time 11294751 ps
CPU time 2.66 seconds
Started Aug 25 12:47:20 PM UTC 24
Finished Aug 25 12:47:24 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247360696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3247360696
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/35.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.1745096557
Short name T793
Test name
Test status
Simulation time 13454060 ps
CPU time 2.65 seconds
Started Aug 25 12:47:20 PM UTC 24
Finished Aug 25 12:47:24 PM UTC 24
Peak memory 248288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745096557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1745096557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/36.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.2907096246
Short name T795
Test name
Test status
Simulation time 15442945 ps
CPU time 2.13 seconds
Started Aug 25 12:47:22 PM UTC 24
Finished Aug 25 12:47:25 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907096246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2907096246
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/37.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.771876879
Short name T796
Test name
Test status
Simulation time 8665122 ps
CPU time 2.19 seconds
Started Aug 25 12:47:23 PM UTC 24
Finished Aug 25 12:47:26 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771876879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.771876879
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/38.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.725560601
Short name T797
Test name
Test status
Simulation time 8875195 ps
CPU time 2.29 seconds
Started Aug 25 12:47:23 PM UTC 24
Finished Aug 25 12:47:26 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725560601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.725560601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/39.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.737843920
Short name T725
Test name
Test status
Simulation time 4409820398 ps
CPU time 213.08 seconds
Started Aug 25 12:38:05 PM UTC 24
Finished Aug 25 12:41:42 PM UTC 24
Peak memory 252504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737843920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/al
ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.737843920
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.126765411
Short name T715
Test name
Test status
Simulation time 6809063552 ps
CPU time 146.44 seconds
Started Aug 25 12:38:01 PM UTC 24
Finished Aug 25 12:40:31 PM UTC 24
Peak memory 250452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126765411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/al
ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.126765411
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1994358004
Short name T706
Test name
Test status
Simulation time 69808120 ps
CPU time 12 seconds
Started Aug 25 12:37:53 PM UTC 24
Finished Aug 25 12:38:07 PM UTC 24
Peak memory 262624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994358004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1994358004
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.971917944
Short name T412
Test name
Test status
Simulation time 79742883 ps
CPU time 10.06 seconds
Started Aug 25 12:38:11 PM UTC 24
Finished Aug 25 12:38:22 PM UTC 24
Peak memory 252576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971917944 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_r
w_with_rand_reset.971917944
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2992044196
Short name T238
Test name
Test status
Simulation time 517773229 ps
CPU time 66.17 seconds
Started Aug 25 12:38:08 PM UTC 24
Finished Aug 25 12:39:16 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992044196 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.2992044196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2355248728
Short name T184
Test name
Test status
Simulation time 3845119396 ps
CPU time 223.39 seconds
Started Aug 25 12:37:40 PM UTC 24
Finished Aug 25 12:41:27 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355248728 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.2355248728
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_errors.3748281935
Short name T707
Test name
Test status
Simulation time 824073884 ps
CPU time 23.06 seconds
Started Aug 25 12:37:46 PM UTC 24
Finished Aug 25 12:38:10 PM UTC 24
Peak memory 262944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748281935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3748281935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.3189402487
Short name T800
Test name
Test status
Simulation time 9686375 ps
CPU time 2.23 seconds
Started Aug 25 12:47:25 PM UTC 24
Finished Aug 25 12:47:28 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189402487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3189402487
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/40.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.215791913
Short name T799
Test name
Test status
Simulation time 8398202 ps
CPU time 2.16 seconds
Started Aug 25 12:47:25 PM UTC 24
Finished Aug 25 12:47:28 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215791913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.215791913
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/41.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.2420415297
Short name T798
Test name
Test status
Simulation time 9868651 ps
CPU time 2.02 seconds
Started Aug 25 12:47:25 PM UTC 24
Finished Aug 25 12:47:28 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420415297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2420415297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/42.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.2590213360
Short name T801
Test name
Test status
Simulation time 11807584 ps
CPU time 2.26 seconds
Started Aug 25 12:47:26 PM UTC 24
Finished Aug 25 12:47:30 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590213360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2590213360
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/43.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.2705483963
Short name T802
Test name
Test status
Simulation time 19435005 ps
CPU time 2.41 seconds
Started Aug 25 12:47:27 PM UTC 24
Finished Aug 25 12:47:31 PM UTC 24
Peak memory 250408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705483963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2705483963
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/44.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.1947695073
Short name T804
Test name
Test status
Simulation time 6150474 ps
CPU time 2.31 seconds
Started Aug 25 12:47:30 PM UTC 24
Finished Aug 25 12:47:33 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947695073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1947695073
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/45.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.3019204709
Short name T805
Test name
Test status
Simulation time 19156825 ps
CPU time 2.32 seconds
Started Aug 25 12:47:30 PM UTC 24
Finished Aug 25 12:47:33 PM UTC 24
Peak memory 250344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019204709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3019204709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/46.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.3000190624
Short name T803
Test name
Test status
Simulation time 9651702 ps
CPU time 2.13 seconds
Started Aug 25 12:47:30 PM UTC 24
Finished Aug 25 12:47:33 PM UTC 24
Peak memory 248424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000190624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3000190624
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/47.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.2974030481
Short name T806
Test name
Test status
Simulation time 19116258 ps
CPU time 2.22 seconds
Started Aug 25 12:47:31 PM UTC 24
Finished Aug 25 12:47:34 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974030481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2974030481
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/48.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.900251244
Short name T807
Test name
Test status
Simulation time 8342022 ps
CPU time 1.89 seconds
Started Aug 25 12:47:32 PM UTC 24
Finished Aug 25 12:47:35 PM UTC 24
Peak memory 248716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900251244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.900251244
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/49.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3700154162
Short name T709
Test name
Test status
Simulation time 70351472 ps
CPU time 10.33 seconds
Started Aug 25 12:38:48 PM UTC 24
Finished Aug 25 12:38:59 PM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700154162 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_mem_
rw_with_rand_reset.3700154162
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_rw.1571076281
Short name T411
Test name
Test status
Simulation time 183330644 ps
CPU time 12.7 seconds
Started Aug 25 12:38:34 PM UTC 24
Finished Aug 25 12:38:49 PM UTC 24
Peak memory 250396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571076281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1571076281
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_intr_test.2172298390
Short name T402
Test name
Test status
Simulation time 9585945 ps
CPU time 2.17 seconds
Started Aug 25 12:38:30 PM UTC 24
Finished Aug 25 12:38:33 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172298390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2172298390
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4204190483
Short name T267
Test name
Test status
Simulation time 1439501068 ps
CPU time 77.98 seconds
Started Aug 25 12:38:44 PM UTC 24
Finished Aug 25 12:40:05 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204190483 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outstanding.4204190483
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.961644355
Short name T168
Test name
Test status
Simulation time 778214243 ps
CPU time 186.32 seconds
Started Aug 25 12:38:15 PM UTC 24
Finished Aug 25 12:41:25 PM UTC 24
Peak memory 269228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961644355 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.961644355
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3975778604
Short name T409
Test name
Test status
Simulation time 7950832798 ps
CPU time 824.41 seconds
Started Aug 25 12:38:12 PM UTC 24
Finished Aug 25 12:52:08 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975778604 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shado
w_reg_errors_with_csr_rw.3975778604
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_errors.215877486
Short name T708
Test name
Test status
Simulation time 96296229 ps
CPU time 7.49 seconds
Started Aug 25 12:38:21 PM UTC 24
Finished Aug 25 12:38:30 PM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215877486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.215877486
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2697897749
Short name T710
Test name
Test status
Simulation time 82505683 ps
CPU time 12.84 seconds
Started Aug 25 12:39:30 PM UTC 24
Finished Aug 25 12:39:44 PM UTC 24
Peak memory 252504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697897749 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_mem_
rw_with_rand_reset.2697897749
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_rw.1317471043
Short name T406
Test name
Test status
Simulation time 246221203 ps
CPU time 7.41 seconds
Started Aug 25 12:39:19 PM UTC 24
Finished Aug 25 12:39:28 PM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317471043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1317471043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_intr_test.3154396344
Short name T401
Test name
Test status
Simulation time 27547993 ps
CPU time 3.38 seconds
Started Aug 25 12:39:16 PM UTC 24
Finished Aug 25 12:39:21 PM UTC 24
Peak memory 250536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154396344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3154396344
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2526075364
Short name T239
Test name
Test status
Simulation time 182493074 ps
CPU time 21.41 seconds
Started Aug 25 12:39:22 PM UTC 24
Finished Aug 25 12:39:44 PM UTC 24
Peak memory 260768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526075364 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outstanding.2526075364
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1788960070
Short name T197
Test name
Test status
Simulation time 15803676227 ps
CPU time 1797.85 seconds
Started Aug 25 12:38:51 PM UTC 24
Finished Aug 25 01:09:15 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788960070 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shado
w_reg_errors_with_csr_rw.1788960070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_errors.758924813
Short name T272
Test name
Test status
Simulation time 305449987 ps
CPU time 9.9 seconds
Started Aug 25 12:39:00 PM UTC 24
Finished Aug 25 12:39:11 PM UTC 24
Peak memory 262816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758924813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.758924813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1899645012
Short name T274
Test name
Test status
Simulation time 307354225 ps
CPU time 19.49 seconds
Started Aug 25 12:40:07 PM UTC 24
Finished Aug 25 12:40:28 PM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899645012 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_mem_
rw_with_rand_reset.1899645012
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_rw.3143054990
Short name T713
Test name
Test status
Simulation time 365014487 ps
CPU time 12.53 seconds
Started Aug 25 12:40:06 PM UTC 24
Finished Aug 25 12:40:19 PM UTC 24
Peak memory 252372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143054990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3143054990
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_intr_test.1044858553
Short name T403
Test name
Test status
Simulation time 6131372 ps
CPU time 2.07 seconds
Started Aug 25 12:40:03 PM UTC 24
Finished Aug 25 12:40:06 PM UTC 24
Peak memory 248488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044858553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1044858553
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.4271828495
Short name T717
Test name
Test status
Simulation time 331422102 ps
CPU time 38.91 seconds
Started Aug 25 12:40:07 PM UTC 24
Finished Aug 25 12:40:47 PM UTC 24
Peak memory 260704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271828495 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outstanding.4271828495
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2865936810
Short name T175
Test name
Test status
Simulation time 7588982730 ps
CPU time 278.69 seconds
Started Aug 25 12:39:45 PM UTC 24
Finished Aug 25 12:44:29 PM UTC 24
Peak memory 279592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865936810 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.2865936810
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2878536328
Short name T193
Test name
Test status
Simulation time 6396043936 ps
CPU time 861.82 seconds
Started Aug 25 12:39:44 PM UTC 24
Finished Aug 25 12:54:19 PM UTC 24
Peak memory 285600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878536328 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shado
w_reg_errors_with_csr_rw.2878536328
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_errors.1761012325
Short name T711
Test name
Test status
Simulation time 133592815 ps
CPU time 10.13 seconds
Started Aug 25 12:39:45 PM UTC 24
Finished Aug 25 12:39:57 PM UTC 24
Peak memory 266984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761012325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1761012325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3820614718
Short name T712
Test name
Test status
Simulation time 58812669 ps
CPU time 6.17 seconds
Started Aug 25 12:39:57 PM UTC 24
Finished Aug 25 12:40:05 PM UTC 24
Peak memory 250392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820614718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3820614718
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3696854553
Short name T718
Test name
Test status
Simulation time 134159238 ps
CPU time 16.87 seconds
Started Aug 25 12:40:34 PM UTC 24
Finished Aug 25 12:40:52 PM UTC 24
Peak memory 268888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696854553 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_mem_
rw_with_rand_reset.3696854553
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_rw.1022006289
Short name T716
Test name
Test status
Simulation time 25884547 ps
CPU time 6.05 seconds
Started Aug 25 12:40:29 PM UTC 24
Finished Aug 25 12:40:37 PM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022006289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1022006289
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_intr_test.1289534423
Short name T405
Test name
Test status
Simulation time 11908770 ps
CPU time 2.33 seconds
Started Aug 25 12:40:29 PM UTC 24
Finished Aug 25 12:40:33 PM UTC 24
Peak memory 250408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289534423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1289534423
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.4276709865
Short name T724
Test name
Test status
Simulation time 526452442 ps
CPU time 64.14 seconds
Started Aug 25 12:40:31 PM UTC 24
Finished Aug 25 12:41:38 PM UTC 24
Peak memory 262680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276709865 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outstanding.4276709865
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3770223848
Short name T195
Test name
Test status
Simulation time 26835440765 ps
CPU time 817.9 seconds
Started Aug 25 12:40:10 PM UTC 24
Finished Aug 25 12:54:00 PM UTC 24
Peak memory 281504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770223848 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shado
w_reg_errors_with_csr_rw.3770223848
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_errors.2067775627
Short name T719
Test name
Test status
Simulation time 543858601 ps
CPU time 36.71 seconds
Started Aug 25 12:40:25 PM UTC 24
Finished Aug 25 12:41:03 PM UTC 24
Peak memory 262824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067775627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2067775627
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2155306221
Short name T211
Test name
Test status
Simulation time 2796112083 ps
CPU time 63.67 seconds
Started Aug 25 12:40:25 PM UTC 24
Finished Aug 25 12:41:31 PM UTC 24
Peak memory 252572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155306221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2155306221
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3518878325
Short name T722
Test name
Test status
Simulation time 2167956747 ps
CPU time 22.24 seconds
Started Aug 25 12:41:04 PM UTC 24
Finished Aug 25 12:41:28 PM UTC 24
Peak memory 268952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518878325 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_mem_
rw_with_rand_reset.3518878325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_rw.1161744003
Short name T720
Test name
Test status
Simulation time 475234660 ps
CPU time 12.56 seconds
Started Aug 25 12:40:56 PM UTC 24
Finished Aug 25 12:41:10 PM UTC 24
Peak memory 252444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161744003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1161744003
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_intr_test.1976726519
Short name T399
Test name
Test status
Simulation time 12314255 ps
CPU time 2.09 seconds
Started Aug 25 12:40:56 PM UTC 24
Finished Aug 25 12:40:59 PM UTC 24
Peak memory 250536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976726519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1976726519
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2952566641
Short name T726
Test name
Test status
Simulation time 344688229 ps
CPU time 42.08 seconds
Started Aug 25 12:41:00 PM UTC 24
Finished Aug 25 12:41:44 PM UTC 24
Peak memory 260768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952566641 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outstanding.2952566641
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3298174524
Short name T190
Test name
Test status
Simulation time 9062964205 ps
CPU time 606.05 seconds
Started Aug 25 12:40:38 PM UTC 24
Finished Aug 25 12:50:53 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298174524 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shado
w_reg_errors_with_csr_rw.3298174524
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_errors.4189290549
Short name T721
Test name
Test status
Simulation time 408336856 ps
CPU time 41.76 seconds
Started Aug 25 12:40:49 PM UTC 24
Finished Aug 25 12:41:32 PM UTC 24
Peak memory 262824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189290549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4189290549
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy.790676509
Short name T125
Test name
Test status
Simulation time 17811899822 ps
CPU time 1813.35 seconds
Started Aug 25 11:11:37 AM UTC 24
Finished Aug 25 11:42:17 AM UTC 24
Peak memory 282084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790676509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.790676509
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy_stress.13859189
Short name T5
Test name
Test status
Simulation time 1450846337 ps
CPU time 52.27 seconds
Started Aug 25 11:11:41 AM UTC 24
Finished Aug 25 11:12:34 AM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13859189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_h
andler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.13859189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_intr_timeout.3478281590
Short name T10
Test name
Test status
Simulation time 3903627655 ps
CPU time 24.25 seconds
Started Aug 25 11:11:37 AM UTC 24
Finished Aug 25 11:12:02 AM UTC 24
Peak memory 269216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478281590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3478281590
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_alerts.486126102
Short name T1
Test name
Test status
Simulation time 116689548 ps
CPU time 4.57 seconds
Started Aug 25 11:11:35 AM UTC 24
Finished Aug 25 11:11:41 AM UTC 24
Peak memory 252728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486126102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.486126102
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/0.alert_handler_smoke.2671142533
Short name T11
Test name
Test status
Simulation time 303696399 ps
CPU time 38.77 seconds
Started Aug 25 11:11:34 AM UTC 24
Finished Aug 25 11:12:14 AM UTC 24
Peak memory 269124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671142533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2671142533
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/0.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy.2448676110
Short name T262
Test name
Test status
Simulation time 9366559550 ps
CPU time 979 seconds
Started Aug 25 11:11:57 AM UTC 24
Finished Aug 25 11:28:30 AM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448676110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2448676110
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy_stress.880530400
Short name T7
Test name
Test status
Simulation time 1575608655 ps
CPU time 50.79 seconds
Started Aug 25 11:12:06 AM UTC 24
Finished Aug 25 11:12:58 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880530400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.880530400
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_alert_accum.1188446972
Short name T133
Test name
Test status
Simulation time 16714074637 ps
CPU time 341.79 seconds
Started Aug 25 11:11:56 AM UTC 24
Finished Aug 25 11:17:43 AM UTC 24
Peak memory 269212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188446972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1188446972
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg_stub_clk.1212452396
Short name T510
Test name
Test status
Simulation time 32187472328 ps
CPU time 2924.29 seconds
Started Aug 25 11:12:06 AM UTC 24
Finished Aug 25 12:01:28 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212452396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1212452396
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/1.alert_handler_ping_timeout.805372458
Short name T344
Test name
Test status
Simulation time 33448433340 ps
CPU time 448.34 seconds
Started Aug 25 11:12:02 AM UTC 24
Finished Aug 25 11:19:36 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805372458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.805372458
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/1.alert_handler_sec_cm.628843672
Short name T6
Test name
Test status
Simulation time 1985135575 ps
CPU time 29.49 seconds
Started Aug 25 11:12:15 AM UTC 24
Finished Aug 25 11:12:46 AM UTC 24
Peak memory 297316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628843672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_h
andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.628843672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/1.alert_handler_smoke.3681969244
Short name T3
Test name
Test status
Simulation time 77998543 ps
CPU time 9.71 seconds
Started Aug 25 11:11:49 AM UTC 24
Finished Aug 25 11:12:00 AM UTC 24
Peak memory 267076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681969244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3681969244
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all.2157706897
Short name T321
Test name
Test status
Simulation time 78645325380 ps
CPU time 2522.27 seconds
Started Aug 25 11:12:07 AM UTC 24
Finished Aug 25 11:54:43 AM UTC 24
Peak memory 304600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157706897 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all.2157706897
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/1.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/10.alert_handler_alert_accum_saturation.3532381655
Short name T83
Test name
Test status
Simulation time 35838459 ps
CPU time 5.47 seconds
Started Aug 25 11:18:38 AM UTC 24
Finished Aug 25 11:18:45 AM UTC 24
Peak memory 263500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532381655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3532381655
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy_stress.1202886978
Short name T85
Test name
Test status
Simulation time 101746305 ps
CPU time 11.33 seconds
Started Aug 25 11:18:36 AM UTC 24
Finished Aug 25 11:18:49 AM UTC 24
Peak memory 263300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202886978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1202886978
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_alert_accum.4003133541
Short name T82
Test name
Test status
Simulation time 323950353 ps
CPU time 23.74 seconds
Started Aug 25 11:18:11 AM UTC 24
Finished Aug 25 11:18:36 AM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003133541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.4003133541
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_intr_timeout.1008288917
Short name T99
Test name
Test status
Simulation time 471981288 ps
CPU time 36.95 seconds
Started Aug 25 11:18:11 AM UTC 24
Finished Aug 25 11:18:49 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008288917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1008288917
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg.4140265305
Short name T379
Test name
Test status
Simulation time 13425233822 ps
CPU time 2041.06 seconds
Started Aug 25 11:18:24 AM UTC 24
Finished Aug 25 11:52:53 AM UTC 24
Peak memory 295740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140265305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.4140265305
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg_stub_clk.3431207217
Short name T561
Test name
Test status
Simulation time 35956100893 ps
CPU time 3255.62 seconds
Started Aug 25 11:18:26 AM UTC 24
Finished Aug 25 12:13:24 PM UTC 24
Peak memory 304616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431207217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3431207217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_alerts.1630540813
Short name T227
Test name
Test status
Simulation time 3214835506 ps
CPU time 69.99 seconds
Started Aug 25 11:17:58 AM UTC 24
Finished Aug 25 11:19:11 AM UTC 24
Peak memory 269184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630540813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1630540813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_classes.1191241205
Short name T80
Test name
Test status
Simulation time 227652341 ps
CPU time 20.04 seconds
Started Aug 25 11:18:00 AM UTC 24
Finished Aug 25 11:18:22 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191241205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1191241205
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/10.alert_handler_sig_int_fail.4206690123
Short name T81
Test name
Test status
Simulation time 270107469 ps
CPU time 23.14 seconds
Started Aug 25 11:18:11 AM UTC 24
Finished Aug 25 11:18:35 AM UTC 24
Peak memory 269072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206690123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.4206690123
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/10.alert_handler_smoke.3248694812
Short name T258
Test name
Test status
Simulation time 17720363 ps
CPU time 4.38 seconds
Started Aug 25 11:17:51 AM UTC 24
Finished Aug 25 11:17:56 AM UTC 24
Peak memory 265096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248694812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3248694812
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all.1379812531
Short name T36
Test name
Test status
Simulation time 24838634281 ps
CPU time 328.94 seconds
Started Aug 25 11:18:36 AM UTC 24
Finished Aug 25 11:24:11 AM UTC 24
Peak memory 269184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379812531 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all.1379812531
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/10.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/11.alert_handler_alert_accum_saturation.428738499
Short name T250
Test name
Test status
Simulation time 53240778 ps
CPU time 6.13 seconds
Started Aug 25 11:19:14 AM UTC 24
Finished Aug 25 11:19:21 AM UTC 24
Peak memory 263176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428738499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.428738499
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy.2758494271
Short name T488
Test name
Test status
Simulation time 25874364311 ps
CPU time 2090 seconds
Started Aug 25 11:19:00 AM UTC 24
Finished Aug 25 11:54:18 AM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758494271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2758494271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy_stress.319227946
Short name T414
Test name
Test status
Simulation time 2739620046 ps
CPU time 26.92 seconds
Started Aug 25 11:19:11 AM UTC 24
Finished Aug 25 11:19:39 AM UTC 24
Peak memory 263304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319227946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.319227946
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_alert_accum.1546242954
Short name T419
Test name
Test status
Simulation time 1636909100 ps
CPU time 128.53 seconds
Started Aug 25 11:18:51 AM UTC 24
Finished Aug 25 11:21:02 AM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546242954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1546242954
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_intr_timeout.2022083706
Short name T158
Test name
Test status
Simulation time 518169762 ps
CPU time 23.7 seconds
Started Aug 25 11:18:51 AM UTC 24
Finished Aug 25 11:19:16 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022083706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2022083706
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg_stub_clk.1464770599
Short name T514
Test name
Test status
Simulation time 56730496159 ps
CPU time 2524.42 seconds
Started Aug 25 11:19:08 AM UTC 24
Finished Aug 25 12:01:48 PM UTC 24
Peak memory 285584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464770599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1464770599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/11.alert_handler_ping_timeout.678957219
Short name T346
Test name
Test status
Simulation time 5223485277 ps
CPU time 314.4 seconds
Started Aug 25 11:19:01 AM UTC 24
Finished Aug 25 11:24:20 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678957219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.678957219
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_alerts.4190513467
Short name T316
Test name
Test status
Simulation time 440211948 ps
CPU time 45.44 seconds
Started Aug 25 11:18:48 AM UTC 24
Finished Aug 25 11:19:35 AM UTC 24
Peak memory 269248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190513467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.4190513467
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_classes.2395424064
Short name T224
Test name
Test status
Simulation time 42798325 ps
CPU time 7.23 seconds
Started Aug 25 11:18:50 AM UTC 24
Finished Aug 25 11:18:59 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395424064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2395424064
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/11.alert_handler_sig_int_fail.1374412288
Short name T261
Test name
Test status
Simulation time 4642729019 ps
CPU time 84.54 seconds
Started Aug 25 11:18:54 AM UTC 24
Finished Aug 25 11:20:20 AM UTC 24
Peak memory 269216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374412288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1374412288
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/11.alert_handler_smoke.144072198
Short name T225
Test name
Test status
Simulation time 238141759 ps
CPU time 13.18 seconds
Started Aug 25 11:18:48 AM UTC 24
Finished Aug 25 11:19:02 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144072198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.144072198
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/11.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/12.alert_handler_alert_accum_saturation.3943236650
Short name T251
Test name
Test status
Simulation time 46363338 ps
CPU time 6.06 seconds
Started Aug 25 11:20:12 AM UTC 24
Finished Aug 25 11:20:19 AM UTC 24
Peak memory 263172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943236650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3943236650
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy.1069590753
Short name T511
Test name
Test status
Simulation time 26881519148 ps
CPU time 2477.29 seconds
Started Aug 25 11:19:40 AM UTC 24
Finished Aug 25 12:01:30 PM UTC 24
Peak memory 295744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069590753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1069590753
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy_stress.1255462961
Short name T417
Test name
Test status
Simulation time 335190229 ps
CPU time 15.05 seconds
Started Aug 25 11:19:58 AM UTC 24
Finished Aug 25 11:20:14 AM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255462961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1255462961
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_alert_accum.2093016717
Short name T427
Test name
Test status
Simulation time 12316226712 ps
CPU time 276.06 seconds
Started Aug 25 11:19:37 AM UTC 24
Finished Aug 25 11:24:18 AM UTC 24
Peak memory 269500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093016717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2093016717
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_intr_timeout.1204269316
Short name T421
Test name
Test status
Simulation time 3410898354 ps
CPU time 95.67 seconds
Started Aug 25 11:19:36 AM UTC 24
Finished Aug 25 11:21:14 AM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204269316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1204269316
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg_stub_clk.3436887155
Short name T117
Test name
Test status
Simulation time 15184436796 ps
CPU time 2321.43 seconds
Started Aug 25 11:19:55 AM UTC 24
Finished Aug 25 11:59:11 AM UTC 24
Peak memory 302092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436887155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3436887155
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/12.alert_handler_ping_timeout.4001117122
Short name T345
Test name
Test status
Simulation time 7838066829 ps
CPU time 310.81 seconds
Started Aug 25 11:19:42 AM UTC 24
Finished Aug 25 11:24:58 AM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001117122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.4001117122
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_alerts.3322153927
Short name T65
Test name
Test status
Simulation time 217807818 ps
CPU time 13.34 seconds
Started Aug 25 11:19:21 AM UTC 24
Finished Aug 25 11:19:36 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322153927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3322153927
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_classes.1530749812
Short name T305
Test name
Test status
Simulation time 366336676 ps
CPU time 25.37 seconds
Started Aug 25 11:19:33 AM UTC 24
Finished Aug 25 11:20:00 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530749812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1530749812
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/12.alert_handler_sig_int_fail.3735413912
Short name T123
Test name
Test status
Simulation time 66242665 ps
CPU time 13.72 seconds
Started Aug 25 11:19:37 AM UTC 24
Finished Aug 25 11:19:52 AM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735413912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3735413912
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/12.alert_handler_smoke.1706724272
Short name T416
Test name
Test status
Simulation time 6371501322 ps
CPU time 36.36 seconds
Started Aug 25 11:19:19 AM UTC 24
Finished Aug 25 11:19:57 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706724272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1706724272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all.1845826636
Short name T423
Test name
Test status
Simulation time 3357085690 ps
CPU time 154.74 seconds
Started Aug 25 11:20:01 AM UTC 24
Finished Aug 25 11:22:38 AM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845826636 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all.1845826636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/12.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy_stress.1694888055
Short name T141
Test name
Test status
Simulation time 1131389284 ps
CPU time 26.59 seconds
Started Aug 25 11:21:15 AM UTC 24
Finished Aug 25 11:21:43 AM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694888055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1694888055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_alert_accum.1907152420
Short name T279
Test name
Test status
Simulation time 3569709625 ps
CPU time 230.41 seconds
Started Aug 25 11:20:55 AM UTC 24
Finished Aug 25 11:24:49 AM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907152420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1907152420
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_intr_timeout.2756428392
Short name T420
Test name
Test status
Simulation time 356368632 ps
CPU time 40.06 seconds
Started Aug 25 11:20:25 AM UTC 24
Finished Aug 25 11:21:07 AM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756428392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2756428392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg.3836954930
Short name T332
Test name
Test status
Simulation time 77462765472 ps
CPU time 1636.74 seconds
Started Aug 25 11:21:14 AM UTC 24
Finished Aug 25 11:48:54 AM UTC 24
Peak memory 285832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836954930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3836954930
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg_stub_clk.2548366821
Short name T116
Test name
Test status
Simulation time 38241007995 ps
CPU time 1316.7 seconds
Started Aug 25 11:21:15 AM UTC 24
Finished Aug 25 11:43:30 AM UTC 24
Peak memory 285508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548366821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2548366821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/13.alert_handler_ping_timeout.392389216
Short name T347
Test name
Test status
Simulation time 27529640500 ps
CPU time 369.64 seconds
Started Aug 25 11:21:11 AM UTC 24
Finished Aug 25 11:27:26 AM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392389216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.392389216
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_alerts.2608977615
Short name T418
Test name
Test status
Simulation time 1162108013 ps
CPU time 32.57 seconds
Started Aug 25 11:20:20 AM UTC 24
Finished Aug 25 11:20:54 AM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608977615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2608977615
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_classes.2271565158
Short name T140
Test name
Test status
Simulation time 10296106363 ps
CPU time 78.62 seconds
Started Aug 25 11:20:21 AM UTC 24
Finished Aug 25 11:21:42 AM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271565158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2271565158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/13.alert_handler_sig_int_fail.1330018012
Short name T100
Test name
Test status
Simulation time 82402431 ps
CPU time 9.81 seconds
Started Aug 25 11:21:03 AM UTC 24
Finished Aug 25 11:21:14 AM UTC 24
Peak memory 263328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330018012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1330018012
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/13.alert_handler_smoke.1182015965
Short name T143
Test name
Test status
Simulation time 4407590047 ps
CPU time 121.27 seconds
Started Aug 25 11:20:15 AM UTC 24
Finished Aug 25 11:22:19 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182015965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1182015965
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all.4045701929
Short name T145
Test name
Test status
Simulation time 1528653429 ps
CPU time 69.97 seconds
Started Aug 25 11:21:17 AM UTC 24
Finished Aug 25 11:22:29 AM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045701929 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all.4045701929
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/13.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/14.alert_handler_alert_accum_saturation.1925959341
Short name T252
Test name
Test status
Simulation time 108879951 ps
CPU time 2.96 seconds
Started Aug 25 11:22:30 AM UTC 24
Finished Aug 25 11:22:34 AM UTC 24
Peak memory 263488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925959341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1925959341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy_stress.3674246184
Short name T424
Test name
Test status
Simulation time 580810393 ps
CPU time 25.63 seconds
Started Aug 25 11:22:19 AM UTC 24
Finished Aug 25 11:22:46 AM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674246184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3674246184
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_alert_accum.802331445
Short name T447
Test name
Test status
Simulation time 10884852695 ps
CPU time 496.88 seconds
Started Aug 25 11:21:50 AM UTC 24
Finished Aug 25 11:30:15 AM UTC 24
Peak memory 269212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802331445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.802331445
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_intr_timeout.3965342590
Short name T89
Test name
Test status
Simulation time 213926902 ps
CPU time 32 seconds
Started Aug 25 11:21:44 AM UTC 24
Finished Aug 25 11:22:17 AM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965342590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3965342590
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg_stub_clk.1461240717
Short name T552
Test name
Test status
Simulation time 137105783263 ps
CPU time 2879.4 seconds
Started Aug 25 11:22:18 AM UTC 24
Finished Aug 25 12:10:57 PM UTC 24
Peak memory 288308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461240717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1461240717
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/14.alert_handler_ping_timeout.3123994517
Short name T359
Test name
Test status
Simulation time 17122564727 ps
CPU time 477.95 seconds
Started Aug 25 11:21:59 AM UTC 24
Finished Aug 25 11:30:03 AM UTC 24
Peak memory 262984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123994517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3123994517
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_alerts.2131071559
Short name T422
Test name
Test status
Simulation time 2262538043 ps
CPU time 59.7 seconds
Started Aug 25 11:21:32 AM UTC 24
Finished Aug 25 11:22:34 AM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131071559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2131071559
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_classes.4232268027
Short name T151
Test name
Test status
Simulation time 314356262 ps
CPU time 51.77 seconds
Started Aug 25 11:21:43 AM UTC 24
Finished Aug 25 11:22:36 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232268027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.4232268027
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/14.alert_handler_sig_int_fail.3702417870
Short name T67
Test name
Test status
Simulation time 768497265 ps
CPU time 45.01 seconds
Started Aug 25 11:21:51 AM UTC 24
Finished Aug 25 11:22:38 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702417870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3702417870
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/14.alert_handler_smoke.3931035016
Short name T142
Test name
Test status
Simulation time 253097853 ps
CPU time 26.28 seconds
Started Aug 25 11:21:30 AM UTC 24
Finished Aug 25 11:21:58 AM UTC 24
Peak memory 269128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931035016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3931035016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all.1589097162
Short name T437
Test name
Test status
Simulation time 1598453531 ps
CPU time 244.22 seconds
Started Aug 25 11:22:22 AM UTC 24
Finished Aug 25 11:26:31 AM UTC 24
Peak memory 264952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589097162 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all.1589097162
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/14.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/15.alert_handler_alert_accum_saturation.1459944408
Short name T253
Test name
Test status
Simulation time 38502226 ps
CPU time 3.35 seconds
Started Aug 25 11:23:21 AM UTC 24
Finished Aug 25 11:23:25 AM UTC 24
Peak memory 263248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459944408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1459944408
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy.2587597308
Short name T303
Test name
Test status
Simulation time 72468655410 ps
CPU time 1459.4 seconds
Started Aug 25 11:22:46 AM UTC 24
Finished Aug 25 11:47:24 AM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587597308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2587597308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy_stress.4194245604
Short name T425
Test name
Test status
Simulation time 255326605 ps
CPU time 20 seconds
Started Aug 25 11:23:11 AM UTC 24
Finished Aug 25 11:23:32 AM UTC 24
Peak memory 263236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194245604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.4194245604
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_alert_accum.3520430892
Short name T438
Test name
Test status
Simulation time 1854979752 ps
CPU time 244.64 seconds
Started Aug 25 11:22:38 AM UTC 24
Finished Aug 25 11:26:47 AM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520430892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3520430892
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_intr_timeout.2027615865
Short name T147
Test name
Test status
Simulation time 3758959704 ps
CPU time 58.98 seconds
Started Aug 25 11:22:37 AM UTC 24
Finished Aug 25 11:23:38 AM UTC 24
Peak memory 263356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027615865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2027615865
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg_stub_clk.3093466778
Short name T523
Test name
Test status
Simulation time 28161553351 ps
CPU time 2361.76 seconds
Started Aug 25 11:23:08 AM UTC 24
Finished Aug 25 12:03:04 PM UTC 24
Peak memory 301892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093466778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3093466778
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_alerts.3352134093
Short name T68
Test name
Test status
Simulation time 309187418 ps
CPU time 8.86 seconds
Started Aug 25 11:22:35 AM UTC 24
Finished Aug 25 11:22:45 AM UTC 24
Peak memory 264924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352134093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3352134093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_classes.3728569967
Short name T41
Test name
Test status
Simulation time 609682130 ps
CPU time 54.34 seconds
Started Aug 25 11:22:35 AM UTC 24
Finished Aug 25 11:23:31 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728569967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3728569967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/15.alert_handler_sig_int_fail.3136184681
Short name T260
Test name
Test status
Simulation time 300735043 ps
CPU time 25.8 seconds
Started Aug 25 11:22:40 AM UTC 24
Finished Aug 25 11:23:07 AM UTC 24
Peak memory 269080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136184681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3136184681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/15.alert_handler_smoke.998675749
Short name T426
Test name
Test status
Simulation time 11551697080 ps
CPU time 76.95 seconds
Started Aug 25 11:22:35 AM UTC 24
Finished Aug 25 11:23:54 AM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998675749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.998675749
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all.2811446481
Short name T339
Test name
Test status
Simulation time 20041086645 ps
CPU time 1694.6 seconds
Started Aug 25 11:23:14 AM UTC 24
Finished Aug 25 11:51:53 AM UTC 24
Peak memory 301880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811446481 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all.2811446481
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all_with_rand_reset.1117665682
Short name T223
Test name
Test status
Simulation time 3294984163 ps
CPU time 270.7 seconds
Started Aug 25 11:23:26 AM UTC 24
Finished Aug 25 11:28:01 AM UTC 24
Peak memory 281600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1117665682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.a
lert_handler_stress_all_with_rand_reset.1117665682
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/16.alert_handler_alert_accum_saturation.3589276060
Short name T254
Test name
Test status
Simulation time 53410845 ps
CPU time 6.74 seconds
Started Aug 25 11:24:20 AM UTC 24
Finished Aug 25 11:24:28 AM UTC 24
Peak memory 263248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589276060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3589276060
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy.3718780276
Short name T500
Test name
Test status
Simulation time 280650023563 ps
CPU time 2023.24 seconds
Started Aug 25 11:23:47 AM UTC 24
Finished Aug 25 11:57:57 AM UTC 24
Peak memory 301956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718780276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3718780276
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy_stress.1137818075
Short name T434
Test name
Test status
Simulation time 3002643689 ps
CPU time 53.95 seconds
Started Aug 25 11:24:12 AM UTC 24
Finished Aug 25 11:25:08 AM UTC 24
Peak memory 263300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137818075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1137818075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_alert_accum.375810150
Short name T430
Test name
Test status
Simulation time 901932652 ps
CPU time 42.53 seconds
Started Aug 25 11:23:44 AM UTC 24
Finished Aug 25 11:24:28 AM UTC 24
Peak memory 269080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375810150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.375810150
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_intr_timeout.155277393
Short name T432
Test name
Test status
Simulation time 1592006572 ps
CPU time 59.23 seconds
Started Aug 25 11:23:39 AM UTC 24
Finished Aug 25 11:24:40 AM UTC 24
Peak memory 263292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155277393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.155277393
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg_stub_clk.2215282594
Short name T599
Test name
Test status
Simulation time 76977225859 ps
CPU time 3214.65 seconds
Started Aug 25 11:24:05 AM UTC 24
Finished Aug 25 12:18:21 PM UTC 24
Peak memory 305008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215282594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2215282594
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/16.alert_handler_ping_timeout.851927019
Short name T361
Test name
Test status
Simulation time 15405835262 ps
CPU time 940.58 seconds
Started Aug 25 11:23:55 AM UTC 24
Finished Aug 25 11:39:50 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851927019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.851927019
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_alerts.1771531342
Short name T428
Test name
Test status
Simulation time 1410057708 ps
CPU time 47.58 seconds
Started Aug 25 11:23:33 AM UTC 24
Finished Aug 25 11:24:22 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771531342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1771531342
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_classes.3149078233
Short name T69
Test name
Test status
Simulation time 518968792 ps
CPU time 28.82 seconds
Started Aug 25 11:23:34 AM UTC 24
Finished Aug 25 11:24:05 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149078233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3149078233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/16.alert_handler_sig_int_fail.3751907466
Short name T322
Test name
Test status
Simulation time 78086177 ps
CPU time 8.63 seconds
Started Aug 25 11:23:47 AM UTC 24
Finished Aug 25 11:23:57 AM UTC 24
Peak memory 252960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751907466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3751907466
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/16.alert_handler_smoke.3204132907
Short name T429
Test name
Test status
Simulation time 852355998 ps
CPU time 53.62 seconds
Started Aug 25 11:23:32 AM UTC 24
Finished Aug 25 11:24:27 AM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204132907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3204132907
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all.4205749259
Short name T126
Test name
Test status
Simulation time 66343521197 ps
CPU time 2685.4 seconds
Started Aug 25 11:24:13 AM UTC 24
Finished Aug 25 12:09:35 PM UTC 24
Peak memory 318264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205749259 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all.4205749259
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/16.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/17.alert_handler_alert_accum_saturation.3579761017
Short name T255
Test name
Test status
Simulation time 41714925 ps
CPU time 6.37 seconds
Started Aug 25 11:25:09 AM UTC 24
Finished Aug 25 11:25:16 AM UTC 24
Peak memory 263168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579761017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3579761017
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy.3475844169
Short name T494
Test name
Test status
Simulation time 100441513783 ps
CPU time 1824.48 seconds
Started Aug 25 11:24:41 AM UTC 24
Finished Aug 25 11:55:30 AM UTC 24
Peak memory 285508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475844169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3475844169
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy_stress.3576057852
Short name T269
Test name
Test status
Simulation time 3673533513 ps
CPU time 63.9 seconds
Started Aug 25 11:24:50 AM UTC 24
Finished Aug 25 11:25:55 AM UTC 24
Peak memory 263044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576057852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3576057852
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_alert_accum.3365697303
Short name T282
Test name
Test status
Simulation time 6226533003 ps
CPU time 570.26 seconds
Started Aug 25 11:24:29 AM UTC 24
Finished Aug 25 11:34:07 AM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365697303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3365697303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_intr_timeout.3681372837
Short name T431
Test name
Test status
Simulation time 18566602 ps
CPU time 5.05 seconds
Started Aug 25 11:24:29 AM UTC 24
Finished Aug 25 11:24:35 AM UTC 24
Peak memory 252732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681372837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3681372837
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg.1496403090
Short name T329
Test name
Test status
Simulation time 31370663859 ps
CPU time 997.32 seconds
Started Aug 25 11:24:43 AM UTC 24
Finished Aug 25 11:41:35 AM UTC 24
Peak memory 285828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496403090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1496403090
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/17.alert_handler_ping_timeout.1582755579
Short name T363
Test name
Test status
Simulation time 3613226281 ps
CPU time 193.37 seconds
Started Aug 25 11:24:42 AM UTC 24
Finished Aug 25 11:27:59 AM UTC 24
Peak memory 263120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582755579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1582755579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_alerts.758826803
Short name T436
Test name
Test status
Simulation time 3887451542 ps
CPU time 64.79 seconds
Started Aug 25 11:24:23 AM UTC 24
Finished Aug 25 11:25:31 AM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758826803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.758826803
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_classes.935009501
Short name T433
Test name
Test status
Simulation time 158623558 ps
CPU time 17.66 seconds
Started Aug 25 11:24:28 AM UTC 24
Finished Aug 25 11:24:47 AM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935009501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.935009501
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/17.alert_handler_sig_int_fail.2496708848
Short name T348
Test name
Test status
Simulation time 660022944 ps
CPU time 31.18 seconds
Started Aug 25 11:24:36 AM UTC 24
Finished Aug 25 11:25:09 AM UTC 24
Peak memory 262916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496708848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2496708848
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/17.alert_handler_smoke.4245371170
Short name T435
Test name
Test status
Simulation time 713765158 ps
CPU time 64.43 seconds
Started Aug 25 11:24:21 AM UTC 24
Finished Aug 25 11:25:28 AM UTC 24
Peak memory 269128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245371170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.4245371170
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all_with_rand_reset.3530661581
Short name T106
Test name
Test status
Simulation time 14607601714 ps
CPU time 611.88 seconds
Started Aug 25 11:25:10 AM UTC 24
Finished Aug 25 11:35:31 AM UTC 24
Peak memory 283576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3530661581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.a
lert_handler_stress_all_with_rand_reset.3530661581
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/18.alert_handler_alert_accum_saturation.2439150734
Short name T256
Test name
Test status
Simulation time 13078551 ps
CPU time 3.65 seconds
Started Aug 25 11:26:12 AM UTC 24
Finished Aug 25 11:26:17 AM UTC 24
Peak memory 263504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439150734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2439150734
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy.874344016
Short name T509
Test name
Test status
Simulation time 24305754587 ps
CPU time 2105.52 seconds
Started Aug 25 11:25:45 AM UTC 24
Finished Aug 25 12:01:19 PM UTC 24
Peak memory 279684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874344016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.874344016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy_stress.2988866368
Short name T439
Test name
Test status
Simulation time 1482098343 ps
CPU time 42.95 seconds
Started Aug 25 11:26:03 AM UTC 24
Finished Aug 25 11:26:47 AM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988866368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2988866368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_alert_accum.1355257941
Short name T440
Test name
Test status
Simulation time 1161640973 ps
CPU time 97.78 seconds
Started Aug 25 11:25:32 AM UTC 24
Finished Aug 25 11:27:12 AM UTC 24
Peak memory 269052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355257941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1355257941
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_intr_timeout.1315595540
Short name T268
Test name
Test status
Simulation time 450447405 ps
CPU time 12.65 seconds
Started Aug 25 11:25:29 AM UTC 24
Finished Aug 25 11:25:44 AM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315595540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1315595540
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg_stub_clk.3086717179
Short name T574
Test name
Test status
Simulation time 47309814183 ps
CPU time 2900.62 seconds
Started Aug 25 11:25:56 AM UTC 24
Finished Aug 25 12:14:56 PM UTC 24
Peak memory 285840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086717179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3086717179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/18.alert_handler_ping_timeout.1230013827
Short name T355
Test name
Test status
Simulation time 9329102455 ps
CPU time 596.03 seconds
Started Aug 25 11:25:47 AM UTC 24
Finished Aug 25 11:35:52 AM UTC 24
Peak memory 269124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230013827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1230013827
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_classes.644725610
Short name T91
Test name
Test status
Simulation time 235634018 ps
CPU time 22.28 seconds
Started Aug 25 11:25:22 AM UTC 24
Finished Aug 25 11:25:46 AM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644725610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.644725610
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/18.alert_handler_sig_int_fail.285336596
Short name T42
Test name
Test status
Simulation time 76821935 ps
CPU time 16.33 seconds
Started Aug 25 11:25:44 AM UTC 24
Finished Aug 25 11:26:01 AM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285336596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.285336596
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/18.alert_handler_smoke.1749924610
Short name T270
Test name
Test status
Simulation time 2541534048 ps
CPU time 60.15 seconds
Started Aug 25 11:25:13 AM UTC 24
Finished Aug 25 11:26:15 AM UTC 24
Peak memory 263304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749924610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1749924610
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all.1643049445
Short name T107
Test name
Test status
Simulation time 23869227315 ps
CPU time 982.76 seconds
Started Aug 25 11:26:07 AM UTC 24
Finished Aug 25 11:42:44 AM UTC 24
Peak memory 279424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643049445 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all.1643049445
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/18.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/19.alert_handler_alert_accum_saturation.200851002
Short name T257
Test name
Test status
Simulation time 94455537 ps
CPU time 6.83 seconds
Started Aug 25 11:27:13 AM UTC 24
Finished Aug 25 11:27:21 AM UTC 24
Peak memory 263176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200851002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.200851002
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy_stress.4098240556
Short name T442
Test name
Test status
Simulation time 551207831 ps
CPU time 42.61 seconds
Started Aug 25 11:27:06 AM UTC 24
Finished Aug 25 11:27:50 AM UTC 24
Peak memory 263240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098240556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.4098240556
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_alert_accum.440564129
Short name T280
Test name
Test status
Simulation time 5618831755 ps
CPU time 231.25 seconds
Started Aug 25 11:26:32 AM UTC 24
Finished Aug 25 11:30:28 AM UTC 24
Peak memory 263004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440564129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.440564129
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_intr_timeout.611460786
Short name T160
Test name
Test status
Simulation time 284315608 ps
CPU time 29.72 seconds
Started Aug 25 11:26:31 AM UTC 24
Finished Aug 25 11:27:03 AM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611460786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.611460786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg.1355547449
Short name T387
Test name
Test status
Simulation time 46446136201 ps
CPU time 1902.31 seconds
Started Aug 25 11:27:00 AM UTC 24
Finished Aug 25 11:59:11 AM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355547449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1355547449
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg_stub_clk.3233271768
Short name T482
Test name
Test status
Simulation time 39979675030 ps
CPU time 1457.69 seconds
Started Aug 25 11:27:03 AM UTC 24
Finished Aug 25 11:51:42 AM UTC 24
Peak memory 301892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233271768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3233271768
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/19.alert_handler_ping_timeout.1730658794
Short name T354
Test name
Test status
Simulation time 15041364841 ps
CPU time 414.7 seconds
Started Aug 25 11:26:59 AM UTC 24
Finished Aug 25 11:34:00 AM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730658794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1730658794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_alerts.4048297678
Short name T111
Test name
Test status
Simulation time 434488011 ps
CPU time 47.99 seconds
Started Aug 25 11:26:18 AM UTC 24
Finished Aug 25 11:27:08 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048297678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.4048297678
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_classes.891076474
Short name T152
Test name
Test status
Simulation time 394606172 ps
CPU time 39 seconds
Started Aug 25 11:26:24 AM UTC 24
Finished Aug 25 11:27:05 AM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891076474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.891076474
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/19.alert_handler_sig_int_fail.3724058331
Short name T350
Test name
Test status
Simulation time 308956522 ps
CPU time 9.87 seconds
Started Aug 25 11:26:49 AM UTC 24
Finished Aug 25 11:27:00 AM UTC 24
Peak memory 264796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724058331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3724058331
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/19.alert_handler_smoke.487269379
Short name T441
Test name
Test status
Simulation time 5225870481 ps
CPU time 84.29 seconds
Started Aug 25 11:26:16 AM UTC 24
Finished Aug 25 11:27:42 AM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487269379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.487269379
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all.4009503481
Short name T110
Test name
Test status
Simulation time 127261772619 ps
CPU time 3264.41 seconds
Started Aug 25 11:27:09 AM UTC 24
Finished Aug 25 12:22:18 PM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009503481 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all.4009503481
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all_with_rand_reset.732060932
Short name T132
Test name
Test status
Simulation time 5068538740 ps
CPU time 727.55 seconds
Started Aug 25 11:27:22 AM UTC 24
Finished Aug 25 11:39:41 AM UTC 24
Peak memory 283572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=732060932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.al
ert_handler_stress_all_with_rand_reset.732060932
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy_stress.2209724389
Short name T8
Test name
Test status
Simulation time 1710209689 ps
CPU time 31.63 seconds
Started Aug 25 11:12:28 AM UTC 24
Finished Aug 25 11:13:01 AM UTC 24
Peak memory 263300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209724389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2209724389
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_alert_accum.1311557575
Short name T31
Test name
Test status
Simulation time 1473169702 ps
CPU time 34.09 seconds
Started Aug 25 11:12:21 AM UTC 24
Finished Aug 25 11:12:57 AM UTC 24
Peak memory 269076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311557575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1311557575
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg.516931785
Short name T378
Test name
Test status
Simulation time 18830880171 ps
CPU time 2255.91 seconds
Started Aug 25 11:12:26 AM UTC 24
Finished Aug 25 11:50:30 AM UTC 24
Peak memory 304680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516931785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.516931785
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg_stub_clk.2146500943
Short name T556
Test name
Test status
Simulation time 44329550923 ps
CPU time 3528.63 seconds
Started Aug 25 11:12:27 AM UTC 24
Finished Aug 25 12:11:59 PM UTC 24
Peak memory 302560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146500943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2146500943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/2.alert_handler_ping_timeout.3948077561
Short name T271
Test name
Test status
Simulation time 26876863029 ps
CPU time 826.28 seconds
Started Aug 25 11:12:26 AM UTC 24
Finished Aug 25 11:26:23 AM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948077561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3948077561
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_alerts.3591636974
Short name T44
Test name
Test status
Simulation time 691727485 ps
CPU time 51.07 seconds
Started Aug 25 11:12:16 AM UTC 24
Finished Aug 25 11:13:09 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591636974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3591636974
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/2.alert_handler_sec_cm.2482570002
Short name T9
Test name
Test status
Simulation time 652520259 ps
CPU time 17.05 seconds
Started Aug 25 11:12:32 AM UTC 24
Finished Aug 25 11:12:50 AM UTC 24
Peak memory 297320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482570002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2482570002
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/2.alert_handler_sig_int_fail.3843344359
Short name T28
Test name
Test status
Simulation time 288669013 ps
CPU time 30.83 seconds
Started Aug 25 11:12:22 AM UTC 24
Finished Aug 25 11:12:54 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843344359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3843344359
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/2.alert_handler_smoke.658798098
Short name T29
Test name
Test status
Simulation time 898694450 ps
CPU time 39.43 seconds
Started Aug 25 11:12:15 AM UTC 24
Finished Aug 25 11:12:56 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658798098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.658798098
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all.2964023332
Short name T622
Test name
Test status
Simulation time 205024402567 ps
CPU time 4370.28 seconds
Started Aug 25 11:12:30 AM UTC 24
Finished Aug 25 12:26:18 PM UTC 24
Peak memory 304992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964023332 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all.2964023332
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all_with_rand_reset.357889570
Short name T50
Test name
Test status
Simulation time 9454793507 ps
CPU time 651.9 seconds
Started Aug 25 11:12:32 AM UTC 24
Finished Aug 25 11:23:34 AM UTC 24
Peak memory 285700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=357889570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ale
rt_handler_stress_all_with_rand_reset.357889570
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/20.alert_handler_entropy.3153378226
Short name T507
Test name
Test status
Simulation time 27833104331 ps
CPU time 1914.17 seconds
Started Aug 25 11:28:16 AM UTC 24
Finished Aug 25 12:00:35 PM UTC 24
Peak memory 301888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153378226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3153378226
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/20.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_alert_accum.209734888
Short name T275
Test name
Test status
Simulation time 1632248125 ps
CPU time 32.58 seconds
Started Aug 25 11:28:00 AM UTC 24
Finished Aug 25 11:28:34 AM UTC 24
Peak memory 269468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209734888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.209734888
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_intr_timeout.3320525567
Short name T103
Test name
Test status
Simulation time 902590285 ps
CPU time 30.7 seconds
Started Aug 25 11:27:57 AM UTC 24
Finished Aug 25 11:28:29 AM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320525567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3320525567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg_stub_clk.2783885381
Short name T338
Test name
Test status
Simulation time 38664860011 ps
CPU time 1333.96 seconds
Started Aug 25 11:28:34 AM UTC 24
Finished Aug 25 11:51:07 AM UTC 24
Peak memory 285508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783885381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2783885381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_alerts.2448442075
Short name T445
Test name
Test status
Simulation time 3106855871 ps
CPU time 100.94 seconds
Started Aug 25 11:27:43 AM UTC 24
Finished Aug 25 11:29:26 AM UTC 24
Peak memory 263040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448442075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2448442075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/20.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_classes.739593143
Short name T444
Test name
Test status
Simulation time 307182276 ps
CPU time 23.35 seconds
Started Aug 25 11:27:50 AM UTC 24
Finished Aug 25 11:28:15 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739593143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.739593143
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/20.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/20.alert_handler_smoke.596223709
Short name T443
Test name
Test status
Simulation time 209757733 ps
CPU time 26.54 seconds
Started Aug 25 11:27:27 AM UTC 24
Finished Aug 25 11:27:55 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596223709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.596223709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/20.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all.2377467640
Short name T109
Test name
Test status
Simulation time 16659171827 ps
CPU time 2516.88 seconds
Started Aug 25 11:29:01 AM UTC 24
Finished Aug 25 12:11:33 PM UTC 24
Peak memory 301952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377467640 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all.2377467640
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/20.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all_with_rand_reset.2990369027
Short name T34
Test name
Test status
Simulation time 3655785110 ps
CPU time 570.52 seconds
Started Aug 25 11:29:28 AM UTC 24
Finished Aug 25 11:39:07 AM UTC 24
Peak memory 283776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2990369027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.a
lert_handler_stress_all_with_rand_reset.2990369027
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/21.alert_handler_entropy.296659520
Short name T521
Test name
Test status
Simulation time 50117303920 ps
CPU time 1924.92 seconds
Started Aug 25 11:30:29 AM UTC 24
Finished Aug 25 12:03:00 PM UTC 24
Peak memory 285896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296659520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.296659520
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/21.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_alert_accum.3265698402
Short name T451
Test name
Test status
Simulation time 1381310055 ps
CPU time 46.68 seconds
Started Aug 25 11:30:27 AM UTC 24
Finished Aug 25 11:31:15 AM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265698402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3265698402
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_intr_timeout.1830883629
Short name T448
Test name
Test status
Simulation time 655476497 ps
CPU time 9.26 seconds
Started Aug 25 11:30:16 AM UTC 24
Finished Aug 25 11:30:26 AM UTC 24
Peak memory 252988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830883629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1830883629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg.2690092034
Short name T388
Test name
Test status
Simulation time 197485318017 ps
CPU time 3013 seconds
Started Aug 25 11:31:07 AM UTC 24
Finished Aug 25 12:21:59 PM UTC 24
Peak memory 288552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690092034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2690092034
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/21.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg_stub_clk.2761528421
Short name T148
Test name
Test status
Simulation time 12088999587 ps
CPU time 732.13 seconds
Started Aug 25 11:31:17 AM UTC 24
Finished Aug 25 11:43:40 AM UTC 24
Peak memory 285508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761528421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2761528421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/21.alert_handler_ping_timeout.1441632720
Short name T353
Test name
Test status
Simulation time 21799070889 ps
CPU time 369.76 seconds
Started Aug 25 11:31:02 AM UTC 24
Finished Aug 25 11:37:18 AM UTC 24
Peak memory 262984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441632720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1441632720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_alerts.1411498678
Short name T449
Test name
Test status
Simulation time 145377981 ps
CPU time 21.32 seconds
Started Aug 25 11:30:04 AM UTC 24
Finished Aug 25 11:30:27 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411498678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1411498678
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/21.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_classes.4242571779
Short name T450
Test name
Test status
Simulation time 2316004062 ps
CPU time 59.33 seconds
Started Aug 25 11:30:05 AM UTC 24
Finished Aug 25 11:31:06 AM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242571779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.4242571779
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/21.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/21.alert_handler_smoke.819329499
Short name T446
Test name
Test status
Simulation time 49154366 ps
CPU time 13.2 seconds
Started Aug 25 11:29:50 AM UTC 24
Finished Aug 25 11:30:04 AM UTC 24
Peak memory 267072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819329499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.819329499
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/21.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all_with_rand_reset.1177366856
Short name T33
Test name
Test status
Simulation time 1495771319 ps
CPU time 276.75 seconds
Started Aug 25 11:33:58 AM UTC 24
Finished Aug 25 11:38:40 AM UTC 24
Peak memory 279420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1177366856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.a
lert_handler_stress_all_with_rand_reset.1177366856
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/22.alert_handler_entropy.1499212394
Short name T318
Test name
Test status
Simulation time 9346796947 ps
CPU time 1510.23 seconds
Started Aug 25 11:35:44 AM UTC 24
Finished Aug 25 12:01:16 PM UTC 24
Peak memory 285828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499212394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1499212394
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/22.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_alert_accum.614910250
Short name T461
Test name
Test status
Simulation time 4239035552 ps
CPU time 310.4 seconds
Started Aug 25 11:35:18 AM UTC 24
Finished Aug 25 11:40:34 AM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614910250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.614910250
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_intr_timeout.1804852765
Short name T455
Test name
Test status
Simulation time 2174011043 ps
CPU time 53.82 seconds
Started Aug 25 11:34:48 AM UTC 24
Finished Aug 25 11:35:44 AM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804852765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1804852765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg_stub_clk.152818037
Short name T550
Test name
Test status
Simulation time 25370101813 ps
CPU time 2023.9 seconds
Started Aug 25 11:35:57 AM UTC 24
Finished Aug 25 12:10:08 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152818037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.152818037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_alerts.4097664587
Short name T452
Test name
Test status
Simulation time 316869416 ps
CPU time 34.98 seconds
Started Aug 25 11:34:09 AM UTC 24
Finished Aug 25 11:34:46 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097664587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.4097664587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/22.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_classes.4260374259
Short name T453
Test name
Test status
Simulation time 437872858 ps
CPU time 30.41 seconds
Started Aug 25 11:34:46 AM UTC 24
Finished Aug 25 11:35:18 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260374259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.4260374259
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/22.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/22.alert_handler_sig_int_fail.1345401434
Short name T454
Test name
Test status
Simulation time 81764901 ps
CPU time 9.24 seconds
Started Aug 25 11:35:32 AM UTC 24
Finished Aug 25 11:35:42 AM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345401434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1345401434
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/22.alert_handler_smoke.1257783320
Short name T324
Test name
Test status
Simulation time 1718215326 ps
CPU time 43.71 seconds
Started Aug 25 11:34:02 AM UTC 24
Finished Aug 25 11:34:47 AM UTC 24
Peak memory 269128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257783320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1257783320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/22.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/23.alert_handler_entropy.1581045683
Short name T571
Test name
Test status
Simulation time 28147581576 ps
CPU time 2113.52 seconds
Started Aug 25 11:39:08 AM UTC 24
Finished Aug 25 12:14:50 PM UTC 24
Peak memory 301956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581045683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1581045683
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/23.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_alert_accum.1988145028
Short name T283
Test name
Test status
Simulation time 22080700613 ps
CPU time 242.33 seconds
Started Aug 25 11:39:02 AM UTC 24
Finished Aug 25 11:43:09 AM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988145028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1988145028
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_intr_timeout.3923967854
Short name T457
Test name
Test status
Simulation time 1148044650 ps
CPU time 54.78 seconds
Started Aug 25 11:38:58 AM UTC 24
Finished Aug 25 11:39:55 AM UTC 24
Peak memory 263292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923967854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3923967854
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg.1687785803
Short name T369
Test name
Test status
Simulation time 13826746346 ps
CPU time 1620.38 seconds
Started Aug 25 11:39:42 AM UTC 24
Finished Aug 25 12:07:05 PM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687785803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1687785803
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/23.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg_stub_clk.2795801801
Short name T606
Test name
Test status
Simulation time 51077048279 ps
CPU time 2406.62 seconds
Started Aug 25 11:39:51 AM UTC 24
Finished Aug 25 12:20:28 PM UTC 24
Peak memory 285508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795801801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2795801801
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/23.alert_handler_ping_timeout.1092210289
Short name T352
Test name
Test status
Simulation time 14094739532 ps
CPU time 818.53 seconds
Started Aug 25 11:39:15 AM UTC 24
Finished Aug 25 11:53:04 AM UTC 24
Peak memory 269456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092210289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1092210289
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_alerts.1796233080
Short name T458
Test name
Test status
Simulation time 712664651 ps
CPU time 73.77 seconds
Started Aug 25 11:38:46 AM UTC 24
Finished Aug 25 11:40:02 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796233080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1796233080
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/23.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_classes.3757003093
Short name T459
Test name
Test status
Simulation time 6809210712 ps
CPU time 81.35 seconds
Started Aug 25 11:38:48 AM UTC 24
Finished Aug 25 11:40:11 AM UTC 24
Peak memory 269212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757003093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3757003093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/23.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/23.alert_handler_sig_int_fail.3403416402
Short name T112
Test name
Test status
Simulation time 92624511 ps
CPU time 9.71 seconds
Started Aug 25 11:39:04 AM UTC 24
Finished Aug 25 11:39:14 AM UTC 24
Peak memory 263200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403416402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3403416402
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/23.alert_handler_smoke.2962578311
Short name T456
Test name
Test status
Simulation time 795297726 ps
CPU time 19.9 seconds
Started Aug 25 11:38:41 AM UTC 24
Finished Aug 25 11:39:02 AM UTC 24
Peak memory 263304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962578311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2962578311
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/23.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all_with_rand_reset.3727521599
Short name T153
Test name
Test status
Simulation time 1647166555 ps
CPU time 166.1 seconds
Started Aug 25 11:40:02 AM UTC 24
Finished Aug 25 11:42:52 AM UTC 24
Peak memory 285552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3727521599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.a
lert_handler_stress_all_with_rand_reset.3727521599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/24.alert_handler_entropy.2548361040
Short name T542
Test name
Test status
Simulation time 65940535387 ps
CPU time 1568.47 seconds
Started Aug 25 11:41:36 AM UTC 24
Finished Aug 25 12:08:08 PM UTC 24
Peak memory 297788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548361040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2548361040
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/24.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_alert_accum.2069304012
Short name T471
Test name
Test status
Simulation time 7925333095 ps
CPU time 356.1 seconds
Started Aug 25 11:40:41 AM UTC 24
Finished Aug 25 11:46:43 AM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069304012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2069304012
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_intr_timeout.90142558
Short name T462
Test name
Test status
Simulation time 82539755 ps
CPU time 4.59 seconds
Started Aug 25 11:40:35 AM UTC 24
Finished Aug 25 11:40:41 AM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90142558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc
_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.90142558
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/24.alert_handler_ping_timeout.2787148097
Short name T472
Test name
Test status
Simulation time 49766034130 ps
CPU time 363.86 seconds
Started Aug 25 11:41:44 AM UTC 24
Finished Aug 25 11:47:54 AM UTC 24
Peak memory 269200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787148097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2787148097
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_alerts.3920350441
Short name T463
Test name
Test status
Simulation time 738341750 ps
CPU time 55.95 seconds
Started Aug 25 11:40:22 AM UTC 24
Finished Aug 25 11:41:20 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920350441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3920350441
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/24.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/24.alert_handler_sig_int_fail.2935168036
Short name T351
Test name
Test status
Simulation time 532505807 ps
CPU time 47.29 seconds
Started Aug 25 11:41:21 AM UTC 24
Finished Aug 25 11:42:10 AM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935168036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2935168036
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/24.alert_handler_smoke.758810676
Short name T460
Test name
Test status
Simulation time 206109914 ps
CPU time 7.74 seconds
Started Aug 25 11:40:12 AM UTC 24
Finished Aug 25 11:40:21 AM UTC 24
Peak memory 263296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758810676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.758810676
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/24.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all.2578790199
Short name T299
Test name
Test status
Simulation time 114445791198 ps
CPU time 5036.92 seconds
Started Aug 25 11:42:11 AM UTC 24
Finished Aug 25 01:07:09 PM UTC 24
Peak memory 320988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578790199 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all.2578790199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/24.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_alert_accum.3201335954
Short name T466
Test name
Test status
Simulation time 2977748204 ps
CPU time 75.86 seconds
Started Aug 25 11:43:10 AM UTC 24
Finished Aug 25 11:44:28 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201335954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3201335954
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/25.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_intr_timeout.3991851674
Short name T296
Test name
Test status
Simulation time 1123515457 ps
CPU time 97.01 seconds
Started Aug 25 11:42:53 AM UTC 24
Finished Aug 25 11:44:32 AM UTC 24
Peak memory 263292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991851674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3991851674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg.2785795267
Short name T381
Test name
Test status
Simulation time 14880846798 ps
CPU time 1826.66 seconds
Started Aug 25 11:43:42 AM UTC 24
Finished Aug 25 12:14:32 PM UTC 24
Peak memory 301956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785795267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2785795267
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/25.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg_stub_clk.3301325305
Short name T327
Test name
Test status
Simulation time 31283101261 ps
CPU time 1620.76 seconds
Started Aug 25 11:43:59 AM UTC 24
Finished Aug 25 12:11:23 PM UTC 24
Peak memory 295824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301325305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3301325305
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/25.alert_handler_ping_timeout.1325238536
Short name T479
Test name
Test status
Simulation time 23322807225 ps
CPU time 394.67 seconds
Started Aug 25 11:43:36 AM UTC 24
Finished Aug 25 11:50:17 AM UTC 24
Peak memory 269124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325238536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1325238536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_alerts.3974424302
Short name T465
Test name
Test status
Simulation time 8761085325 ps
CPU time 70.83 seconds
Started Aug 25 11:42:45 AM UTC 24
Finished Aug 25 11:43:58 AM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974424302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3974424302
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/25.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_classes.744728518
Short name T134
Test name
Test status
Simulation time 994926048 ps
CPU time 32.86 seconds
Started Aug 25 11:42:52 AM UTC 24
Finished Aug 25 11:43:26 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744728518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.744728518
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/25.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/25.alert_handler_sig_int_fail.583415090
Short name T349
Test name
Test status
Simulation time 1253105365 ps
CPU time 43.69 seconds
Started Aug 25 11:43:27 AM UTC 24
Finished Aug 25 11:44:13 AM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583415090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.583415090
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/25.alert_handler_smoke.374732770
Short name T464
Test name
Test status
Simulation time 166128198 ps
CPU time 10.01 seconds
Started Aug 25 11:42:39 AM UTC 24
Finished Aug 25 11:42:50 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374732770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.374732770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/25.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all.37506702
Short name T286
Test name
Test status
Simulation time 13547305309 ps
CPU time 1251.06 seconds
Started Aug 25 11:44:13 AM UTC 24
Finished Aug 25 12:05:23 PM UTC 24
Peak memory 279616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37506702 -assert nopostproc +UVM_TES
TNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all.37506702
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/25.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all_with_rand_reset.182690102
Short name T73
Test name
Test status
Simulation time 1745981515 ps
CPU time 333.94 seconds
Started Aug 25 11:44:19 AM UTC 24
Finished Aug 25 11:49:58 AM UTC 24
Peak memory 285556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=182690102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.al
ert_handler_stress_all_with_rand_reset.182690102
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/26.alert_handler_entropy.4238499743
Short name T642
Test name
Test status
Simulation time 27365461493 ps
CPU time 2609.01 seconds
Started Aug 25 11:46:00 AM UTC 24
Finished Aug 25 12:30:05 PM UTC 24
Peak memory 295816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238499743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.4238499743
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/26.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_alert_accum.3182754652
Short name T476
Test name
Test status
Simulation time 9417058206 ps
CPU time 233.72 seconds
Started Aug 25 11:45:36 AM UTC 24
Finished Aug 25 11:49:33 AM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182754652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3182754652
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/26.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_intr_timeout.4264059500
Short name T470
Test name
Test status
Simulation time 395836533 ps
CPU time 41.63 seconds
Started Aug 25 11:45:15 AM UTC 24
Finished Aug 25 11:45:59 AM UTC 24
Peak memory 263292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264059500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.4264059500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/26.alert_handler_ping_timeout.2670561709
Short name T356
Test name
Test status
Simulation time 14570445527 ps
CPU time 835.59 seconds
Started Aug 25 11:46:04 AM UTC 24
Finished Aug 25 12:00:11 PM UTC 24
Peak memory 263056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670561709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2670561709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_alerts.424417057
Short name T467
Test name
Test status
Simulation time 207454847 ps
CPU time 21 seconds
Started Aug 25 11:44:33 AM UTC 24
Finished Aug 25 11:44:56 AM UTC 24
Peak memory 267000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424417057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.424417057
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/26.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_classes.2017367538
Short name T469
Test name
Test status
Simulation time 662909329 ps
CPU time 51.51 seconds
Started Aug 25 11:44:56 AM UTC 24
Finished Aug 25 11:45:49 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017367538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2017367538
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/26.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/26.alert_handler_sig_int_fail.1917088094
Short name T72
Test name
Test status
Simulation time 225084803 ps
CPU time 11.64 seconds
Started Aug 25 11:45:51 AM UTC 24
Finished Aug 25 11:46:04 AM UTC 24
Peak memory 267032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917088094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1917088094
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/26.alert_handler_smoke.2021937034
Short name T468
Test name
Test status
Simulation time 684744886 ps
CPU time 42.78 seconds
Started Aug 25 11:44:29 AM UTC 24
Finished Aug 25 11:45:14 AM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021937034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2021937034
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/26.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all.938808378
Short name T325
Test name
Test status
Simulation time 75391856236 ps
CPU time 4081.77 seconds
Started Aug 25 11:46:44 AM UTC 24
Finished Aug 25 12:55:40 PM UTC 24
Peak memory 304672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938808378 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all.938808378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/26.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all_with_rand_reset.1127461098
Short name T308
Test name
Test status
Simulation time 4322639960 ps
CPU time 510.1 seconds
Started Aug 25 11:47:23 AM UTC 24
Finished Aug 25 11:56:01 AM UTC 24
Peak memory 281520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1127461098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.a
lert_handler_stress_all_with_rand_reset.1127461098
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/27.alert_handler_entropy.2988565973
Short name T527
Test name
Test status
Simulation time 16869199699 ps
CPU time 938.85 seconds
Started Aug 25 11:48:30 AM UTC 24
Finished Aug 25 12:04:24 PM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988565973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2988565973
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/27.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_alert_accum.3498557388
Short name T477
Test name
Test status
Simulation time 692956477 ps
CPU time 85.25 seconds
Started Aug 25 11:48:17 AM UTC 24
Finished Aug 25 11:49:44 AM UTC 24
Peak memory 262896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498557388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3498557388
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/27.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_intr_timeout.1019750500
Short name T475
Test name
Test status
Simulation time 250199560 ps
CPU time 28.2 seconds
Started Aug 25 11:48:13 AM UTC 24
Finished Aug 25 11:48:43 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019750500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1019750500
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg.3952475530
Short name T373
Test name
Test status
Simulation time 20691458818 ps
CPU time 1470.37 seconds
Started Aug 25 11:48:49 AM UTC 24
Finished Aug 25 12:13:39 PM UTC 24
Peak memory 295740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952475530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3952475530
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/27.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg_stub_clk.1829876347
Short name T618
Test name
Test status
Simulation time 49754030803 ps
CPU time 2099.13 seconds
Started Aug 25 11:48:56 AM UTC 24
Finished Aug 25 12:24:24 PM UTC 24
Peak memory 301892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829876347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1829876347
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/27.alert_handler_ping_timeout.606099104
Short name T364
Test name
Test status
Simulation time 6051515882 ps
CPU time 273.92 seconds
Started Aug 25 11:48:44 AM UTC 24
Finished Aug 25 11:53:22 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606099104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.606099104
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_alerts.3610631544
Short name T473
Test name
Test status
Simulation time 217881821 ps
CPU time 21.76 seconds
Started Aug 25 11:47:49 AM UTC 24
Finished Aug 25 11:48:12 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610631544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3610631544
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/27.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_classes.754664002
Short name T309
Test name
Test status
Simulation time 405562526 ps
CPU time 33.37 seconds
Started Aug 25 11:47:55 AM UTC 24
Finished Aug 25 11:48:30 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754664002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.754664002
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/27.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/27.alert_handler_sig_int_fail.596614243
Short name T297
Test name
Test status
Simulation time 179152043 ps
CPU time 16.44 seconds
Started Aug 25 11:48:30 AM UTC 24
Finished Aug 25 11:48:48 AM UTC 24
Peak memory 267328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596614243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.596614243
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/27.alert_handler_smoke.3718381794
Short name T474
Test name
Test status
Simulation time 2010479923 ps
CPU time 49.51 seconds
Started Aug 25 11:47:25 AM UTC 24
Finished Aug 25 11:48:16 AM UTC 24
Peak memory 269064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718381794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3718381794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/27.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all.900659440
Short name T691
Test name
Test status
Simulation time 116258758313 ps
CPU time 4947.7 seconds
Started Aug 25 11:49:16 AM UTC 24
Finished Aug 25 01:12:47 PM UTC 24
Peak memory 321248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900659440 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all.900659440
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/27.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all_with_rand_reset.3158444895
Short name T326
Test name
Test status
Simulation time 16252209606 ps
CPU time 992.41 seconds
Started Aug 25 11:49:35 AM UTC 24
Finished Aug 25 12:06:22 PM UTC 24
Peak memory 296192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3158444895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.a
lert_handler_stress_all_with_rand_reset.3158444895
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_alert_accum.887457991
Short name T498
Test name
Test status
Simulation time 17880299718 ps
CPU time 424.23 seconds
Started Aug 25 11:50:34 AM UTC 24
Finished Aug 25 11:57:44 AM UTC 24
Peak memory 269340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887457991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.887457991
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/28.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_intr_timeout.3156351504
Short name T481
Test name
Test status
Simulation time 678512516 ps
CPU time 28.84 seconds
Started Aug 25 11:50:18 AM UTC 24
Finished Aug 25 11:50:48 AM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156351504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3156351504
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg.910459632
Short name T386
Test name
Test status
Simulation time 14909856548 ps
CPU time 1969.49 seconds
Started Aug 25 11:51:09 AM UTC 24
Finished Aug 25 12:24:27 PM UTC 24
Peak memory 302204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910459632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.910459632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/28.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg_stub_clk.305076309
Short name T664
Test name
Test status
Simulation time 29072850026 ps
CPU time 2789.55 seconds
Started Aug 25 11:51:34 AM UTC 24
Finished Aug 25 12:38:42 PM UTC 24
Peak memory 304612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305076309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.305076309
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/28.alert_handler_ping_timeout.4159120513
Short name T362
Test name
Test status
Simulation time 57172795778 ps
CPU time 719.09 seconds
Started Aug 25 11:50:49 AM UTC 24
Finished Aug 25 12:02:58 PM UTC 24
Peak memory 262984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159120513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4159120513
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_alerts.2476734120
Short name T478
Test name
Test status
Simulation time 191746975 ps
CPU time 14.28 seconds
Started Aug 25 11:49:59 AM UTC 24
Finished Aug 25 11:50:15 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476734120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2476734120
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/28.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_classes.4289404674
Short name T128
Test name
Test status
Simulation time 195557678 ps
CPU time 28.67 seconds
Started Aug 25 11:50:15 AM UTC 24
Finished Aug 25 11:50:45 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289404674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.4289404674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/28.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/28.alert_handler_sig_int_fail.1445371065
Short name T483
Test name
Test status
Simulation time 4024448585 ps
CPU time 100.45 seconds
Started Aug 25 11:50:35 AM UTC 24
Finished Aug 25 11:52:18 AM UTC 24
Peak memory 269216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445371065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1445371065
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/28.alert_handler_smoke.568085920
Short name T480
Test name
Test status
Simulation time 1100377437 ps
CPU time 46.55 seconds
Started Aug 25 11:49:45 AM UTC 24
Finished Aug 25 11:50:33 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568085920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.568085920
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/28.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all.4138336783
Short name T292
Test name
Test status
Simulation time 246215855641 ps
CPU time 3969.58 seconds
Started Aug 25 11:51:44 AM UTC 24
Finished Aug 25 12:58:45 PM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138336783 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all.4138336783
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/28.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all_with_rand_reset.3897444330
Short name T263
Test name
Test status
Simulation time 6517837829 ps
CPU time 331.36 seconds
Started Aug 25 11:51:55 AM UTC 24
Finished Aug 25 11:57:31 AM UTC 24
Peak memory 279480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3897444330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.a
lert_handler_stress_all_with_rand_reset.3897444330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/29.alert_handler_entropy.297122482
Short name T120
Test name
Test status
Simulation time 23940966605 ps
CPU time 1863.46 seconds
Started Aug 25 11:54:05 AM UTC 24
Finished Aug 25 12:25:35 PM UTC 24
Peak memory 301892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297122482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.297122482
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/29.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_alert_accum.1804137276
Short name T317
Test name
Test status
Simulation time 2047371968 ps
CPU time 170.9 seconds
Started Aug 25 11:53:28 AM UTC 24
Finished Aug 25 11:56:23 AM UTC 24
Peak memory 264948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804137276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1804137276
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/29.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_intr_timeout.1178986152
Short name T487
Test name
Test status
Simulation time 334849258 ps
CPU time 46.5 seconds
Started Aug 25 11:53:23 AM UTC 24
Finished Aug 25 11:54:11 AM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178986152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1178986152
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg.760545962
Short name T370
Test name
Test status
Simulation time 51193418286 ps
CPU time 1463.32 seconds
Started Aug 25 11:54:14 AM UTC 24
Finished Aug 25 12:18:56 PM UTC 24
Peak memory 295804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760545962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.760545962
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/29.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg_stub_clk.4237772732
Short name T631
Test name
Test status
Simulation time 23004393659 ps
CPU time 1978.86 seconds
Started Aug 25 11:54:19 AM UTC 24
Finished Aug 25 12:27:46 PM UTC 24
Peak memory 295748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237772732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.4237772732
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/29.alert_handler_ping_timeout.207920993
Short name T366
Test name
Test status
Simulation time 18732893379 ps
CPU time 583.22 seconds
Started Aug 25 11:54:13 AM UTC 24
Finished Aug 25 12:04:05 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207920993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.207920993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_alerts.3815297781
Short name T484
Test name
Test status
Simulation time 930510517 ps
CPU time 30.11 seconds
Started Aug 25 11:52:56 AM UTC 24
Finished Aug 25 11:53:27 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815297781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3815297781
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/29.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_classes.4247596315
Short name T486
Test name
Test status
Simulation time 765369374 ps
CPU time 56.85 seconds
Started Aug 25 11:53:05 AM UTC 24
Finished Aug 25 11:54:04 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247596315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.4247596315
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/29.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/29.alert_handler_sig_int_fail.1246066092
Short name T304
Test name
Test status
Simulation time 487357574 ps
CPU time 22.73 seconds
Started Aug 25 11:53:59 AM UTC 24
Finished Aug 25 11:54:23 AM UTC 24
Peak memory 269080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246066092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1246066092
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/29.alert_handler_smoke.3390991739
Short name T485
Test name
Test status
Simulation time 2141107712 ps
CPU time 97.26 seconds
Started Aug 25 11:52:18 AM UTC 24
Finished Aug 25 11:53:58 AM UTC 24
Peak memory 269128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390991739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3390991739
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/29.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all.991948211
Short name T294
Test name
Test status
Simulation time 12277804627 ps
CPU time 1588.98 seconds
Started Aug 25 11:54:23 AM UTC 24
Finished Aug 25 12:21:14 PM UTC 24
Peak memory 298172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991948211 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all.991948211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/29.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/3.alert_handler_alert_accum_saturation.3613578736
Short name T75
Test name
Test status
Simulation time 452816252 ps
CPU time 4.37 seconds
Started Aug 25 11:12:56 AM UTC 24
Finished Aug 25 11:13:02 AM UTC 24
Peak memory 263172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613578736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3613578736
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy.3589132368
Short name T154
Test name
Test status
Simulation time 84116129735 ps
CPU time 2001.92 seconds
Started Aug 25 11:12:47 AM UTC 24
Finished Aug 25 11:46:37 AM UTC 24
Peak memory 288300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589132368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3589132368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_alert_accum.1489781573
Short name T276
Test name
Test status
Simulation time 58199047292 ps
CPU time 499.41 seconds
Started Aug 25 11:12:45 AM UTC 24
Finished Aug 25 11:21:13 AM UTC 24
Peak memory 265012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489781573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1489781573
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_intr_timeout.874590708
Short name T30
Test name
Test status
Simulation time 153076232 ps
CPU time 18.64 seconds
Started Aug 25 11:12:36 AM UTC 24
Finished Aug 25 11:12:56 AM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874590708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.874590708
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg.2381527116
Short name T376
Test name
Test status
Simulation time 55059260397 ps
CPU time 2791.66 seconds
Started Aug 25 11:12:48 AM UTC 24
Finished Aug 25 11:59:58 AM UTC 24
Peak memory 304940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381527116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2381527116
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg_stub_clk.3823126526
Short name T489
Test name
Test status
Simulation time 205521829071 ps
CPU time 2493.39 seconds
Started Aug 25 11:12:51 AM UTC 24
Finished Aug 25 11:54:57 AM UTC 24
Peak memory 300512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823126526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3823126526
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/3.alert_handler_ping_timeout.1031100915
Short name T18
Test name
Test status
Simulation time 6455760850 ps
CPU time 184.35 seconds
Started Aug 25 11:12:48 AM UTC 24
Finished Aug 25 11:15:56 AM UTC 24
Peak memory 269448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031100915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1031100915
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_alerts.1525246210
Short name T32
Test name
Test status
Simulation time 640907519 ps
CPU time 20.87 seconds
Started Aug 25 11:12:35 AM UTC 24
Finished Aug 25 11:12:58 AM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525246210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1525246210
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_classes.3939332037
Short name T53
Test name
Test status
Simulation time 225070778 ps
CPU time 26.93 seconds
Started Aug 25 11:12:36 AM UTC 24
Finished Aug 25 11:13:05 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939332037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3939332037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/3.alert_handler_sig_int_fail.4283049006
Short name T54
Test name
Test status
Simulation time 273653445 ps
CPU time 31.31 seconds
Started Aug 25 11:12:46 AM UTC 24
Finished Aug 25 11:13:18 AM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283049006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.4283049006
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/3.alert_handler_smoke.2511507617
Short name T413
Test name
Test status
Simulation time 2129563925 ps
CPU time 100.51 seconds
Started Aug 25 11:12:34 AM UTC 24
Finished Aug 25 11:14:18 AM UTC 24
Peak memory 269124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511507617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2511507617
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all.2219040273
Short name T38
Test name
Test status
Simulation time 11371284909 ps
CPU time 365.7 seconds
Started Aug 25 11:12:55 AM UTC 24
Finished Aug 25 11:19:07 AM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219040273 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all.2219040273
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all_with_rand_reset.544570353
Short name T144
Test name
Test status
Simulation time 11132745902 ps
CPU time 555.44 seconds
Started Aug 25 11:12:57 AM UTC 24
Finished Aug 25 11:22:21 AM UTC 24
Peak memory 281860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=544570353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.ale
rt_handler_stress_all_with_rand_reset.544570353
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_alert_accum.1939945574
Short name T499
Test name
Test status
Simulation time 8362911320 ps
CPU time 143.28 seconds
Started Aug 25 11:55:30 AM UTC 24
Finished Aug 25 11:57:57 AM UTC 24
Peak memory 269208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939945574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1939945574
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/30.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_intr_timeout.4160683179
Short name T495
Test name
Test status
Simulation time 401937625 ps
CPU time 26.58 seconds
Started Aug 25 11:55:22 AM UTC 24
Finished Aug 25 11:55:50 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160683179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.4160683179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg_stub_clk.3475433425
Short name T659
Test name
Test status
Simulation time 127980814364 ps
CPU time 2442.02 seconds
Started Aug 25 11:56:11 AM UTC 24
Finished Aug 25 12:37:25 PM UTC 24
Peak memory 285648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475433425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3475433425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/30.alert_handler_ping_timeout.1375513078
Short name T516
Test name
Test status
Simulation time 17555318875 ps
CPU time 388.55 seconds
Started Aug 25 11:55:51 AM UTC 24
Finished Aug 25 12:02:25 PM UTC 24
Peak memory 263056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375513078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1375513078
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_alerts.3702436434
Short name T493
Test name
Test status
Simulation time 203531140 ps
CPU time 27.56 seconds
Started Aug 25 11:55:00 AM UTC 24
Finished Aug 25 11:55:29 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702436434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3702436434
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/30.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_classes.2580077536
Short name T491
Test name
Test status
Simulation time 168104437 ps
CPU time 11.4 seconds
Started Aug 25 11:55:09 AM UTC 24
Finished Aug 25 11:55:22 AM UTC 24
Peak memory 264952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580077536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2580077536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/30.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/30.alert_handler_smoke.1624242483
Short name T490
Test name
Test status
Simulation time 263497408 ps
CPU time 21.65 seconds
Started Aug 25 11:54:45 AM UTC 24
Finished Aug 25 11:55:08 AM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624242483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1624242483
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/30.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all.1049613671
Short name T678
Test name
Test status
Simulation time 43568809105 ps
CPU time 3591.08 seconds
Started Aug 25 11:56:15 AM UTC 24
Finished Aug 25 12:56:52 PM UTC 24
Peak memory 302628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049613671 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all.1049613671
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/30.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all_with_rand_reset.308276241
Short name T277
Test name
Test status
Simulation time 2211750126 ps
CPU time 429.77 seconds
Started Aug 25 11:56:24 AM UTC 24
Finished Aug 25 12:03:41 PM UTC 24
Peak memory 281600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=308276241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.al
ert_handler_stress_all_with_rand_reset.308276241
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/31.alert_handler_entropy.2762413201
Short name T675
Test name
Test status
Simulation time 139306473444 ps
CPU time 3318.32 seconds
Started Aug 25 11:58:00 AM UTC 24
Finished Aug 25 12:54:05 PM UTC 24
Peak memory 304744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762413201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2762413201
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/31.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_alert_accum.281346678
Short name T519
Test name
Test status
Simulation time 3785189971 ps
CPU time 306.43 seconds
Started Aug 25 11:57:46 AM UTC 24
Finished Aug 25 12:02:57 PM UTC 24
Peak memory 265012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281346678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.281346678
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/31.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_intr_timeout.3191640323
Short name T501
Test name
Test status
Simulation time 436081174 ps
CPU time 48.43 seconds
Started Aug 25 11:57:33 AM UTC 24
Finished Aug 25 11:58:23 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191640323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3191640323
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg_stub_clk.2010964471
Short name T667
Test name
Test status
Simulation time 59707547098 ps
CPU time 2508.8 seconds
Started Aug 25 11:58:21 AM UTC 24
Finished Aug 25 12:40:45 PM UTC 24
Peak memory 301892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010964471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2010964471
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/31.alert_handler_ping_timeout.1040325775
Short name T358
Test name
Test status
Simulation time 47692284609 ps
CPU time 771.51 seconds
Started Aug 25 11:58:07 AM UTC 24
Finished Aug 25 12:11:10 PM UTC 24
Peak memory 263312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040325775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1040325775
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_alerts.2959110698
Short name T497
Test name
Test status
Simulation time 71300996 ps
CPU time 4.15 seconds
Started Aug 25 11:57:05 AM UTC 24
Finished Aug 25 11:57:10 AM UTC 24
Peak memory 252992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959110698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2959110698
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/31.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_classes.1721382168
Short name T155
Test name
Test status
Simulation time 514460468 ps
CPU time 77.56 seconds
Started Aug 25 11:57:11 AM UTC 24
Finished Aug 25 11:58:31 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721382168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1721382168
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/31.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/31.alert_handler_sig_int_fail.1484497910
Short name T502
Test name
Test status
Simulation time 1715757571 ps
CPU time 44.14 seconds
Started Aug 25 11:57:57 AM UTC 24
Finished Aug 25 11:58:43 AM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484497910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1484497910
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/31.alert_handler_smoke.2257744508
Short name T496
Test name
Test status
Simulation time 1192015519 ps
CPU time 37.73 seconds
Started Aug 25 11:56:25 AM UTC 24
Finished Aug 25 11:57:04 AM UTC 24
Peak memory 269384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257744508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2257744508
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/31.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all.2503402720
Short name T665
Test name
Test status
Simulation time 25364910610 ps
CPU time 2390.46 seconds
Started Aug 25 11:58:24 AM UTC 24
Finished Aug 25 12:38:45 PM UTC 24
Peak memory 298176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503402720 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all.2503402720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/31.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/32.alert_handler_entropy.1071377939
Short name T653
Test name
Test status
Simulation time 168726918053 ps
CPU time 1925.62 seconds
Started Aug 25 11:59:31 AM UTC 24
Finished Aug 25 12:32:02 PM UTC 24
Peak memory 283452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071377939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1071377939
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/32.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_alert_accum.1278953268
Short name T531
Test name
Test status
Simulation time 57714886513 ps
CPU time 307.57 seconds
Started Aug 25 11:59:28 AM UTC 24
Finished Aug 25 12:04:41 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278953268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1278953268
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/32.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_intr_timeout.1294780516
Short name T505
Test name
Test status
Simulation time 3947125487 ps
CPU time 32.48 seconds
Started Aug 25 11:59:15 AM UTC 24
Finished Aug 25 11:59:49 AM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294780516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1294780516
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg.3709695818
Short name T393
Test name
Test status
Simulation time 23799891820 ps
CPU time 2158.5 seconds
Started Aug 25 12:00:01 PM UTC 24
Finished Aug 25 12:36:32 PM UTC 24
Peak memory 285828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709695818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3709695818
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/32.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg_stub_clk.3860186004
Short name T672
Test name
Test status
Simulation time 52599913283 ps
CPU time 2998.76 seconds
Started Aug 25 12:00:02 PM UTC 24
Finished Aug 25 12:50:45 PM UTC 24
Peak memory 300852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860186004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3860186004
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/32.alert_handler_ping_timeout.1739683111
Short name T517
Test name
Test status
Simulation time 11983068076 ps
CPU time 169.06 seconds
Started Aug 25 11:59:50 AM UTC 24
Finished Aug 25 12:02:43 PM UTC 24
Peak memory 263056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739683111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1739683111
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_alerts.740463226
Short name T504
Test name
Test status
Simulation time 283699880 ps
CPU time 34.74 seconds
Started Aug 25 11:58:54 AM UTC 24
Finished Aug 25 11:59:31 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740463226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.740463226
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/32.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_classes.2655302962
Short name T506
Test name
Test status
Simulation time 520521047 ps
CPU time 46.49 seconds
Started Aug 25 11:59:13 AM UTC 24
Finished Aug 25 12:00:01 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655302962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2655302962
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/32.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/32.alert_handler_sig_int_fail.2994850767
Short name T508
Test name
Test status
Simulation time 4371503953 ps
CPU time 106.17 seconds
Started Aug 25 11:59:28 AM UTC 24
Finished Aug 25 12:01:17 PM UTC 24
Peak memory 263328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994850767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2994850767
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/32.alert_handler_smoke.4158712812
Short name T503
Test name
Test status
Simulation time 274155021 ps
CPU time 8.58 seconds
Started Aug 25 11:58:44 AM UTC 24
Finished Aug 25 11:58:54 AM UTC 24
Peak memory 262984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158712812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.4158712812
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/32.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_alert_accum.1178288420
Short name T520
Test name
Test status
Simulation time 2656440657 ps
CPU time 83.41 seconds
Started Aug 25 12:01:33 PM UTC 24
Finished Aug 25 12:02:59 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178288420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1178288420
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/33.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_intr_timeout.234680190
Short name T513
Test name
Test status
Simulation time 82158881 ps
CPU time 5.95 seconds
Started Aug 25 12:01:33 PM UTC 24
Finished Aug 25 12:01:40 PM UTC 24
Peak memory 252660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234680190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.234680190
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg_stub_clk.2757425072
Short name T682
Test name
Test status
Simulation time 74527782370 ps
CPU time 3403.38 seconds
Started Aug 25 12:02:03 PM UTC 24
Finished Aug 25 12:59:31 PM UTC 24
Peak memory 298472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757425072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2757425072
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/33.alert_handler_ping_timeout.2466347283
Short name T365
Test name
Test status
Simulation time 12672477069 ps
CPU time 728.97 seconds
Started Aug 25 12:01:50 PM UTC 24
Finished Aug 25 12:14:09 PM UTC 24
Peak memory 263056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466347283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2466347283
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_alerts.1025601642
Short name T518
Test name
Test status
Simulation time 1877974863 ps
CPU time 90.57 seconds
Started Aug 25 12:01:19 PM UTC 24
Finished Aug 25 12:02:52 PM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025601642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1025601642
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/33.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_classes.3208865913
Short name T515
Test name
Test status
Simulation time 660270604 ps
CPU time 39 seconds
Started Aug 25 12:01:21 PM UTC 24
Finished Aug 25 12:02:01 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208865913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3208865913
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/33.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/33.alert_handler_sig_int_fail.2048628037
Short name T525
Test name
Test status
Simulation time 2015935559 ps
CPU time 106.58 seconds
Started Aug 25 12:01:34 PM UTC 24
Finished Aug 25 12:03:23 PM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048628037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2048628037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/33.alert_handler_smoke.4218443172
Short name T512
Test name
Test status
Simulation time 363516105 ps
CPU time 12.12 seconds
Started Aug 25 12:01:19 PM UTC 24
Finished Aug 25 12:01:32 PM UTC 24
Peak memory 264964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218443172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.4218443172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/33.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all.2283201781
Short name T535
Test name
Test status
Simulation time 5926885843 ps
CPU time 222.02 seconds
Started Aug 25 12:02:26 PM UTC 24
Finished Aug 25 12:06:12 PM UTC 24
Peak memory 265088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283201781 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all.2283201781
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/33.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all_with_rand_reset.2404455923
Short name T545
Test name
Test status
Simulation time 6495508571 ps
CPU time 394.47 seconds
Started Aug 25 12:02:44 PM UTC 24
Finished Aug 25 12:09:25 PM UTC 24
Peak memory 279808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2404455923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.a
lert_handler_stress_all_with_rand_reset.2404455923
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/34.alert_handler_entropy.3758765359
Short name T639
Test name
Test status
Simulation time 49050305106 ps
CPU time 1573.29 seconds
Started Aug 25 12:03:07 PM UTC 24
Finished Aug 25 12:29:41 PM UTC 24
Peak memory 295812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758765359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3758765359
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/34.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_alert_accum.4068935676
Short name T528
Test name
Test status
Simulation time 2908201612 ps
CPU time 79.99 seconds
Started Aug 25 12:03:02 PM UTC 24
Finished Aug 25 12:04:24 PM UTC 24
Peak memory 262964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068935676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.4068935676
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/34.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_intr_timeout.2828569747
Short name T130
Test name
Test status
Simulation time 9844076146 ps
CPU time 48.47 seconds
Started Aug 25 12:03:00 PM UTC 24
Finished Aug 25 12:03:50 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828569747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2828569747
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg_stub_clk.3102883119
Short name T669
Test name
Test status
Simulation time 21620214786 ps
CPU time 2245.92 seconds
Started Aug 25 12:03:41 PM UTC 24
Finished Aug 25 12:41:39 PM UTC 24
Peak memory 285840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102883119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3102883119
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/34.alert_handler_ping_timeout.466905765
Short name T586
Test name
Test status
Simulation time 86917940891 ps
CPU time 827.42 seconds
Started Aug 25 12:03:15 PM UTC 24
Finished Aug 25 12:17:14 PM UTC 24
Peak memory 263044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466905765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.466905765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_alerts.1114770219
Short name T526
Test name
Test status
Simulation time 256048725 ps
CPU time 50.79 seconds
Started Aug 25 12:02:58 PM UTC 24
Finished Aug 25 12:03:51 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114770219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1114770219
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/34.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_classes.1538916961
Short name T529
Test name
Test status
Simulation time 4329239250 ps
CPU time 87.89 seconds
Started Aug 25 12:03:00 PM UTC 24
Finished Aug 25 12:04:30 PM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538916961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1538916961
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/34.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/34.alert_handler_sig_int_fail.863099407
Short name T524
Test name
Test status
Simulation time 618018312 ps
CPU time 10.42 seconds
Started Aug 25 12:03:02 PM UTC 24
Finished Aug 25 12:03:14 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863099407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.863099407
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/34.alert_handler_smoke.623652535
Short name T522
Test name
Test status
Simulation time 53341517 ps
CPU time 7.69 seconds
Started Aug 25 12:02:52 PM UTC 24
Finished Aug 25 12:03:01 PM UTC 24
Peak memory 267072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623652535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.623652535
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/34.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all.2148602069
Short name T694
Test name
Test status
Simulation time 185928745884 ps
CPU time 4176.11 seconds
Started Aug 25 12:03:51 PM UTC 24
Finished Aug 25 01:14:21 PM UTC 24
Peak memory 304676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148602069 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all.2148602069
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/34.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all_with_rand_reset.3666010592
Short name T115
Test name
Test status
Simulation time 8358735417 ps
CPU time 272.11 seconds
Started Aug 25 12:03:52 PM UTC 24
Finished Aug 25 12:08:29 PM UTC 24
Peak memory 285624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3666010592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.a
lert_handler_stress_all_with_rand_reset.3666010592
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_alert_accum.267050571
Short name T540
Test name
Test status
Simulation time 2483821370 ps
CPU time 153.12 seconds
Started Aug 25 12:04:37 PM UTC 24
Finished Aug 25 12:07:13 PM UTC 24
Peak memory 269212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267050571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.267050571
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/35.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_intr_timeout.1973717965
Short name T532
Test name
Test status
Simulation time 102058402 ps
CPU time 11.47 seconds
Started Aug 25 12:04:30 PM UTC 24
Finished Aug 25 12:04:43 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973717965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1973717965
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg.251354795
Short name T391
Test name
Test status
Simulation time 32698628761 ps
CPU time 1076.45 seconds
Started Aug 25 12:04:53 PM UTC 24
Finished Aug 25 12:23:05 PM UTC 24
Peak memory 285564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251354795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.251354795
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/35.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg_stub_clk.2912489080
Short name T638
Test name
Test status
Simulation time 18854070905 ps
CPU time 1408.15 seconds
Started Aug 25 12:05:04 PM UTC 24
Finished Aug 25 12:28:52 PM UTC 24
Peak memory 285584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912489080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2912489080
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/35.alert_handler_ping_timeout.2677871663
Short name T573
Test name
Test status
Simulation time 20187119299 ps
CPU time 595.24 seconds
Started Aug 25 12:04:51 PM UTC 24
Finished Aug 25 12:14:54 PM UTC 24
Peak memory 262988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677871663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2677871663
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_alerts.478285391
Short name T530
Test name
Test status
Simulation time 307503079 ps
CPU time 9.28 seconds
Started Aug 25 12:04:26 PM UTC 24
Finished Aug 25 12:04:37 PM UTC 24
Peak memory 265016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478285391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.478285391
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/35.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_classes.3173638949
Short name T114
Test name
Test status
Simulation time 2360246350 ps
CPU time 35.64 seconds
Started Aug 25 12:04:26 PM UTC 24
Finished Aug 25 12:05:03 PM UTC 24
Peak memory 269184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173638949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3173638949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/35.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/35.alert_handler_sig_int_fail.2359672503
Short name T312
Test name
Test status
Simulation time 1146894901 ps
CPU time 86.7 seconds
Started Aug 25 12:04:43 PM UTC 24
Finished Aug 25 12:06:11 PM UTC 24
Peak memory 269408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359672503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2359672503
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/35.alert_handler_smoke.3202543277
Short name T534
Test name
Test status
Simulation time 2137276802 ps
CPU time 79.29 seconds
Started Aug 25 12:04:06 PM UTC 24
Finished Aug 25 12:05:27 PM UTC 24
Peak memory 269384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202543277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3202543277
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/35.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all.3060941293
Short name T301
Test name
Test status
Simulation time 188737019855 ps
CPU time 4455.96 seconds
Started Aug 25 12:05:24 PM UTC 24
Finished Aug 25 01:20:39 PM UTC 24
Peak memory 321316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060941293 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all.3060941293
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/35.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all_with_rand_reset.2495593527
Short name T264
Test name
Test status
Simulation time 2088663736 ps
CPU time 212.72 seconds
Started Aug 25 12:05:28 PM UTC 24
Finished Aug 25 12:09:05 PM UTC 24
Peak memory 279488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2495593527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.a
lert_handler_stress_all_with_rand_reset.2495593527
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/36.alert_handler_entropy.2903361633
Short name T674
Test name
Test status
Simulation time 48016376975 ps
CPU time 2793.94 seconds
Started Aug 25 12:06:52 PM UTC 24
Finished Aug 25 12:54:02 PM UTC 24
Peak memory 295740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903361633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2903361633
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/36.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_alert_accum.3111414850
Short name T546
Test name
Test status
Simulation time 1532443500 ps
CPU time 159.29 seconds
Started Aug 25 12:06:43 PM UTC 24
Finished Aug 25 12:09:25 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111414850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3111414850
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/36.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_intr_timeout.1493191172
Short name T537
Test name
Test status
Simulation time 230932365 ps
CPU time 7.76 seconds
Started Aug 25 12:06:32 PM UTC 24
Finished Aug 25 12:06:41 PM UTC 24
Peak memory 265276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493191172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1493191172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg_stub_clk.1191131314
Short name T685
Test name
Test status
Simulation time 41475789386 ps
CPU time 3246.23 seconds
Started Aug 25 12:07:07 PM UTC 24
Finished Aug 25 01:01:53 PM UTC 24
Peak memory 302568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191131314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1191131314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/36.alert_handler_ping_timeout.596663331
Short name T357
Test name
Test status
Simulation time 11269862732 ps
CPU time 186.92 seconds
Started Aug 25 12:06:52 PM UTC 24
Finished Aug 25 12:10:02 PM UTC 24
Peak memory 263300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596663331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.596663331
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_alerts.1076687734
Short name T538
Test name
Test status
Simulation time 362622035 ps
CPU time 37.09 seconds
Started Aug 25 12:06:13 PM UTC 24
Finished Aug 25 12:06:51 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076687734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1076687734
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/36.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/36.alert_handler_sig_int_fail.1543975782
Short name T541
Test name
Test status
Simulation time 574961935 ps
CPU time 24.23 seconds
Started Aug 25 12:06:50 PM UTC 24
Finished Aug 25 12:07:15 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543975782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1543975782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/36.alert_handler_smoke.3477329234
Short name T536
Test name
Test status
Simulation time 264106577 ps
CPU time 17.67 seconds
Started Aug 25 12:06:13 PM UTC 24
Finished Aug 25 12:06:31 PM UTC 24
Peak memory 269128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477329234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3477329234
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/36.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all.1187949392
Short name T591
Test name
Test status
Simulation time 7280747109 ps
CPU time 608.8 seconds
Started Aug 25 12:07:14 PM UTC 24
Finished Aug 25 12:17:31 PM UTC 24
Peak memory 269504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187949392 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all.1187949392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/36.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all_with_rand_reset.2411239371
Short name T576
Test name
Test status
Simulation time 15960565142 ps
CPU time 476.25 seconds
Started Aug 25 12:07:16 PM UTC 24
Finished Aug 25 12:15:20 PM UTC 24
Peak memory 281852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2411239371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.a
lert_handler_stress_all_with_rand_reset.2411239371
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/37.alert_handler_entropy.1086525161
Short name T677
Test name
Test status
Simulation time 28769406899 ps
CPU time 2732.17 seconds
Started Aug 25 12:09:26 PM UTC 24
Finished Aug 25 12:55:33 PM UTC 24
Peak memory 297864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086525161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1086525161
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/37.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_alert_accum.1353246009
Short name T560
Test name
Test status
Simulation time 7173283336 ps
CPU time 243.17 seconds
Started Aug 25 12:08:56 PM UTC 24
Finished Aug 25 12:13:04 PM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353246009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1353246009
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/37.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_intr_timeout.3347602310
Short name T549
Test name
Test status
Simulation time 1624472590 ps
CPU time 75.04 seconds
Started Aug 25 12:08:44 PM UTC 24
Finished Aug 25 12:10:01 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347602310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3347602310
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg.2081121435
Short name T380
Test name
Test status
Simulation time 79535212470 ps
CPU time 2435.88 seconds
Started Aug 25 12:09:28 PM UTC 24
Finished Aug 25 12:50:38 PM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081121435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2081121435
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/37.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg_stub_clk.1834614814
Short name T686
Test name
Test status
Simulation time 123764202618 ps
CPU time 3097.79 seconds
Started Aug 25 12:09:38 PM UTC 24
Finished Aug 25 01:01:57 PM UTC 24
Peak memory 304688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834614814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1834614814
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/37.alert_handler_ping_timeout.1420814866
Short name T564
Test name
Test status
Simulation time 23263545019 ps
CPU time 282.61 seconds
Started Aug 25 12:09:26 PM UTC 24
Finished Aug 25 12:14:13 PM UTC 24
Peak memory 267148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420814866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1420814866
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_alerts.2511836392
Short name T543
Test name
Test status
Simulation time 199796571 ps
CPU time 12.67 seconds
Started Aug 25 12:08:29 PM UTC 24
Finished Aug 25 12:08:43 PM UTC 24
Peak memory 267000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511836392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2511836392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/37.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_classes.3309062345
Short name T547
Test name
Test status
Simulation time 1399607647 ps
CPU time 47.42 seconds
Started Aug 25 12:08:38 PM UTC 24
Finished Aug 25 12:09:27 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309062345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3309062345
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/37.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/37.alert_handler_sig_int_fail.2662896002
Short name T548
Test name
Test status
Simulation time 271981772 ps
CPU time 47.52 seconds
Started Aug 25 12:09:05 PM UTC 24
Finished Aug 25 12:09:54 PM UTC 24
Peak memory 269344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662896002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2662896002
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/37.alert_handler_smoke.3916368363
Short name T544
Test name
Test status
Simulation time 925831128 ps
CPU time 42.63 seconds
Started Aug 25 12:08:11 PM UTC 24
Finished Aug 25 12:08:56 PM UTC 24
Peak memory 269128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916368363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3916368363
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/37.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all.1128510302
Short name T597
Test name
Test status
Simulation time 20103177349 ps
CPU time 490.47 seconds
Started Aug 25 12:09:56 PM UTC 24
Finished Aug 25 12:18:14 PM UTC 24
Peak memory 267064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128510302 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all.1128510302
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/37.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_alert_accum.223802126
Short name T565
Test name
Test status
Simulation time 6219108623 ps
CPU time 189.97 seconds
Started Aug 25 12:11:11 PM UTC 24
Finished Aug 25 12:14:25 PM UTC 24
Peak memory 269212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223802126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.223802126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/38.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_intr_timeout.1687541125
Short name T555
Test name
Test status
Simulation time 523279741 ps
CPU time 50.27 seconds
Started Aug 25 12:10:59 PM UTC 24
Finished Aug 25 12:11:51 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687541125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1687541125
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg.1507270782
Short name T389
Test name
Test status
Simulation time 113835076526 ps
CPU time 2558.13 seconds
Started Aug 25 12:11:35 PM UTC 24
Finished Aug 25 12:54:48 PM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507270782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1507270782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/38.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg_stub_clk.2785896859
Short name T662
Test name
Test status
Simulation time 24226168072 ps
CPU time 1559.54 seconds
Started Aug 25 12:11:40 PM UTC 24
Finished Aug 25 12:37:59 PM UTC 24
Peak memory 302220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785896859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2785896859
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/38.alert_handler_ping_timeout.3059383234
Short name T610
Test name
Test status
Simulation time 92627471521 ps
CPU time 577 seconds
Started Aug 25 12:11:26 PM UTC 24
Finished Aug 25 12:21:11 PM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059383234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3059383234
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_alerts.2446205946
Short name T553
Test name
Test status
Simulation time 704203066 ps
CPU time 61.59 seconds
Started Aug 25 12:10:09 PM UTC 24
Finished Aug 25 12:11:13 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446205946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2446205946
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/38.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_classes.3366595567
Short name T554
Test name
Test status
Simulation time 1988396624 ps
CPU time 53.73 seconds
Started Aug 25 12:10:52 PM UTC 24
Finished Aug 25 12:11:48 PM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366595567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3366595567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/38.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/38.alert_handler_sig_int_fail.417743767
Short name T150
Test name
Test status
Simulation time 2533775113 ps
CPU time 73.58 seconds
Started Aug 25 12:11:14 PM UTC 24
Finished Aug 25 12:12:30 PM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417743767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.417743767
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/38.alert_handler_smoke.3365297245
Short name T551
Test name
Test status
Simulation time 315972279 ps
CPU time 45.92 seconds
Started Aug 25 12:10:03 PM UTC 24
Finished Aug 25 12:10:51 PM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365297245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3365297245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/38.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all.4185881454
Short name T319
Test name
Test status
Simulation time 66282688594 ps
CPU time 1226.96 seconds
Started Aug 25 12:11:41 PM UTC 24
Finished Aug 25 12:32:25 PM UTC 24
Peak memory 279424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185881454 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all.4185881454
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/38.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all_with_rand_reset.3720357453
Short name T278
Test name
Test status
Simulation time 3514957460 ps
CPU time 566.28 seconds
Started Aug 25 12:11:49 PM UTC 24
Finished Aug 25 12:21:23 PM UTC 24
Peak memory 281920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3720357453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.a
lert_handler_stress_all_with_rand_reset.3720357453
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/39.alert_handler_entropy.3124391418
Short name T683
Test name
Test status
Simulation time 63646246658 ps
CPU time 2835.01 seconds
Started Aug 25 12:12:31 PM UTC 24
Finished Aug 25 01:00:24 PM UTC 24
Peak memory 302276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124391418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3124391418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/39.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_alert_accum.4209311770
Short name T569
Test name
Test status
Simulation time 2052925074 ps
CPU time 144.77 seconds
Started Aug 25 12:12:07 PM UTC 24
Finished Aug 25 12:14:34 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209311770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.4209311770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/39.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_intr_timeout.4052276701
Short name T563
Test name
Test status
Simulation time 12712264103 ps
CPU time 86.61 seconds
Started Aug 25 12:12:02 PM UTC 24
Finished Aug 25 12:13:31 PM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052276701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.4052276701
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg.4235840548
Short name T652
Test name
Test status
Simulation time 29845090061 ps
CPU time 1109.06 seconds
Started Aug 25 12:13:05 PM UTC 24
Finished Aug 25 12:31:49 PM UTC 24
Peak memory 285828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235840548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.4235840548
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/39.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg_stub_clk.3961928551
Short name T641
Test name
Test status
Simulation time 20705907378 ps
CPU time 999.11 seconds
Started Aug 25 12:13:10 PM UTC 24
Finished Aug 25 12:30:03 PM UTC 24
Peak memory 285584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961928551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3961928551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/39.alert_handler_ping_timeout.1238304085
Short name T582
Test name
Test status
Simulation time 12164088343 ps
CPU time 181.98 seconds
Started Aug 25 12:12:47 PM UTC 24
Finished Aug 25 12:15:53 PM UTC 24
Peak memory 267076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238304085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1238304085
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_alerts.2485926379
Short name T558
Test name
Test status
Simulation time 36646288 ps
CPU time 6.9 seconds
Started Aug 25 12:11:58 PM UTC 24
Finished Aug 25 12:12:06 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485926379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2485926379
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/39.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_classes.3015178210
Short name T559
Test name
Test status
Simulation time 1958779327 ps
CPU time 43.46 seconds
Started Aug 25 12:12:01 PM UTC 24
Finished Aug 25 12:12:46 PM UTC 24
Peak memory 269184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015178210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3015178210
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/39.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/39.alert_handler_sig_int_fail.3038506727
Short name T562
Test name
Test status
Simulation time 1346991855 ps
CPU time 65.44 seconds
Started Aug 25 12:12:22 PM UTC 24
Finished Aug 25 12:13:29 PM UTC 24
Peak memory 269060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038506727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3038506727
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/39.alert_handler_smoke.2828688520
Short name T557
Test name
Test status
Simulation time 206428096 ps
CPU time 6.88 seconds
Started Aug 25 12:11:52 PM UTC 24
Finished Aug 25 12:12:00 PM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828688520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2828688520
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/39.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all.386333027
Short name T566
Test name
Test status
Simulation time 709516145 ps
CPU time 57.35 seconds
Started Aug 25 12:13:26 PM UTC 24
Finished Aug 25 12:14:25 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386333027 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all.386333027
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/39.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all_with_rand_reset.2531932447
Short name T127
Test name
Test status
Simulation time 11892030840 ps
CPU time 304.83 seconds
Started Aug 25 12:13:30 PM UTC 24
Finished Aug 25 12:18:40 PM UTC 24
Peak memory 279552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2531932447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.a
lert_handler_stress_all_with_rand_reset.2531932447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/4.alert_handler_alert_accum_saturation.441516963
Short name T108
Test name
Test status
Simulation time 34696142 ps
CPU time 4.78 seconds
Started Aug 25 11:13:27 AM UTC 24
Finished Aug 25 11:13:33 AM UTC 24
Peak memory 263504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441516963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.441516963
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy_stress.3866695936
Short name T22
Test name
Test status
Simulation time 1458793794 ps
CPU time 56.13 seconds
Started Aug 25 11:13:20 AM UTC 24
Finished Aug 25 11:14:18 AM UTC 24
Peak memory 263172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866695936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3866695936
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_alert_accum.2391026494
Short name T131
Test name
Test status
Simulation time 902336799 ps
CPU time 69.13 seconds
Started Aug 25 11:13:06 AM UTC 24
Finished Aug 25 11:14:17 AM UTC 24
Peak memory 269076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391026494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2391026494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_intr_timeout.2071557400
Short name T77
Test name
Test status
Simulation time 365856377 ps
CPU time 6.54 seconds
Started Aug 25 11:13:03 AM UTC 24
Finished Aug 25 11:13:11 AM UTC 24
Peak memory 252992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071557400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2071557400
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg.2694314547
Short name T330
Test name
Test status
Simulation time 14433388483 ps
CPU time 1795.9 seconds
Started Aug 25 11:13:13 AM UTC 24
Finished Aug 25 11:43:34 AM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694314547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2694314547
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg_stub_clk.2959384484
Short name T492
Test name
Test status
Simulation time 51163073275 ps
CPU time 2495.9 seconds
Started Aug 25 11:13:19 AM UTC 24
Finished Aug 25 11:55:28 AM UTC 24
Peak memory 288224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959384484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2959384484
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/4.alert_handler_ping_timeout.2962226579
Short name T19
Test name
Test status
Simulation time 15573161894 ps
CPU time 232.31 seconds
Started Aug 25 11:13:11 AM UTC 24
Finished Aug 25 11:17:08 AM UTC 24
Peak memory 269448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962226579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2962226579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_alerts.1181702505
Short name T56
Test name
Test status
Simulation time 174993991 ps
CPU time 28.94 seconds
Started Aug 25 11:12:59 AM UTC 24
Finished Aug 25 11:13:29 AM UTC 24
Peak memory 269184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181702505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1181702505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/4.alert_handler_sec_cm.1543350650
Short name T52
Test name
Test status
Simulation time 1095095721 ps
CPU time 70.49 seconds
Started Aug 25 11:13:34 AM UTC 24
Finished Aug 25 11:14:46 AM UTC 24
Peak memory 295348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543350650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1543350650
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/4.alert_handler_sig_int_fail.1752661456
Short name T60
Test name
Test status
Simulation time 13621666648 ps
CPU time 69.51 seconds
Started Aug 25 11:13:06 AM UTC 24
Finished Aug 25 11:14:17 AM UTC 24
Peak memory 263040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752661456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1752661456
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/4.alert_handler_smoke.3139324507
Short name T157
Test name
Test status
Simulation time 3308330370 ps
CPU time 73.9 seconds
Started Aug 25 11:12:59 AM UTC 24
Finished Aug 25 11:14:15 AM UTC 24
Peak memory 269188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139324507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3139324507
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all.2368799969
Short name T585
Test name
Test status
Simulation time 39883247247 ps
CPU time 3777.36 seconds
Started Aug 25 11:13:21 AM UTC 24
Finished Aug 25 12:17:08 PM UTC 24
Peak memory 304596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368799969 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all.2368799969
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/4.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/40.alert_handler_entropy.1175398256
Short name T676
Test name
Test status
Simulation time 56314412700 ps
CPU time 2386.47 seconds
Started Aug 25 12:14:26 PM UTC 24
Finished Aug 25 12:54:43 PM UTC 24
Peak memory 285832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175398256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1175398256
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/40.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_alert_accum.2345865970
Short name T584
Test name
Test status
Simulation time 4870197326 ps
CPU time 148.77 seconds
Started Aug 25 12:14:17 PM UTC 24
Finished Aug 25 12:16:48 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345865970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2345865970
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/40.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_intr_timeout.1979287190
Short name T570
Test name
Test status
Simulation time 173150723 ps
CPU time 31.75 seconds
Started Aug 25 12:14:14 PM UTC 24
Finished Aug 25 12:14:47 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979287190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1979287190
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg.386277544
Short name T670
Test name
Test status
Simulation time 15078285898 ps
CPU time 1701.19 seconds
Started Aug 25 12:14:35 PM UTC 24
Finished Aug 25 12:43:18 PM UTC 24
Peak memory 285488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386277544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.386277544
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/40.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg_stub_clk.2613622362
Short name T693
Test name
Test status
Simulation time 33288838635 ps
CPU time 3535.81 seconds
Started Aug 25 12:14:35 PM UTC 24
Finished Aug 25 01:14:18 PM UTC 24
Peak memory 304692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613622362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2613622362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/40.alert_handler_ping_timeout.2049261306
Short name T623
Test name
Test status
Simulation time 68534764015 ps
CPU time 720.71 seconds
Started Aug 25 12:14:26 PM UTC 24
Finished Aug 25 12:26:36 PM UTC 24
Peak memory 269200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049261306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2049261306
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_alerts.2285432131
Short name T568
Test name
Test status
Simulation time 840731728 ps
CPU time 49.88 seconds
Started Aug 25 12:13:42 PM UTC 24
Finished Aug 25 12:14:34 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285432131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2285432131
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/40.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_classes.588544550
Short name T567
Test name
Test status
Simulation time 79028933 ps
CPU time 14.35 seconds
Started Aug 25 12:14:10 PM UTC 24
Finished Aug 25 12:14:26 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588544550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.588544550
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/40.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/40.alert_handler_sig_int_fail.2347346168
Short name T572
Test name
Test status
Simulation time 278769174 ps
CPU time 24.15 seconds
Started Aug 25 12:14:26 PM UTC 24
Finished Aug 25 12:14:52 PM UTC 24
Peak memory 269080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347346168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2347346168
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/40.alert_handler_smoke.3966998401
Short name T575
Test name
Test status
Simulation time 1118956020 ps
CPU time 96.39 seconds
Started Aug 25 12:13:32 PM UTC 24
Finished Aug 25 12:15:11 PM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966998401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3966998401
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/40.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all_with_rand_reset.3226246824
Short name T288
Test name
Test status
Simulation time 4448664584 ps
CPU time 777.74 seconds
Started Aug 25 12:14:36 PM UTC 24
Finished Aug 25 12:27:44 PM UTC 24
Peak memory 283776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3226246824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.a
lert_handler_stress_all_with_rand_reset.3226246824
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_alert_accum.4182341535
Short name T588
Test name
Test status
Simulation time 6733733815 ps
CPU time 146.02 seconds
Started Aug 25 12:14:58 PM UTC 24
Finished Aug 25 12:17:27 PM UTC 24
Peak memory 269248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182341535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.4182341535
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/41.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_intr_timeout.1657081845
Short name T577
Test name
Test status
Simulation time 1819160951 ps
CPU time 36.2 seconds
Started Aug 25 12:14:55 PM UTC 24
Finished Aug 25 12:15:32 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657081845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1657081845
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg.55659280
Short name T394
Test name
Test status
Simulation time 33784013269 ps
CPU time 2372.27 seconds
Started Aug 25 12:15:34 PM UTC 24
Finished Aug 25 12:55:39 PM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55659280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.55659280
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/41.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg_stub_clk.2324469892
Short name T689
Test name
Test status
Simulation time 124762016199 ps
CPU time 3037.96 seconds
Started Aug 25 12:15:39 PM UTC 24
Finished Aug 25 01:06:58 PM UTC 24
Peak memory 285584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324469892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2324469892
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/41.alert_handler_ping_timeout.3982227262
Short name T367
Test name
Test status
Simulation time 25951208947 ps
CPU time 705.72 seconds
Started Aug 25 12:15:34 PM UTC 24
Finished Aug 25 12:27:31 PM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982227262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3982227262
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_alerts.4061568556
Short name T581
Test name
Test status
Simulation time 2210496209 ps
CPU time 53.54 seconds
Started Aug 25 12:14:52 PM UTC 24
Finished Aug 25 12:15:48 PM UTC 24
Peak memory 269184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061568556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.4061568556
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/41.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_classes.548242488
Short name T579
Test name
Test status
Simulation time 311665644 ps
CPU time 44.84 seconds
Started Aug 25 12:14:52 PM UTC 24
Finished Aug 25 12:15:39 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548242488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.548242488
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/41.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/41.alert_handler_sig_int_fail.4057697102
Short name T580
Test name
Test status
Simulation time 319658079 ps
CPU time 29.8 seconds
Started Aug 25 12:15:12 PM UTC 24
Finished Aug 25 12:15:43 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057697102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.4057697102
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/41.alert_handler_smoke.68846268
Short name T578
Test name
Test status
Simulation time 430173287 ps
CPU time 48.8 seconds
Started Aug 25 12:14:48 PM UTC 24
Finished Aug 25 12:15:38 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68846268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smo
ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.68846268
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/41.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all_with_rand_reset.2198312662
Short name T608
Test name
Test status
Simulation time 6726606449 ps
CPU time 298.69 seconds
Started Aug 25 12:15:44 PM UTC 24
Finished Aug 25 12:20:48 PM UTC 24
Peak memory 279480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2198312662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.a
lert_handler_stress_all_with_rand_reset.2198312662
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/42.alert_handler_entropy.1876119200
Short name T679
Test name
Test status
Simulation time 57372576181 ps
CPU time 2406.87 seconds
Started Aug 25 12:16:51 PM UTC 24
Finished Aug 25 12:57:31 PM UTC 24
Peak memory 301960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876119200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1876119200
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/42.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_alert_accum.2639469511
Short name T598
Test name
Test status
Simulation time 1084528262 ps
CPU time 95.78 seconds
Started Aug 25 12:16:37 PM UTC 24
Finished Aug 25 12:18:15 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639469511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2639469511
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/42.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_intr_timeout.1687264522
Short name T590
Test name
Test status
Simulation time 549136493 ps
CPU time 52.87 seconds
Started Aug 25 12:16:36 PM UTC 24
Finished Aug 25 12:17:31 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687264522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1687264522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg_stub_clk.784695730
Short name T671
Test name
Test status
Simulation time 19371200989 ps
CPU time 1936.34 seconds
Started Aug 25 12:17:23 PM UTC 24
Finished Aug 25 12:50:05 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784695730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.784695730
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/42.alert_handler_ping_timeout.2779487161
Short name T602
Test name
Test status
Simulation time 11116386542 ps
CPU time 153.86 seconds
Started Aug 25 12:17:11 PM UTC 24
Finished Aug 25 12:19:47 PM UTC 24
Peak memory 269124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779487161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2779487161
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_alerts.591473483
Short name T587
Test name
Test status
Simulation time 2136788777 ps
CPU time 86.66 seconds
Started Aug 25 12:15:53 PM UTC 24
Finished Aug 25 12:17:22 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591473483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.591473483
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/42.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_classes.3845870484
Short name T592
Test name
Test status
Simulation time 2779280905 ps
CPU time 83.18 seconds
Started Aug 25 12:16:07 PM UTC 24
Finished Aug 25 12:17:33 PM UTC 24
Peak memory 269504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845870484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3845870484
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/42.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/42.alert_handler_sig_int_fail.3420997232
Short name T589
Test name
Test status
Simulation time 349256542 ps
CPU time 36.02 seconds
Started Aug 25 12:16:51 PM UTC 24
Finished Aug 25 12:17:29 PM UTC 24
Peak memory 269080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420997232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3420997232
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/42.alert_handler_smoke.3447819998
Short name T583
Test name
Test status
Simulation time 1341430302 ps
CPU time 44.74 seconds
Started Aug 25 12:15:49 PM UTC 24
Finished Aug 25 12:16:36 PM UTC 24
Peak memory 269128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447819998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3447819998
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/42.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all.1669920619
Short name T310
Test name
Test status
Simulation time 44577218172 ps
CPU time 3899.28 seconds
Started Aug 25 12:17:27 PM UTC 24
Finished Aug 25 01:23:19 PM UTC 24
Peak memory 304676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669920619 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all.1669920619
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/42.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/43.alert_handler_entropy.1497821498
Short name T695
Test name
Test status
Simulation time 38940745150 ps
CPU time 3490.12 seconds
Started Aug 25 12:18:13 PM UTC 24
Finished Aug 25 01:17:10 PM UTC 24
Peak memory 288224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497821498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1497821498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/43.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_alert_accum.4293485479
Short name T607
Test name
Test status
Simulation time 3391261093 ps
CPU time 160.64 seconds
Started Aug 25 12:18:00 PM UTC 24
Finished Aug 25 12:20:44 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293485479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.4293485479
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/43.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_intr_timeout.1872457824
Short name T595
Test name
Test status
Simulation time 828856763 ps
CPU time 24.74 seconds
Started Aug 25 12:17:44 PM UTC 24
Finished Aug 25 12:18:10 PM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872457824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1872457824
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg_stub_clk.1251237217
Short name T680
Test name
Test status
Simulation time 60125651275 ps
CPU time 2342.08 seconds
Started Aug 25 12:18:24 PM UTC 24
Finished Aug 25 12:58:00 PM UTC 24
Peak memory 301896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251237217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1251237217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/43.alert_handler_ping_timeout.2639487753
Short name T654
Test name
Test status
Simulation time 21856639422 ps
CPU time 845.63 seconds
Started Aug 25 12:18:15 PM UTC 24
Finished Aug 25 12:32:31 PM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639487753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2639487753
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_alerts.1945915613
Short name T594
Test name
Test status
Simulation time 469369511 ps
CPU time 25.7 seconds
Started Aug 25 12:17:32 PM UTC 24
Finished Aug 25 12:17:59 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945915613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1945915613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/43.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_classes.962888903
Short name T596
Test name
Test status
Simulation time 416052414 ps
CPU time 36.15 seconds
Started Aug 25 12:17:34 PM UTC 24
Finished Aug 25 12:18:12 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962888903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.962888903
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/43.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/43.alert_handler_sig_int_fail.294733628
Short name T600
Test name
Test status
Simulation time 328594408 ps
CPU time 37.1 seconds
Started Aug 25 12:18:11 PM UTC 24
Finished Aug 25 12:18:50 PM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294733628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.294733628
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/43.alert_handler_smoke.3747028827
Short name T593
Test name
Test status
Simulation time 46475573 ps
CPU time 9.94 seconds
Started Aug 25 12:17:32 PM UTC 24
Finished Aug 25 12:17:43 PM UTC 24
Peak memory 267008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747028827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3747028827
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/43.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all.619497539
Short name T692
Test name
Test status
Simulation time 41354665160 ps
CPU time 3285.13 seconds
Started Aug 25 12:18:41 PM UTC 24
Finished Aug 25 01:14:08 PM UTC 24
Peak memory 299824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619497539 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all.619497539
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/43.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/44.alert_handler_entropy.3644559248
Short name T673
Test name
Test status
Simulation time 11853660489 ps
CPU time 1834.29 seconds
Started Aug 25 12:20:25 PM UTC 24
Finished Aug 25 12:51:25 PM UTC 24
Peak memory 297788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644559248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3644559248
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/44.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_alert_accum.3444411434
Short name T612
Test name
Test status
Simulation time 3117573557 ps
CPU time 92.51 seconds
Started Aug 25 12:20:02 PM UTC 24
Finished Aug 25 12:21:37 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444411434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3444411434
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/44.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_intr_timeout.974698893
Short name T609
Test name
Test status
Simulation time 5465818939 ps
CPU time 62.83 seconds
Started Aug 25 12:19:48 PM UTC 24
Finished Aug 25 12:20:53 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974698893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.974698893
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg.1857294150
Short name T681
Test name
Test status
Simulation time 67224478733 ps
CPU time 2281.09 seconds
Started Aug 25 12:20:45 PM UTC 24
Finished Aug 25 12:59:16 PM UTC 24
Peak memory 302020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857294150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1857294150
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/44.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg_stub_clk.1987752182
Short name T684
Test name
Test status
Simulation time 46984236700 ps
CPU time 2383 seconds
Started Aug 25 12:20:49 PM UTC 24
Finished Aug 25 01:01:03 PM UTC 24
Peak memory 296080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987752182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1987752182
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/44.alert_handler_ping_timeout.1777290461
Short name T651
Test name
Test status
Simulation time 39833045136 ps
CPU time 652.22 seconds
Started Aug 25 12:20:31 PM UTC 24
Finished Aug 25 12:31:33 PM UTC 24
Peak memory 262984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777290461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1777290461
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_alerts.298412606
Short name T604
Test name
Test status
Simulation time 6168990923 ps
CPU time 57.26 seconds
Started Aug 25 12:19:04 PM UTC 24
Finished Aug 25 12:20:03 PM UTC 24
Peak memory 269216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298412606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.298412606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/44.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_classes.4243698145
Short name T603
Test name
Test status
Simulation time 946408327 ps
CPU time 22.15 seconds
Started Aug 25 12:19:38 PM UTC 24
Finished Aug 25 12:20:01 PM UTC 24
Peak memory 267328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243698145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.4243698145
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/44.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/44.alert_handler_sig_int_fail.4276137676
Short name T605
Test name
Test status
Simulation time 193308046 ps
CPU time 17.84 seconds
Started Aug 25 12:20:04 PM UTC 24
Finished Aug 25 12:20:23 PM UTC 24
Peak memory 269408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276137676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.4276137676
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/44.alert_handler_smoke.1787951299
Short name T601
Test name
Test status
Simulation time 483079034 ps
CPU time 37.23 seconds
Started Aug 25 12:18:59 PM UTC 24
Finished Aug 25 12:19:37 PM UTC 24
Peak memory 269384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787951299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1787951299
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/44.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all.4051515939
Short name T615
Test name
Test status
Simulation time 4882969719 ps
CPU time 105.1 seconds
Started Aug 25 12:20:54 PM UTC 24
Finished Aug 25 12:22:41 PM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051515939 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all.4051515939
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/44.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all_with_rand_reset.4184137891
Short name T643
Test name
Test status
Simulation time 11535805372 ps
CPU time 525.77 seconds
Started Aug 25 12:21:12 PM UTC 24
Finished Aug 25 12:30:06 PM UTC 24
Peak memory 281528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4184137891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.a
lert_handler_stress_all_with_rand_reset.4184137891
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/45.alert_handler_entropy.858956461
Short name T668
Test name
Test status
Simulation time 13198981286 ps
CPU time 1114.47 seconds
Started Aug 25 12:22:02 PM UTC 24
Finished Aug 25 12:40:53 PM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858956461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.858956461
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/45.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_alert_accum.357701839
Short name T626
Test name
Test status
Simulation time 13423811195 ps
CPU time 285.3 seconds
Started Aug 25 12:21:59 PM UTC 24
Finished Aug 25 12:26:49 PM UTC 24
Peak memory 269468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357701839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.357701839
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/45.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_intr_timeout.3615524593
Short name T614
Test name
Test status
Simulation time 1101072237 ps
CPU time 51.1 seconds
Started Aug 25 12:21:38 PM UTC 24
Finished Aug 25 12:22:31 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615524593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3615524593
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg.1365891943
Short name T690
Test name
Test status
Simulation time 42317216711 ps
CPU time 2688.59 seconds
Started Aug 25 12:22:31 PM UTC 24
Finished Aug 25 01:07:59 PM UTC 24
Peak memory 301884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365891943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1365891943
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/45.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg_stub_clk.7719946
Short name T658
Test name
Test status
Simulation time 60873989095 ps
CPU time 826.11 seconds
Started Aug 25 12:22:32 PM UTC 24
Finished Aug 25 12:36:30 PM UTC 24
Peak memory 285828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7719946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.7719946
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/45.alert_handler_ping_timeout.3035221566
Short name T657
Test name
Test status
Simulation time 50372205412 ps
CPU time 822.22 seconds
Started Aug 25 12:22:20 PM UTC 24
Finished Aug 25 12:36:13 PM UTC 24
Peak memory 269124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035221566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3035221566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_alerts.4006151393
Short name T611
Test name
Test status
Simulation time 45946185 ps
CPU time 8.65 seconds
Started Aug 25 12:21:25 PM UTC 24
Finished Aug 25 12:21:34 PM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006151393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.4006151393
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/45.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_classes.1592240131
Short name T118
Test name
Test status
Simulation time 2230510439 ps
CPU time 80.68 seconds
Started Aug 25 12:21:35 PM UTC 24
Finished Aug 25 12:22:58 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592240131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1592240131
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/45.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/45.alert_handler_sig_int_fail.3622358507
Short name T320
Test name
Test status
Simulation time 484131609 ps
CPU time 28.62 seconds
Started Aug 25 12:22:01 PM UTC 24
Finished Aug 25 12:22:32 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622358507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3622358507
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/45.alert_handler_smoke.3401582026
Short name T613
Test name
Test status
Simulation time 713498837 ps
CPU time 43.45 seconds
Started Aug 25 12:21:17 PM UTC 24
Finished Aug 25 12:22:02 PM UTC 24
Peak memory 269448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401582026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3401582026
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/45.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all.4196769791
Short name T281
Test name
Test status
Simulation time 3198971529 ps
CPU time 221.43 seconds
Started Aug 25 12:22:42 PM UTC 24
Finished Aug 25 12:26:27 PM UTC 24
Peak memory 267392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196769791 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all.4196769791
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/45.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_alert_accum.20000456
Short name T627
Test name
Test status
Simulation time 1261416870 ps
CPU time 142.74 seconds
Started Aug 25 12:24:26 PM UTC 24
Finished Aug 25 12:26:52 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20000456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc
_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.20000456
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/46.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_intr_timeout.1449111591
Short name T620
Test name
Test status
Simulation time 2465096749 ps
CPU time 116.04 seconds
Started Aug 25 12:23:50 PM UTC 24
Finished Aug 25 12:25:49 PM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449111591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1449111591
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg.2133722517
Short name T383
Test name
Test status
Simulation time 103339759779 ps
CPU time 2241.71 seconds
Started Aug 25 12:25:10 PM UTC 24
Finished Aug 25 01:02:58 PM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133722517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2133722517
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/46.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg_stub_clk.841308033
Short name T688
Test name
Test status
Simulation time 121464470456 ps
CPU time 2307.34 seconds
Started Aug 25 12:25:37 PM UTC 24
Finished Aug 25 01:04:37 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841308033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.841308033
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/46.alert_handler_ping_timeout.2838079572
Short name T663
Test name
Test status
Simulation time 221320827659 ps
CPU time 792.99 seconds
Started Aug 25 12:24:49 PM UTC 24
Finished Aug 25 12:38:14 PM UTC 24
Peak memory 262984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838079572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2838079572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_alerts.3850353405
Short name T619
Test name
Test status
Simulation time 761691765 ps
CPU time 61.78 seconds
Started Aug 25 12:23:33 PM UTC 24
Finished Aug 25 12:24:37 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850353405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3850353405
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/46.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_classes.272501182
Short name T617
Test name
Test status
Simulation time 344825818 ps
CPU time 12.47 seconds
Started Aug 25 12:23:35 PM UTC 24
Finished Aug 25 12:23:49 PM UTC 24
Peak memory 265024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272501182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.272501182
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/46.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/46.alert_handler_sig_int_fail.3091006410
Short name T293
Test name
Test status
Simulation time 827951994 ps
CPU time 88.79 seconds
Started Aug 25 12:24:29 PM UTC 24
Finished Aug 25 12:26:00 PM UTC 24
Peak memory 263072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091006410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3091006410
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/46.alert_handler_smoke.1378549594
Short name T616
Test name
Test status
Simulation time 1118534258 ps
CPU time 26.55 seconds
Started Aug 25 12:23:07 PM UTC 24
Finished Aug 25 12:23:35 PM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378549594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1378549594
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/46.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all.4110505777
Short name T701
Test name
Test status
Simulation time 59290546108 ps
CPU time 4254.23 seconds
Started Aug 25 12:25:49 PM UTC 24
Finished Aug 25 01:37:37 PM UTC 24
Peak memory 304676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110505777 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all.4110505777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/46.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all_with_rand_reset.3582136842
Short name T636
Test name
Test status
Simulation time 1649016370 ps
CPU time 161.62 seconds
Started Aug 25 12:25:50 PM UTC 24
Finished Aug 25 12:28:34 PM UTC 24
Peak memory 279416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3582136842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.a
lert_handler_stress_all_with_rand_reset.3582136842
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/47.alert_handler_entropy.3609441629
Short name T698
Test name
Test status
Simulation time 268990096399 ps
CPU time 3341.74 seconds
Started Aug 25 12:26:46 PM UTC 24
Finished Aug 25 01:23:09 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609441629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3609441629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/47.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_alert_accum.1547022547
Short name T625
Test name
Test status
Simulation time 29370161 ps
CPU time 5.37 seconds
Started Aug 25 12:26:38 PM UTC 24
Finished Aug 25 12:26:45 PM UTC 24
Peak memory 252660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547022547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1547022547
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/47.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_intr_timeout.1157744359
Short name T628
Test name
Test status
Simulation time 1504111108 ps
CPU time 36.31 seconds
Started Aug 25 12:26:28 PM UTC 24
Finished Aug 25 12:27:07 PM UTC 24
Peak memory 269052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157744359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1157744359
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg_stub_clk.3589290600
Short name T699
Test name
Test status
Simulation time 35131160425 ps
CPU time 3395.96 seconds
Started Aug 25 12:27:08 PM UTC 24
Finished Aug 25 01:24:28 PM UTC 24
Peak memory 304688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589290600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3589290600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/47.alert_handler_ping_timeout.3150530800
Short name T656
Test name
Test status
Simulation time 23798060812 ps
CPU time 400.38 seconds
Started Aug 25 12:26:50 PM UTC 24
Finished Aug 25 12:33:37 PM UTC 24
Peak memory 269132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150530800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3150530800
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_alerts.1187198748
Short name T624
Test name
Test status
Simulation time 324726906 ps
CPU time 21.9 seconds
Started Aug 25 12:26:16 PM UTC 24
Finished Aug 25 12:26:39 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187198748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1187198748
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/47.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_classes.3569428003
Short name T630
Test name
Test status
Simulation time 3369458232 ps
CPU time 78.82 seconds
Started Aug 25 12:26:21 PM UTC 24
Finished Aug 25 12:27:43 PM UTC 24
Peak memory 269184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569428003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3569428003
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/47.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/47.alert_handler_sig_int_fail.1858581333
Short name T629
Test name
Test status
Simulation time 1079652726 ps
CPU time 36.26 seconds
Started Aug 25 12:26:41 PM UTC 24
Finished Aug 25 12:27:19 PM UTC 24
Peak memory 262936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858581333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1858581333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/47.alert_handler_smoke.660686579
Short name T621
Test name
Test status
Simulation time 679424565 ps
CPU time 13.52 seconds
Started Aug 25 12:26:01 PM UTC 24
Finished Aug 25 12:26:16 PM UTC 24
Peak memory 265280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660686579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.660686579
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/47.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all.169369626
Short name T687
Test name
Test status
Simulation time 18970718444 ps
CPU time 2135.45 seconds
Started Aug 25 12:27:17 PM UTC 24
Finished Aug 25 01:03:20 PM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169369626 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all.169369626
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/47.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all_with_rand_reset.2906783584
Short name T655
Test name
Test status
Simulation time 2504547087 ps
CPU time 362.88 seconds
Started Aug 25 12:27:20 PM UTC 24
Finished Aug 25 12:33:29 PM UTC 24
Peak memory 279480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2906783584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.a
lert_handler_stress_all_with_rand_reset.2906783584
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/48.alert_handler_entropy.1305160697
Short name T696
Test name
Test status
Simulation time 56270204631 ps
CPU time 3094.97 seconds
Started Aug 25 12:28:04 PM UTC 24
Finished Aug 25 01:20:20 PM UTC 24
Peak memory 302212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305160697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1305160697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/48.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_alert_accum.894797151
Short name T650
Test name
Test status
Simulation time 8310570160 ps
CPU time 196.8 seconds
Started Aug 25 12:27:49 PM UTC 24
Finished Aug 25 12:31:09 PM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894797151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.894797151
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/48.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_intr_timeout.256566024
Short name T634
Test name
Test status
Simulation time 241334308 ps
CPU time 12.77 seconds
Started Aug 25 12:27:49 PM UTC 24
Finished Aug 25 12:28:03 PM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256566024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.256566024
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg.131800382
Short name T382
Test name
Test status
Simulation time 100420129063 ps
CPU time 1170.73 seconds
Started Aug 25 12:28:33 PM UTC 24
Finished Aug 25 12:48:20 PM UTC 24
Peak memory 285564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131800382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.131800382
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/48.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg_stub_clk.256381861
Short name T700
Test name
Test status
Simulation time 34534285811 ps
CPU time 3468.31 seconds
Started Aug 25 12:28:36 PM UTC 24
Finished Aug 25 01:27:10 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256381861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.256381861
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/48.alert_handler_ping_timeout.4237585285
Short name T661
Test name
Test status
Simulation time 10333718303 ps
CPU time 578.04 seconds
Started Aug 25 12:28:11 PM UTC 24
Finished Aug 25 12:37:58 PM UTC 24
Peak memory 263312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237585285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.4237585285
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_alerts.4089433367
Short name T635
Test name
Test status
Simulation time 209142013 ps
CPU time 25.31 seconds
Started Aug 25 12:27:43 PM UTC 24
Finished Aug 25 12:28:10 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089433367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.4089433367
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/48.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_classes.1293065043
Short name T633
Test name
Test status
Simulation time 392286127 ps
CPU time 12.88 seconds
Started Aug 25 12:27:46 PM UTC 24
Finished Aug 25 12:28:00 PM UTC 24
Peak memory 269076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293065043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1293065043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/48.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/48.alert_handler_sig_int_fail.3550133985
Short name T637
Test name
Test status
Simulation time 206083832 ps
CPU time 35.65 seconds
Started Aug 25 12:28:01 PM UTC 24
Finished Aug 25 12:28:38 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550133985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3550133985
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/48.alert_handler_smoke.4180634723
Short name T632
Test name
Test status
Simulation time 128014590 ps
CPU time 15.58 seconds
Started Aug 25 12:27:31 PM UTC 24
Finished Aug 25 12:27:48 PM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180634723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.4180634723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/48.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all.2582231869
Short name T666
Test name
Test status
Simulation time 9905718487 ps
CPU time 695.77 seconds
Started Aug 25 12:28:39 PM UTC 24
Finished Aug 25 12:40:24 PM UTC 24
Peak memory 279424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582231869 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all.2582231869
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/48.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/49.alert_handler_entropy.589773062
Short name T697
Test name
Test status
Simulation time 33164073888 ps
CPU time 3046.3 seconds
Started Aug 25 12:30:19 PM UTC 24
Finished Aug 25 01:21:48 PM UTC 24
Peak memory 285832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589773062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.589773062
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/49.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_alert_accum.1283033436
Short name T647
Test name
Test status
Simulation time 506846766 ps
CPU time 51 seconds
Started Aug 25 12:30:07 PM UTC 24
Finished Aug 25 12:31:00 PM UTC 24
Peak memory 269144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283033436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1283033436
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/49.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_intr_timeout.3757219014
Short name T649
Test name
Test status
Simulation time 1359619027 ps
CPU time 59.66 seconds
Started Aug 25 12:30:04 PM UTC 24
Finished Aug 25 12:31:06 PM UTC 24
Peak memory 263100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757219014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3757219014
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg.1861740038
Short name T395
Test name
Test status
Simulation time 16145954814 ps
CPU time 1509.51 seconds
Started Aug 25 12:30:54 PM UTC 24
Finished Aug 25 12:56:24 PM UTC 24
Peak memory 285832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861740038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1861740038
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/49.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/49.alert_handler_ping_timeout.4060119191
Short name T660
Test name
Test status
Simulation time 24687354239 ps
CPU time 421.76 seconds
Started Aug 25 12:30:37 PM UTC 24
Finished Aug 25 12:37:45 PM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060119191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.4060119191
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_alerts.1362766461
Short name T648
Test name
Test status
Simulation time 13063081188 ps
CPU time 79.36 seconds
Started Aug 25 12:29:43 PM UTC 24
Finished Aug 25 12:31:04 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362766461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1362766461
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/49.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_classes.200907035
Short name T646
Test name
Test status
Simulation time 4608445029 ps
CPU time 67.69 seconds
Started Aug 25 12:29:43 PM UTC 24
Finished Aug 25 12:30:52 PM UTC 24
Peak memory 263040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200907035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.200907035
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/49.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/49.alert_handler_sig_int_fail.1042940595
Short name T645
Test name
Test status
Simulation time 977783970 ps
CPU time 28.15 seconds
Started Aug 25 12:30:07 PM UTC 24
Finished Aug 25 12:30:37 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042940595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1042940595
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/49.alert_handler_smoke.3533482721
Short name T640
Test name
Test status
Simulation time 79149815 ps
CPU time 15.05 seconds
Started Aug 25 12:29:25 PM UTC 24
Finished Aug 25 12:29:42 PM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533482721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3533482721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/49.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all.3383533215
Short name T137
Test name
Test status
Simulation time 4941611292 ps
CPU time 202.41 seconds
Started Aug 25 12:31:05 PM UTC 24
Finished Aug 25 12:34:31 PM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383533215 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all.3383533215
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/49.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all_with_rand_reset.3635968808
Short name T138
Test name
Test status
Simulation time 2250269535 ps
CPU time 393.92 seconds
Started Aug 25 12:31:07 PM UTC 24
Finished Aug 25 12:37:48 PM UTC 24
Peak memory 286016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3635968808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.a
lert_handler_stress_all_with_rand_reset.3635968808
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/5.alert_handler_alert_accum_saturation.3725259709
Short name T246
Test name
Test status
Simulation time 140770320 ps
CPU time 5.02 seconds
Started Aug 25 11:14:17 AM UTC 24
Finished Aug 25 11:14:23 AM UTC 24
Peak memory 263500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725259709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3725259709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy.4102579076
Short name T315
Test name
Test status
Simulation time 121907920153 ps
CPU time 2508.47 seconds
Started Aug 25 11:13:51 AM UTC 24
Finished Aug 25 11:56:13 AM UTC 24
Peak memory 287768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102579076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.4102579076
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy_stress.999832017
Short name T23
Test name
Test status
Simulation time 151135504 ps
CPU time 14.02 seconds
Started Aug 25 11:14:15 AM UTC 24
Finished Aug 25 11:14:31 AM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999832017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.999832017
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_intr_timeout.3021890076
Short name T95
Test name
Test status
Simulation time 12349172938 ps
CPU time 92.19 seconds
Started Aug 25 11:13:39 AM UTC 24
Finished Aug 25 11:15:13 AM UTC 24
Peak memory 269216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021890076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3021890076
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg.2963438572
Short name T323
Test name
Test status
Simulation time 17781556888 ps
CPU time 1461.38 seconds
Started Aug 25 11:14:02 AM UTC 24
Finished Aug 25 11:38:43 AM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963438572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2963438572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg_stub_clk.47737897
Short name T335
Test name
Test status
Simulation time 82035597823 ps
CPU time 1554.32 seconds
Started Aug 25 11:14:09 AM UTC 24
Finished Aug 25 11:40:26 AM UTC 24
Peak memory 285828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47737897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.47737897
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_alerts.415140113
Short name T92
Test name
Test status
Simulation time 1026667312 ps
CPU time 30.33 seconds
Started Aug 25 11:13:37 AM UTC 24
Finished Aug 25 11:14:08 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415140113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.415140113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_classes.677869504
Short name T57
Test name
Test status
Simulation time 89051592 ps
CPU time 13.15 seconds
Started Aug 25 11:13:37 AM UTC 24
Finished Aug 25 11:13:51 AM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677869504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.677869504
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/5.alert_handler_smoke.3240062887
Short name T156
Test name
Test status
Simulation time 3780975499 ps
CPU time 35.93 seconds
Started Aug 25 11:13:37 AM UTC 24
Finished Aug 25 11:14:14 AM UTC 24
Peak memory 269444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240062887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3240062887
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all.599320738
Short name T644
Test name
Test status
Simulation time 56715638520 ps
CPU time 4502.75 seconds
Started Aug 25 11:14:15 AM UTC 24
Finished Aug 25 12:30:17 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599320738 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all.599320738
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all_with_rand_reset.1044260106
Short name T49
Test name
Test status
Simulation time 1517022837 ps
CPU time 263.46 seconds
Started Aug 25 11:14:19 AM UTC 24
Finished Aug 25 11:18:47 AM UTC 24
Peak memory 283516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1044260106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.al
ert_handler_stress_all_with_rand_reset.1044260106
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/6.alert_handler_alert_accum_saturation.2811741979
Short name T247
Test name
Test status
Simulation time 328181706 ps
CPU time 5.85 seconds
Started Aug 25 11:14:47 AM UTC 24
Finished Aug 25 11:14:54 AM UTC 24
Peak memory 263244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811741979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2811741979
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy.3567588618
Short name T336
Test name
Test status
Simulation time 33495461739 ps
CPU time 1609.18 seconds
Started Aug 25 11:14:30 AM UTC 24
Finished Aug 25 11:41:42 AM UTC 24
Peak memory 279432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567588618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3567588618
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy_stress.55616628
Short name T25
Test name
Test status
Simulation time 1512994347 ps
CPU time 86.34 seconds
Started Aug 25 11:14:38 AM UTC 24
Finished Aug 25 11:16:07 AM UTC 24
Peak memory 262896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55616628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_h
andler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.55616628
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_alert_accum.1870394333
Short name T226
Test name
Test status
Simulation time 6315188387 ps
CPU time 279.78 seconds
Started Aug 25 11:14:25 AM UTC 24
Finished Aug 25 11:19:10 AM UTC 24
Peak memory 269212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870394333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1870394333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_intr_timeout.3350632882
Short name T93
Test name
Test status
Simulation time 373630014 ps
CPU time 35.12 seconds
Started Aug 25 11:14:24 AM UTC 24
Finished Aug 25 11:15:00 AM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350632882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3350632882
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_alerts.3215604666
Short name T87
Test name
Test status
Simulation time 3324747201 ps
CPU time 55.52 seconds
Started Aug 25 11:14:19 AM UTC 24
Finished Aug 25 11:15:16 AM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215604666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3215604666
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_classes.2199409871
Short name T62
Test name
Test status
Simulation time 137856859 ps
CPU time 16.66 seconds
Started Aug 25 11:14:19 AM UTC 24
Finished Aug 25 11:14:37 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199409871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2199409871
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/6.alert_handler_smoke.2697267754
Short name T86
Test name
Test status
Simulation time 343210365 ps
CPU time 45.88 seconds
Started Aug 25 11:14:19 AM UTC 24
Finished Aug 25 11:15:06 AM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697267754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2697267754
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all_with_rand_reset.1078869152
Short name T119
Test name
Test status
Simulation time 11101101736 ps
CPU time 720.44 seconds
Started Aug 25 11:14:47 AM UTC 24
Finished Aug 25 11:26:58 AM UTC 24
Peak memory 283644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1078869152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.al
ert_handler_stress_all_with_rand_reset.1078869152
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/7.alert_handler_alert_accum_saturation.3223348038
Short name T162
Test name
Test status
Simulation time 387795566 ps
CPU time 7.04 seconds
Started Aug 25 11:15:40 AM UTC 24
Finished Aug 25 11:15:48 AM UTC 24
Peak memory 263172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223348038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3223348038
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy.711724146
Short name T135
Test name
Test status
Simulation time 114972755278 ps
CPU time 2559.54 seconds
Started Aug 25 11:15:03 AM UTC 24
Finished Aug 25 11:58:18 AM UTC 24
Peak memory 288300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711724146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.711724146
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy_stress.3907356555
Short name T24
Test name
Test status
Simulation time 459575844 ps
CPU time 27.31 seconds
Started Aug 25 11:15:15 AM UTC 24
Finished Aug 25 11:15:44 AM UTC 24
Peak memory 263300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907356555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3907356555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_alert_accum.1261099415
Short name T244
Test name
Test status
Simulation time 2048147014 ps
CPU time 151.58 seconds
Started Aug 25 11:15:02 AM UTC 24
Finished Aug 25 11:17:36 AM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261099415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1261099415
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_intr_timeout.4213564316
Short name T96
Test name
Test status
Simulation time 3697597534 ps
CPU time 79.32 seconds
Started Aug 25 11:15:01 AM UTC 24
Finished Aug 25 11:16:22 AM UTC 24
Peak memory 263072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213564316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.4213564316
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg.1040399723
Short name T375
Test name
Test status
Simulation time 25590347524 ps
CPU time 2321.57 seconds
Started Aug 25 11:15:09 AM UTC 24
Finished Aug 25 11:54:24 AM UTC 24
Peak memory 285760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040399723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1040399723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg_stub_clk.847727536
Short name T306
Test name
Test status
Simulation time 17002961111 ps
CPU time 1574.66 seconds
Started Aug 25 11:15:15 AM UTC 24
Finished Aug 25 11:41:50 AM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847727536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.847727536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/7.alert_handler_ping_timeout.2406669249
Short name T20
Test name
Test status
Simulation time 11889353443 ps
CPU time 133.33 seconds
Started Aug 25 11:15:07 AM UTC 24
Finished Aug 25 11:17:23 AM UTC 24
Peak memory 263240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406669249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2406669249
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_alerts.484635489
Short name T161
Test name
Test status
Simulation time 636177134 ps
CPU time 43.75 seconds
Started Aug 25 11:14:54 AM UTC 24
Finished Aug 25 11:15:40 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484635489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.484635489
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_classes.3874778028
Short name T88
Test name
Test status
Simulation time 3193359697 ps
CPU time 79.43 seconds
Started Aug 25 11:14:55 AM UTC 24
Finished Aug 25 11:16:16 AM UTC 24
Peak memory 263360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874778028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3874778028
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/7.alert_handler_sig_int_fail.4010119822
Short name T121
Test name
Test status
Simulation time 2145908743 ps
CPU time 44.38 seconds
Started Aug 25 11:15:02 AM UTC 24
Finished Aug 25 11:15:48 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010119822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.4010119822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/7.alert_handler_smoke.3862996605
Short name T94
Test name
Test status
Simulation time 783399433 ps
CPU time 14.21 seconds
Started Aug 25 11:14:53 AM UTC 24
Finished Aug 25 11:15:09 AM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862996605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3862996605
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all.437247762
Short name T284
Test name
Test status
Simulation time 52950955448 ps
CPU time 2534.1 seconds
Started Aug 25 11:15:17 AM UTC 24
Finished Aug 25 11:58:05 AM UTC 24
Peak memory 288220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437247762 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all.437247762
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/7.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/8.alert_handler_alert_accum_saturation.300239200
Short name T248
Test name
Test status
Simulation time 24133214 ps
CPU time 3.33 seconds
Started Aug 25 11:16:24 AM UTC 24
Finished Aug 25 11:16:29 AM UTC 24
Peak memory 263504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300239200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.300239200
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy_stress.1398360190
Short name T163
Test name
Test status
Simulation time 1240995041 ps
CPU time 69.86 seconds
Started Aug 25 11:16:17 AM UTC 24
Finished Aug 25 11:17:29 AM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398360190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1398360190
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_alert_accum.2822480694
Short name T84
Test name
Test status
Simulation time 2757451693 ps
CPU time 162.03 seconds
Started Aug 25 11:16:00 AM UTC 24
Finished Aug 25 11:18:45 AM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822480694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2822480694
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_intr_timeout.3511713766
Short name T46
Test name
Test status
Simulation time 2997522718 ps
CPU time 59.42 seconds
Started Aug 25 11:15:57 AM UTC 24
Finished Aug 25 11:16:58 AM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511713766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3511713766
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg_stub_clk.3155368385
Short name T539
Test name
Test status
Simulation time 125331090703 ps
CPU time 2999.51 seconds
Started Aug 25 11:16:15 AM UTC 24
Finished Aug 25 12:06:54 PM UTC 24
Peak memory 298468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155368385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3155368385
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/8.alert_handler_ping_timeout.2244681540
Short name T228
Test name
Test status
Simulation time 19287264242 ps
CPU time 178.71 seconds
Started Aug 25 11:16:11 AM UTC 24
Finished Aug 25 11:19:13 AM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244681540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2244681540
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_alerts.3538312644
Short name T368
Test name
Test status
Simulation time 1661263797 ps
CPU time 34.98 seconds
Started Aug 25 11:15:49 AM UTC 24
Finished Aug 25 11:16:25 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538312644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3538312644
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_classes.180530489
Short name T76
Test name
Test status
Simulation time 383417673 ps
CPU time 11.47 seconds
Started Aug 25 11:15:50 AM UTC 24
Finished Aug 25 11:16:02 AM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180530489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.180530489
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/8.alert_handler_smoke.1650827916
Short name T97
Test name
Test status
Simulation time 248029010 ps
CPU time 42.96 seconds
Started Aug 25 11:15:44 AM UTC 24
Finished Aug 25 11:16:29 AM UTC 24
Peak memory 263044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650827916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1650827916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/8.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/9.alert_handler_alert_accum_saturation.108109041
Short name T249
Test name
Test status
Simulation time 208754346 ps
CPU time 5.65 seconds
Started Aug 25 11:17:42 AM UTC 24
Finished Aug 25 11:17:49 AM UTC 24
Peak memory 263248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108109041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.108109041
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy.2803136868
Short name T70
Test name
Test status
Simulation time 7499364423 ps
CPU time 980.97 seconds
Started Aug 25 11:17:21 AM UTC 24
Finished Aug 25 11:33:56 AM UTC 24
Peak memory 285896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803136868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2803136868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy_stress.2987988273
Short name T79
Test name
Test status
Simulation time 450116459 ps
CPU time 29.16 seconds
Started Aug 25 11:17:38 AM UTC 24
Finished Aug 25 11:18:09 AM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987988273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2987988273
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_alert_accum.2625807163
Short name T415
Test name
Test status
Simulation time 1877788230 ps
CPU time 171.66 seconds
Started Aug 25 11:16:59 AM UTC 24
Finished Aug 25 11:19:54 AM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625807163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2625807163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_intr_timeout.3331463176
Short name T159
Test name
Test status
Simulation time 3577766664 ps
CPU time 58.36 seconds
Started Aug 25 11:16:41 AM UTC 24
Finished Aug 25 11:17:41 AM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331463176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3331463176
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg.3921239430
Short name T372
Test name
Test status
Simulation time 89358463812 ps
CPU time 2304.35 seconds
Started Aug 25 11:17:26 AM UTC 24
Finished Aug 25 11:56:21 AM UTC 24
Peak memory 302280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921239430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3921239430
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg_stub_clk.671373638
Short name T124
Test name
Test status
Simulation time 146387823803 ps
CPU time 3511.87 seconds
Started Aug 25 11:17:30 AM UTC 24
Finished Aug 25 12:16:49 PM UTC 24
Peak memory 304684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671373638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.671373638
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_alerts.2779816039
Short name T45
Test name
Test status
Simulation time 2036047200 ps
CPU time 64.47 seconds
Started Aug 25 11:16:30 AM UTC 24
Finished Aug 25 11:17:37 AM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779816039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2779816039
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/9.alert_handler_smoke.2130039419
Short name T98
Test name
Test status
Simulation time 27039446 ps
CPU time 4.83 seconds
Started Aug 25 11:16:29 AM UTC 24
Finished Aug 25 11:16:35 AM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130039419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2130039419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all.3453093472
Short name T291
Test name
Test status
Simulation time 41205142149 ps
CPU time 3021.23 seconds
Started Aug 25 11:17:38 AM UTC 24
Finished Aug 25 12:08:36 PM UTC 24
Peak memory 298528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453093472 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all.3453093472
Directory /workspaces/repo/scratch/os_regression_2024_08_24/alert_handler-sim-vcs/9.alert_handler_stress_all/latest
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