Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	61318	1			T13	535		T44	5		T14	1
class_i[0x1]	38372	1			T14	2		T84	10		T15	3
class_i[0x2]	60966	1			T39	1		T44	33		T28	7
class_i[0x3]	40277	1			T23	460		T53	3		T14	2

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	48750	1			T13	3		T23	19		T44	9
alert[0x1]	50574	1			T13	126		T23	387		T44	14
alert[0x2]	52100	1			T13	391		T23	30		T39	1
alert[0x3]	49509	1			T13	15		T23	24		T53	1

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

200638

1

T13

535

T23

460

T39

1

esc_ping_fail

295

1

T14

2

T15

3

T16

8

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	48670	1			T13	3		T23	19		T44	9
esc_integrity_fail	alert[0x1]	50501	1			T13	126		T23	387		T44	14
esc_integrity_fail	alert[0x2]	52025	1			T13	391		T23	30		T39	1
esc_integrity_fail	alert[0x3]	49442	1			T13	15		T23	24		T53	1
esc_ping_fail	alert[0x0]	80	1			T14	1		T16	2		T151	2
esc_ping_fail	alert[0x1]	73	1			T15	1		T16	3		T151	1
esc_ping_fail	alert[0x2]	75	1			T14	1		T15	1		T16	2
esc_ping_fail	alert[0x3]	67	1			T15	1		T16	1		T151	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	61248	1			T13	535		T44	5		T133	8
esc_integrity_fail	class_i[0x1]	38317	1			T14	2		T84	10		T133	6
esc_integrity_fail	class_i[0x2]	60874	1			T39	1		T44	33		T28	7
esc_integrity_fail	class_i[0x3]	40199	1			T23	460		T53	3		T14	1
esc_ping_fail	class_i[0x0]	70	1			T14	1		T317	9		T340	1
esc_ping_fail	class_i[0x1]	55	1			T15	3		T16	8		T261	10
esc_ping_fail	class_i[0x2]	92	1			T314	7		T317	1		T112	1
esc_ping_fail	class_i[0x3]	78	1			T14	1		T151	6		T152	8