Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.22	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	4	40	90.91

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	4	40	90.91	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	153	1			T50	1		T122	1		T28	2
index[0x1]	163	1			T2	1		T13	1		T24	2
index[0x2]	172	1			T12	1		T21	1		T50	2
index[0x3]	156	1			T23	1		T53	1		T54	2

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	195	1			T13	1		T24	2		T28	2
lens_less_than_1000[1]	142	1			T2	1		T12	1		T74	2
lens_less_than_1000[2]	103	1			T84	1		T56	1		T149	1
lens_less_than_1000[3]	73	1			T23	1		T50	1		T45	1
lens_less_than_1000[4]	50	1			T53	1		T31	1		T96	1
lens_less_than_1000[5]	20	1			T88	1		T96	1		T135	1
lens_less_than_1000[6]	23	1			T34	1		T96	1		T82	1
lens_less_than_1000[7]	14	1			T21	1		T77	1		T263	1
lens_less_than_1000[8]	14	1			T50	2		T27	1		T45	1
lens_less_than_1000[9]	1	1			T124	1		-	-		-	-
len_2	9	1			T264	1		T265	1		T126	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	4	40	90.91	4

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1
[index[0x1]]	[lens_less_than_1000[9] , len_2]	--	--	2
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	55	1			T28	2		T40	1		T152	1
index[0x0]	lens_less_than_1000[1]	28	1			T122	1		T32	1		T139	2
index[0x0]	lens_less_than_1000[2]	27	1			T150	1		T113	1		T45	1
index[0x0]	lens_less_than_1000[3]	10	1			T50	1		T45	1		T118	4
index[0x0]	lens_less_than_1000[4]	10	1			T31	1		T46	1		T266	1
index[0x0]	lens_less_than_1000[5]	7	1			T135	1		T267	1		T62	1
index[0x0]	lens_less_than_1000[6]	5	1			T266	1		T268	1		T269	1
index[0x0]	lens_less_than_1000[7]	1	1			T270	1		-	-		-	-
index[0x0]	lens_less_than_1000[8]	5	1			T45	1		T111	1		T271	2
index[0x0]	len_2	5	1			T265	1		T126	1		T71	1
index[0x1]	lens_less_than_1000[0]	46	1			T13	1		T24	2		T56	1
index[0x1]	lens_less_than_1000[1]	32	1			T2	1		T74	1		T254	1
index[0x1]	lens_less_than_1000[2]	34	1			T56	1		T149	1		T45	1
index[0x1]	lens_less_than_1000[3]	14	1			T102	1		T272	1		T124	1
index[0x1]	lens_less_than_1000[4]	16	1			T96	1		T46	1		T273	1
index[0x1]	lens_less_than_1000[5]	5	1			T88	1		T125	1		T126	1
index[0x1]	lens_less_than_1000[6]	9	1			T96	1		T274	1		T137	1
index[0x1]	lens_less_than_1000[7]	5	1			T275	1		T256	1		T276	1
index[0x1]	lens_less_than_1000[8]	2	1			T27	1		T139	1		-	-
index[0x2]	lens_less_than_1000[0]	49	1			T85	1		T29	1		T97	1
index[0x2]	lens_less_than_1000[1]	34	1			T12	1		T74	1		T56	1
index[0x2]	lens_less_than_1000[2]	25	1			T90	1		T96	1		T102	1
index[0x2]	lens_less_than_1000[3]	30	1			T263	1		T97	1		T277	1
index[0x2]	lens_less_than_1000[4]	16	1			T58	1		T98	1		T119	1
index[0x2]	lens_less_than_1000[5]	4	1			T66	1		T125	1		T270	1
index[0x2]	lens_less_than_1000[6]	5	1			T34	1		T278	1		T279	1
index[0x2]	lens_less_than_1000[7]	2	1			T21	1		T280	1		-	-
index[0x2]	lens_less_than_1000[8]	4	1			T50	2		T281	1		T282	1
index[0x2]	lens_less_than_1000[9]	1	1			T124	1		-	-		-	-
index[0x2]	len_2	2	1			T264	1		T283	1		-	-
index[0x3]	lens_less_than_1000[0]	45	1			T54	1		T31	2		T56	1
index[0x3]	lens_less_than_1000[1]	48	1			T54	1		T56	1		T150	1
index[0x3]	lens_less_than_1000[2]	17	1			T84	1		T96	1		T35	1
index[0x3]	lens_less_than_1000[3]	19	1			T23	1		T95	1		T97	1
index[0x3]	lens_less_than_1000[4]	8	1			T53	1		T284	1		T285	1
index[0x3]	lens_less_than_1000[5]	4	1			T96	1		T266	1		T286	1
index[0x3]	lens_less_than_1000[6]	4	1			T82	1		T276	1		T287	1
index[0x3]	lens_less_than_1000[7]	6	1			T77	1		T263	1		T265	1
index[0x3]	lens_less_than_1000[8]	3	1			T61	2		T288	1		-	-
index[0x3]	len_2	2	1			T289	1		T290	1		-	-