Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	56	1			T54	1		T41	1		T94	1
class_index[0x1]	52	1			T13	1		T29	1		T94	1
class_index[0x2]	52	1			T3	1		T13	1		T36	1
class_index[0x3]	48	1			T13	1		T75	1		T91	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	89	1			T3	1		T54	2		T41	1
intr_timeout_cnt[1]	40	1			T36	1		T75	1		T94	1
intr_timeout_cnt[2]	16	1			T45	1		T100	1		T136	1
intr_timeout_cnt[3]	19	1			T13	1		T99	2		T291	4
intr_timeout_cnt[4]	11	1			T95	1		T99	1		T124	3
intr_timeout_cnt[5]	6	1			T13	2		T154	1		T135	1
intr_timeout_cnt[6]	8	1			T292	1		T126	1		T270	1
intr_timeout_cnt[7]	6	1			T78	1		T70	3		T293	1
intr_timeout_cnt[8]	9	1			T98	1		T135	1		T136	1
intr_timeout_cnt[9]	4	1			T94	1		T95	1		T281	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	29	1			T54	1		T41	1		T77	1
class_index[0x0]	intr_timeout_cnt[1]	10	1			T94	1		T103	1		T266	1
class_index[0x0]	intr_timeout_cnt[2]	5	1			T292	1		T270	1		T294	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T99	2		T295	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	2	1			T296	1		T297	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	1	1			T124	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T282	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	4	1			T98	1		T63	1		T298	2
class_index[0x0]	intr_timeout_cnt[9]	1	1			T281	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	28	1			T29	1		T90	1		T95	1
class_index[0x1]	intr_timeout_cnt[1]	5	1			T102	1		T299	1		T300	1
class_index[0x1]	intr_timeout_cnt[2]	2	1			T100	1		T282	1		-	-
class_index[0x1]	intr_timeout_cnt[3]	4	1			T13	1		T301	3		-	-
class_index[0x1]	intr_timeout_cnt[4]	6	1			T124	3		T69	1		T281	1
class_index[0x1]	intr_timeout_cnt[6]	2	1			T126	1		T282	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T70	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T123	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T94	1		T95	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	11	1			T3	1		T54	1		T38	1
class_index[0x2]	intr_timeout_cnt[1]	10	1			T36	1		T153	2		T125	1
class_index[0x2]	intr_timeout_cnt[2]	5	1			T45	1		T63	1		T286	1
class_index[0x2]	intr_timeout_cnt[3]	10	1			T291	4		T125	1		T302	5
class_index[0x2]	intr_timeout_cnt[4]	2	1			T95	1		T99	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	3	1			T13	1		T154	1		T135	1
class_index[0x2]	intr_timeout_cnt[6]	5	1			T270	1		T303	4		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T78	1		T293	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	3	1			T136	1		T304	1		T298	1
class_index[0x2]	intr_timeout_cnt[9]	1	1			T298	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	21	1			T91	1		T77	1		T134	1
class_index[0x3]	intr_timeout_cnt[1]	15	1			T75	1		T137	1		T291	3
class_index[0x3]	intr_timeout_cnt[2]	4	1			T136	1		T290	1		T298	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T305	1		T306	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	1	1			T255	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	2	1			T13	1		T63	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T292	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	1	1			T70	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T135	1		-	-		-	-