Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	289500	1			T2	7		T3	9		T11	5
all_values[1]	289500	1			T2	7		T3	9		T11	5
all_values[2]	289500	1			T2	7		T3	9		T11	5
all_values[3]	289500	1			T2	7		T3	9		T11	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

575362

1

T2

11

T3

14

T11

13

auto[1]

582638

1

T2

17

T3

22

T11

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

681407

1

T2

25

T3

20

T11

12

auto[1]

476593

1

T2

3

T3

16

T11

8

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	82195	1			T2	2		T3	2		T9	2
all_values[0]	auto[0]	auto[1]	61383	1			T2	2		T3	2		T9	1
all_values[0]	auto[1]	auto[0]	84098	1			T2	2		T3	3		T11	3
all_values[0]	auto[1]	auto[1]	61824	1			T2	1		T3	2		T11	2
all_values[1]	auto[0]	auto[0]	84953	1			T2	2		T3	2		T11	3
all_values[1]	auto[0]	auto[1]	59239	1			T3	1		T11	2		T12	6
all_values[1]	auto[1]	auto[0]	85854	1			T2	5		T3	3		T9	3
all_values[1]	auto[1]	auto[1]	59454	1			T3	3		T12	7		T13	4
all_values[2]	auto[0]	auto[0]	85075	1			T2	2		T3	2		T11	3
all_values[2]	auto[0]	auto[1]	58079	1			T3	1		T11	2		T12	8
all_values[2]	auto[1]	auto[0]	87446	1			T2	5		T3	3		T12	6
all_values[2]	auto[1]	auto[1]	58900	1			T3	3		T12	5		T13	7
all_values[3]	auto[0]	auto[0]	85431	1			T2	3		T3	2		T11	2
all_values[3]	auto[0]	auto[1]	59007	1			T3	2		T11	1		T12	10
all_values[3]	auto[1]	auto[0]	86355	1			T2	4		T3	3		T11	1
all_values[3]	auto[1]	auto[1]	58707	1			T3	2		T11	1		T12	3