Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	289500	1			T2	7		T3	9		T11	5
all_pins[1]	289500	1			T2	7		T3	9		T11	5
all_pins[2]	289500	1			T2	7		T3	9		T11	5
all_pins[3]	289500	1			T2	7		T3	9		T11	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	919115	1			T2	27		T3	26		T11	17
values[0x1]	238885	1			T2	1		T3	10		T11	3
transitions[0x0=>0x1]	157076	1			T2	1		T3	5		T11	2
transitions[0x1=>0x0]	157332	1			T2	1		T3	5		T11	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	227676	1			T2	6		T3	7		T11	3
all_pins[0]	values[0x1]	61824	1			T2	1		T3	2		T11	2
all_pins[0]	transitions[0x0=>0x1]	61243	1			T2	1		T3	2		T11	1
all_pins[0]	transitions[0x1=>0x0]	58382	1			T3	2		T11	1		T12	3
all_pins[1]	values[0x0]	230046	1			T2	7		T3	6		T11	5
all_pins[1]	values[0x1]	59454	1			T3	3		T12	7		T13	4
all_pins[1]	transitions[0x0=>0x1]	31977	1			T3	2		T12	2		T13	3
all_pins[1]	transitions[0x1=>0x0]	34347	1			T2	1		T3	1		T11	2
all_pins[2]	values[0x0]	230600	1			T2	7		T3	6		T11	5
all_pins[2]	values[0x1]	58900	1			T3	3		T12	5		T13	7
all_pins[2]	transitions[0x0=>0x1]	32002	1			T12	2		T13	3		T23	4
all_pins[2]	transitions[0x1=>0x0]	32556	1			T12	4		T23	3		T49	4
all_pins[3]	values[0x0]	230793	1			T2	7		T3	7		T11	4
all_pins[3]	values[0x1]	58707	1			T3	2		T11	1		T12	3
all_pins[3]	transitions[0x0=>0x1]	31854	1			T3	1		T11	1		T12	2
all_pins[3]	transitions[0x1=>0x0]	32047	1			T3	2		T12	4		T13	4