Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1			T195	4		T197	7		T374	4
all_values[1]	269	1			T195	4		T197	7		T374	4
all_values[2]	269	1			T195	4		T197	7		T374	4
all_values[3]	269	1			T195	4		T197	7		T374	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

571

1

T195

10

T197

15

T374

9

auto[1]

505

1

T195

6

T197

13

T374

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

434

1

T195

5

T197

7

T374

5

auto[1]

642

1

T195

11

T197

21

T374

11

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

647

1

T195

7

T197

14

T374

8

auto[1]

429

1

T195

9

T197

14

T374

8

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

55

1

T375

1

T376

1

T377

1

all_values[0]

auto[0]

auto[0]

auto[1]

32

1

T195

1

T197

1

T374

1

all_values[0]

auto[0]

auto[1]

auto[0]

42

1

T195

1

T375

1

T377

2

all_values[0]

auto[0]

auto[1]

auto[1]

23

1

T374

1

T376

2

T378

2

all_values[0]

auto[1]

auto[0]

auto[1]

55

1

T195

1

T197

4

T379

2

all_values[0]

auto[1]

auto[1]

auto[1]

62

1

T195

1

T197

2

T374

2

all_values[1]

auto[0]

auto[0]

auto[0]

56

1

T195

1

T375

2

T379

2

all_values[1]

auto[0]

auto[0]

auto[1]

17

1

T197

2

T375

1

T380

1

all_values[1]

auto[0]

auto[1]

auto[0]

59

1

T195

1

T374

2

T376

2

all_values[1]

auto[0]

auto[1]

auto[1]

29

1

T197

2

T377

1

T379

1

all_values[1]

auto[1]

auto[0]

auto[1]

60

1

T195

1

T197

2

T374

2

all_values[1]

auto[1]

auto[1]

auto[1]

48

1

T195

1

T197

1

T376

2

all_values[2]

auto[0]

auto[0]

auto[0]

69

1

T197

2

T374

2

T375

2

all_values[2]

auto[0]

auto[0]

auto[1]

29

1

T195

1

T197

1

T379

1

all_values[2]

auto[0]

auto[1]

auto[0]

48

1

T197

1

T375

2

T376

2

all_values[2]

auto[0]

auto[1]

auto[1]

25

1

T197

1

T377

1

T379

1

all_values[2]

auto[1]

auto[0]

auto[1]

53

1

T195

1

T374

2

T376

1

all_values[2]

auto[1]

auto[1]

auto[1]

45

1

T195

2

T197

2

T376

2

all_values[3]

auto[0]

auto[0]

auto[0]

56

1

T195

2

T197

1

T376

1

all_values[3]

auto[0]

auto[0]

auto[1]

33

1

T374

1

T375

1

T376

2

all_values[3]

auto[0]

auto[1]

auto[0]

49

1

T197

3

T374

1

T375

1

all_values[3]

auto[0]

auto[1]

auto[1]

25

1

T381

1

T382

1

T383

2

all_values[3]

auto[1]

auto[0]

auto[1]

56

1

T195

2

T197

2

T374

1

all_values[3]

auto[1]

auto[1]

auto[1]

50

1

T197

1

T374

1

T375

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal