Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	89777	1			T258	59		T139	239		T312	833
accum_cnt_1000	183953	1			T52	89		T122	40		T88	2
accum_cnt_100	20671	1			T24	7		T27	4		T39	3
accum_cnt_50	47796	1			T2	3		T12	30		T24	10
accum_cnt_10	153610	1			T2	2		T3	17		T11	8
accum_cnt_0	316378	1			T2	15		T3	15		T11	8

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	214365	1			T2	5		T3	8		T11	4
class_index[0x1]	214365	1			T2	5		T3	8		T11	4
class_index[0x2]	214365	1			T2	5		T3	8		T11	4
class_index[0x3]	214365	1			T2	5		T3	8		T11	4

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22475	1			T258	59		T313	703		T61	199
class_index[0x0]	accum_cnt_1000	43030	1			T252	8		T258	708		T262	23
class_index[0x0]	accum_cnt_100	5627	1			T24	7		T27	4		T39	3
class_index[0x0]	accum_cnt_50	10672	1			T2	3		T12	9		T24	10
class_index[0x0]	accum_cnt_10	50433	1			T2	2		T3	5		T9	1
class_index[0x0]	accum_cnt_0	68209	1			T3	3		T11	4		T9	6
class_index[0x1]	accum_cnt_2000	21167	1			T274	203		T61	75		T62	115
class_index[0x1]	accum_cnt_1000	48014	1			T88	2		T250	707		T37	631
class_index[0x1]	accum_cnt_100	4892	1			T88	16		T150	9		T94	2
class_index[0x1]	accum_cnt_50	12705	1			T12	5		T49	22		T75	10
class_index[0x1]	accum_cnt_10	40276	1			T3	4		T12	10		T13	14
class_index[0x1]	accum_cnt_0	77895	1			T2	5		T3	4		T11	4
class_index[0x2]	accum_cnt_2000	24142	1			T139	220		T312	425		T313	499
class_index[0x2]	accum_cnt_1000	48092	1			T52	37		T84	1		T94	52
class_index[0x2]	accum_cnt_100	5312	1			T52	30		T44	7		T88	5
class_index[0x2]	accum_cnt_50	10773	1			T12	4		T87	6		T43	17
class_index[0x2]	accum_cnt_10	28812	1			T3	4		T11	4		T12	11
class_index[0x2]	accum_cnt_0	84247	1			T2	5		T3	4		T9	7
class_index[0x3]	accum_cnt_2000	21993	1			T139	19		T312	408		T62	641
class_index[0x3]	accum_cnt_1000	44817	1			T52	52		T122	40		T150	2
class_index[0x3]	accum_cnt_100	4840	1			T52	22		T122	18		T150	17
class_index[0x3]	accum_cnt_50	13646	1			T12	12		T52	18		T53	1
class_index[0x3]	accum_cnt_10	34089	1			T3	4		T11	4		T12	5
class_index[0x3]	accum_cnt_0	86027	1			T2	5		T3	4		T9	7