Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	12133	1			T35	2		T314	1		T315	472
alert[0x1]	9871	1			T50	5		T151	1		T113	2
alert[0x2]	3043	1			T15	1		T152	1		T37	3
alert[0x3]	4852	1			T44	7		T139	1048		T315	186
alert[0x4]	8353	1			T28	1		T16	1		T35	39
alert[0x5]	3826	1			T23	1		T151	1		T37	21
alert[0x6]	5873	1			T258	1		T261	1		T316	1
alert[0x7]	6068	1			T151	1		T94	1		T261	1
alert[0x8]	6124	1			T86	6		T90	2		T314	1
alert[0x9]	8343	1			T23	19		T56	2		T152	1
alert[0xa]	14859	1			T97	5		T317	1		T139	23
alert[0xb]	3370	1			T14	1		T16	1		T261	1
alert[0xc]	6446	1			T44	10		T16	1		T261	1
alert[0xd]	4699	1			T139	75		T112	1		T318	1
alert[0xe]	6670	1			T97	1		T98	1		T316	1
alert[0xf]	6134	1			T16	1		T151	1		T152	1
alert[0x10]	5794	1			T90	1		T319	2		T64	31
alert[0x11]	8336	1			T35	253		T60	10		T314	1
alert[0x12]	2978	1			T15	1		T151	1		T113	6
alert[0x13]	12373	1			T53	3		T56	1		T151	1
alert[0x14]	5175	1			T56	12		T152	1		T258	1
alert[0x15]	4054	1			T15	1		T37	1		T95	1
alert[0x16]	4781	1			T16	1		T320	1		T321	1
alert[0x17]	10574	1			T56	1		T152	1		T90	6
alert[0x18]	11118	1			T15	1		T16	1		T152	1
alert[0x19]	4991	1			T16	1		T113	1		T35	4
alert[0x1a]	6124	1			T151	1		T90	5		T37	1
alert[0x1b]	2061	1			T23	4		T152	1		T316	2
alert[0x1c]	5952	1			T14	1		T56	1		T37	1
alert[0x1d]	7204	1			T23	2		T37	3		T35	6
alert[0x1e]	4774	1			T90	2		T64	118		T322	2
alert[0x1f]	2986	1			T16	1		T37	1		T314	2
alert[0x20]	5891	1			T35	1		T100	1		T139	12
alert[0x21]	897	1			T23	2		T35	20		T323	2
alert[0x22]	4018	1			T15	1		T320	1		T38	2
alert[0x23]	7009	1			T15	1		T56	1		T151	1
alert[0x24]	17094	1			T50	1		T321	2		T139	213
alert[0x25]	4193	1			T35	3		T316	1		T100	3
alert[0x26]	1948	1			T151	1		T152	2		T154	2
alert[0x27]	3383	1			T94	61		T317	1		T139	167
alert[0x28]	5993	1			T152	1		T90	2		T261	1
alert[0x29]	3600	1			T56	4		T151	1		T314	1
alert[0x2a]	2010	1			T23	3		T113	27		T152	1
alert[0x2b]	5964	1			T23	20		T37	1		T139	821
alert[0x2c]	4525	1			T44	4		T15	2		T16	1
alert[0x2d]	6284	1			T152	1		T320	1		T316	1
alert[0x2e]	8370	1			T44	1		T16	1		T94	7
alert[0x2f]	3672	1			T16	1		T151	1		T152	1
alert[0x30]	5512	1			T39	8		T152	1		T317	1
alert[0x31]	1463	1			T39	2		T35	1		T317	1
alert[0x32]	8608	1			T320	1		T98	6		T321	1
alert[0x33]	3915	1			T23	3		T15	1		T45	77
alert[0x34]	6534	1			T35	5		T323	1		T324	1
alert[0x35]	5150	1			T16	2		T86	15		T139	13
alert[0x36]	4872	1			T23	12		T53	9		T261	2
alert[0x37]	5982	1			T14	1		T16	1		T37	4
alert[0x38]	11144	1			T44	3		T14	1		T37	2
alert[0x39]	4981	1			T133	3		T152	2		T98	2
alert[0x3a]	3845	1			T39	1		T152	1		T94	3
alert[0x3b]	10097	1			T28	1		T14	1		T151	1
alert[0x3c]	4590	1			T314	2		T321	1		T139	26
alert[0x3d]	5664	1			T50	2		T16	1		T56	20
alert[0x3e]	3511	1			T15	1		T56	23		T86	2
alert[0x3f]	12148	1			T16	1		T35	4		T139	12
alert[0x40]	3992	1			T39	1		T15	1		T37	5

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	93884	1			T50	8		T44	8		T28	1
class_i[0x1]	93709	1			T39	12		T14	3		T15	9
class_i[0x2]	126058	1			T23	66		T44	17		T28	1
class_i[0x3]	83147	1			T53	12		T14	1		T15	2

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

396125

1

T23

66

T50

8

T39

12

alert_ping_fail

673

1

T14

5

T15

11

T16

16

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	12125	1			T35	2		T315	472		T146	23
alert_integrity_fail	alert[0x1]	9861	1			T50	5		T113	2		T78	3
alert_integrity_fail	alert[0x2]	3033	1			T37	3		T35	3		T98	2
alert_integrity_fail	alert[0x3]	4847	1			T44	7		T139	1048		T315	186
alert_integrity_fail	alert[0x4]	8348	1			T28	1		T35	39		T139	18
alert_integrity_fail	alert[0x5]	3812	1			T23	1		T37	21		T78	1
alert_integrity_fail	alert[0x6]	5860	1			T139	48		T325	5		T62	79
alert_integrity_fail	alert[0x7]	6057	1			T94	1		T139	4		T61	31
alert_integrity_fail	alert[0x8]	6116	1			T86	6		T90	2		T135	4
alert_integrity_fail	alert[0x9]	8335	1			T23	19		T56	2		T97	2
alert_integrity_fail	alert[0xa]	14849	1			T97	5		T139	23		T103	8
alert_integrity_fail	alert[0xb]	3361	1			T35	2		T103	5		T61	76
alert_integrity_fail	alert[0xc]	6439	1			T44	10		T60	34		T139	2
alert_integrity_fail	alert[0xd]	4692	1			T139	75		T322	3		T146	2
alert_integrity_fail	alert[0xe]	6658	1			T97	1		T98	1		T139	306
alert_integrity_fail	alert[0xf]	6125	1			T139	864		T315	5		T141	2
alert_integrity_fail	alert[0x10]	5790	1			T90	1		T319	2		T64	31
alert_integrity_fail	alert[0x11]	8330	1			T35	253		T60	10		T62	2741
alert_integrity_fail	alert[0x12]	2968	1			T113	6		T139	1532		T326	97
alert_integrity_fail	alert[0x13]	12358	1			T53	3		T56	1		T113	1
alert_integrity_fail	alert[0x14]	5158	1			T56	12		T35	3		T60	19
alert_integrity_fail	alert[0x15]	4040	1			T37	1		T95	1		T154	1
alert_integrity_fail	alert[0x16]	4755	1			T139	126		T278	1		T274	1
alert_integrity_fail	alert[0x17]	10567	1			T56	1		T90	6		T60	19
alert_integrity_fail	alert[0x18]	11102	1			T94	10		T37	7		T95	1
alert_integrity_fail	alert[0x19]	4979	1			T113	1		T35	4		T62	27
alert_integrity_fail	alert[0x1a]	6114	1			T90	5		T37	1		T103	2
alert_integrity_fail	alert[0x1b]	2047	1			T23	4		T139	115		T103	2
alert_integrity_fail	alert[0x1c]	5939	1			T56	1		T37	1		T98	1
alert_integrity_fail	alert[0x1d]	7195	1			T23	2		T37	3		T35	6
alert_integrity_fail	alert[0x1e]	4768	1			T90	2		T64	118		T322	2
alert_integrity_fail	alert[0x1f]	2976	1			T37	1		T62	17		T146	18
alert_integrity_fail	alert[0x20]	5880	1			T35	1		T100	1		T139	12
alert_integrity_fail	alert[0x21]	888	1			T23	2		T35	20		T278	17
alert_integrity_fail	alert[0x22]	3996	1			T38	2		T60	23		T139	2
alert_integrity_fail	alert[0x23]	6999	1			T56	1		T154	6		T278	3
alert_integrity_fail	alert[0x24]	17085	1			T50	1		T139	213		T325	4
alert_integrity_fail	alert[0x25]	4182	1			T35	3		T100	3		T139	3
alert_integrity_fail	alert[0x26]	1939	1			T154	2		T97	2		T60	3
alert_integrity_fail	alert[0x27]	3379	1			T94	61		T139	167		T274	1
alert_integrity_fail	alert[0x28]	5981	1			T90	2		T61	10		T64	1284
alert_integrity_fail	alert[0x29]	3594	1			T56	4		T274	20		T61	332
alert_integrity_fail	alert[0x2a]	1998	1			T23	3		T113	27		T35	7
alert_integrity_fail	alert[0x2b]	5957	1			T23	20		T37	1		T139	821
alert_integrity_fail	alert[0x2c]	4507	1			T44	4		T56	7		T95	4
alert_integrity_fail	alert[0x2d]	6272	1			T274	79		T62	27		T64	4
alert_integrity_fail	alert[0x2e]	8362	1			T44	1		T94	7		T37	101
alert_integrity_fail	alert[0x2f]	3659	1			T78	1		T62	177		T64	331
alert_integrity_fail	alert[0x30]	5502	1			T39	8		T326	97		T327	22
alert_integrity_fail	alert[0x31]	1457	1			T39	2		T35	1		T139	22
alert_integrity_fail	alert[0x32]	8600	1			T98	6		T139	317		T315	198
alert_integrity_fail	alert[0x33]	3905	1			T23	3		T45	77		T154	5
alert_integrity_fail	alert[0x34]	6524	1			T35	5		T62	43		T315	26
alert_integrity_fail	alert[0x35]	5143	1			T86	15		T139	13		T61	41
alert_integrity_fail	alert[0x36]	4863	1			T23	12		T53	9		T97	4
alert_integrity_fail	alert[0x37]	5967	1			T37	4		T60	1		T100	4
alert_integrity_fail	alert[0x38]	11134	1			T44	3		T37	2		T78	2
alert_integrity_fail	alert[0x39]	4973	1			T133	3		T98	2		T60	4
alert_integrity_fail	alert[0x3a]	3834	1			T39	1		T94	3		T37	15
alert_integrity_fail	alert[0x3b]	10087	1			T28	1		T45	5		T100	5
alert_integrity_fail	alert[0x3c]	4574	1			T139	26		T102	8		T62	17
alert_integrity_fail	alert[0x3d]	5653	1			T50	2		T56	20		T60	1
alert_integrity_fail	alert[0x3e]	3493	1			T56	23		T86	2		T35	3
alert_integrity_fail	alert[0x3f]	12145	1			T35	4		T139	12		T135	2
alert_integrity_fail	alert[0x40]	3989	1			T39	1		T37	5		T60	23
alert_ping_fail	alert[0x0]	8	1			T314	1		T328	2		T329	2
alert_ping_fail	alert[0x1]	10	1			T151	1		T321	2		T318	1
alert_ping_fail	alert[0x2]	10	1			T15	1		T152	1		T320	1
alert_ping_fail	alert[0x3]	5	1			T330	3		T331	1		T332	1
alert_ping_fail	alert[0x4]	5	1			T16	1		T333	1		T329	1
alert_ping_fail	alert[0x5]	14	1			T151	1		T314	2		T112	1
alert_ping_fail	alert[0x6]	13	1			T258	1		T261	1		T316	1
alert_ping_fail	alert[0x7]	11	1			T151	1		T261	1		T317	1
alert_ping_fail	alert[0x8]	8	1			T314	1		T317	1		T323	1
alert_ping_fail	alert[0x9]	8	1			T152	1		T320	1		T317	1
alert_ping_fail	alert[0xa]	10	1			T317	1		T333	1		T334	1
alert_ping_fail	alert[0xb]	9	1			T14	1		T16	1		T261	1
alert_ping_fail	alert[0xc]	7	1			T16	1		T261	1		T316	1
alert_ping_fail	alert[0xd]	7	1			T112	1		T318	1		T335	1
alert_ping_fail	alert[0xe]	12	1			T316	1		T314	1		T317	2
alert_ping_fail	alert[0xf]	9	1			T16	1		T151	1		T152	1
alert_ping_fail	alert[0x10]	4	1			T336	1		T337	1		T283	1
alert_ping_fail	alert[0x11]	6	1			T314	1		T323	2		T338	1
alert_ping_fail	alert[0x12]	10	1			T15	1		T151	1		T261	1
alert_ping_fail	alert[0x13]	15	1			T151	1		T317	1		T323	1
alert_ping_fail	alert[0x14]	17	1			T152	1		T258	1		T321	1
alert_ping_fail	alert[0x15]	14	1			T15	1		T258	1		T316	2
alert_ping_fail	alert[0x16]	26	1			T16	1		T320	1		T321	1
alert_ping_fail	alert[0x17]	7	1			T152	1		T261	1		T323	1
alert_ping_fail	alert[0x18]	16	1			T15	1		T16	1		T152	1
alert_ping_fail	alert[0x19]	12	1			T16	1		T323	1		T112	1
alert_ping_fail	alert[0x1a]	10	1			T151	1		T261	1		T316	1
alert_ping_fail	alert[0x1b]	14	1			T152	1		T316	2		T339	1
alert_ping_fail	alert[0x1c]	13	1			T14	1		T316	1		T314	1
alert_ping_fail	alert[0x1d]	9	1			T340	1		T324	1		T341	2
alert_ping_fail	alert[0x1e]	6	1			T338	1		T342	1		T283	1
alert_ping_fail	alert[0x1f]	10	1			T16	1		T314	2		T317	1
alert_ping_fail	alert[0x20]	11	1			T343	1		T328	1		T335	1
alert_ping_fail	alert[0x21]	9	1			T323	2		T337	1		T344	1
alert_ping_fail	alert[0x22]	22	1			T15	1		T320	1		T317	1
alert_ping_fail	alert[0x23]	10	1			T15	1		T151	1		T152	1
alert_ping_fail	alert[0x24]	9	1			T321	2		T340	1		T345	1
alert_ping_fail	alert[0x25]	11	1			T316	1		T323	1		T339	1
alert_ping_fail	alert[0x26]	9	1			T151	1		T152	2		T316	1
alert_ping_fail	alert[0x27]	4	1			T317	1		T318	1		T324	1
alert_ping_fail	alert[0x28]	12	1			T152	1		T261	1		T320	1
alert_ping_fail	alert[0x29]	6	1			T151	1		T314	1		T317	1
alert_ping_fail	alert[0x2a]	12	1			T152	1		T261	2		T321	1
alert_ping_fail	alert[0x2b]	7	1			T308	1		T336	1		T341	2
alert_ping_fail	alert[0x2c]	18	1			T15	2		T16	1		T261	1
alert_ping_fail	alert[0x2d]	12	1			T152	1		T320	1		T316	1
alert_ping_fail	alert[0x2e]	8	1			T16	1		T261	1		T320	1
alert_ping_fail	alert[0x2f]	13	1			T16	1		T151	1		T152	1
alert_ping_fail	alert[0x30]	10	1			T152	1		T317	1		T318	1
alert_ping_fail	alert[0x31]	6	1			T317	1		T117	1		T329	1
alert_ping_fail	alert[0x32]	8	1			T320	1		T321	1		T112	1
alert_ping_fail	alert[0x33]	10	1			T15	1		T316	1		T318	1
alert_ping_fail	alert[0x34]	10	1			T323	1		T324	1		T339	1
alert_ping_fail	alert[0x35]	7	1			T16	2		T343	1		T346	1
alert_ping_fail	alert[0x36]	9	1			T261	2		T318	1		T346	1
alert_ping_fail	alert[0x37]	15	1			T14	1		T16	1		T320	2
alert_ping_fail	alert[0x38]	10	1			T14	1		T261	1		T316	1
alert_ping_fail	alert[0x39]	8	1			T152	2		T314	2		T317	1
alert_ping_fail	alert[0x3a]	11	1			T152	1		T261	1		T333	1
alert_ping_fail	alert[0x3b]	10	1			T14	1		T151	1		T314	1
alert_ping_fail	alert[0x3c]	16	1			T314	2		T321	1		T112	1
alert_ping_fail	alert[0x3d]	11	1			T16	1		T320	1		T314	1
alert_ping_fail	alert[0x3e]	18	1			T15	1		T261	1		T316	2
alert_ping_fail	alert[0x3f]	3	1			T16	1		T339	1		T346	1
alert_ping_fail	alert[0x40]	3	1			T15	1		T334	2		-	-

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	93735	1			T50	8		T44	8		T28	1
alert_integrity_fail	class_i[0x1]	93556	1			T39	12		T133	3		T56	9
alert_integrity_fail	class_i[0x2]	125918	1			T23	66		T44	17		T28	1
alert_integrity_fail	class_i[0x3]	82916	1			T53	12		T37	15		T45	50
alert_ping_fail	class_i[0x0]	149	1			T14	1		T152	15		T320	9
alert_ping_fail	class_i[0x1]	153	1			T14	3		T15	9		T152	1
alert_ping_fail	class_i[0x2]	140	1			T151	12		T152	2		T261	18
alert_ping_fail	class_i[0x3]	231	1			T14	1		T15	2		T16	16