| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.24 | 99.99 | 98.67 | 97.09 | 100.00 | 100.00 | 99.38 | 99.52 |
| T162 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.270565735 | Aug 29 07:22:39 AM UTC 24 | Aug 29 07:30:17 AM UTC 24 | 5974035126 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.1662907998 | Aug 29 07:30:16 AM UTC 24 | Aug 29 07:30:24 AM UTC 24 | 65849820 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.795915272 | Aug 29 07:30:18 AM UTC 24 | Aug 29 07:30:26 AM UTC 24 | 29525582 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.1987073867 | Aug 29 07:30:27 AM UTC 24 | Aug 29 07:30:36 AM UTC 24 | 42019260 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.1422429688 | Aug 29 07:30:36 AM UTC 24 | Aug 29 07:30:39 AM UTC 24 | 8128045 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1871766724 | Aug 29 07:23:02 AM UTC 24 | Aug 29 07:30:47 AM UTC 24 | 2149304870 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.2390752622 | Aug 29 07:30:40 AM UTC 24 | Aug 29 07:30:50 AM UTC 24 | 252486996 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3418617761 | Aug 29 07:29:46 AM UTC 24 | Aug 29 07:30:56 AM UTC 24 | 683555685 ps | ||
| T172 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1254716548 | Aug 29 07:22:39 AM UTC 24 | Aug 29 07:30:56 AM UTC 24 | 2582430383 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.4137511014 | Aug 29 07:30:17 AM UTC 24 | Aug 29 07:30:56 AM UTC 24 | 1316754051 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1844949483 | Aug 29 07:30:50 AM UTC 24 | Aug 29 07:30:58 AM UTC 24 | 102227096 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.3773881620 | Aug 29 07:30:56 AM UTC 24 | Aug 29 07:30:59 AM UTC 24 | 10724212 ps | ||
| T168 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3642193798 | Aug 29 07:23:36 AM UTC 24 | Aug 29 07:31:00 AM UTC 24 | 2309677930 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.59711736 | Aug 29 07:30:58 AM UTC 24 | Aug 29 07:31:01 AM UTC 24 | 24644432 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.1849123043 | Aug 29 07:30:58 AM UTC 24 | Aug 29 07:31:01 AM UTC 24 | 6822939 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.2032248840 | Aug 29 07:30:59 AM UTC 24 | Aug 29 07:31:02 AM UTC 24 | 26225099 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.1505744372 | Aug 29 07:31:00 AM UTC 24 | Aug 29 07:31:03 AM UTC 24 | 17621261 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3069904613 | Aug 29 07:30:00 AM UTC 24 | Aug 29 07:31:04 AM UTC 24 | 1630737575 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.1306620767 | Aug 29 07:31:02 AM UTC 24 | Aug 29 07:31:05 AM UTC 24 | 8701887 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.3754318584 | Aug 29 07:31:02 AM UTC 24 | Aug 29 07:31:05 AM UTC 24 | 10253067 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.1135348729 | Aug 29 07:31:02 AM UTC 24 | Aug 29 07:31:05 AM UTC 24 | 24163366 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.73444376 | Aug 29 07:24:59 AM UTC 24 | Aug 29 07:31:06 AM UTC 24 | 15607853881 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.3847876086 | Aug 29 07:31:03 AM UTC 24 | Aug 29 07:31:06 AM UTC 24 | 8730419 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.991160084 | Aug 29 07:31:04 AM UTC 24 | Aug 29 07:31:07 AM UTC 24 | 6308513 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.3446581009 | Aug 29 07:31:05 AM UTC 24 | Aug 29 07:31:08 AM UTC 24 | 7757650 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.3323891913 | Aug 29 07:31:06 AM UTC 24 | Aug 29 07:31:09 AM UTC 24 | 18463081 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.4108552826 | Aug 29 07:31:06 AM UTC 24 | Aug 29 07:31:09 AM UTC 24 | 12315351 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.701184623 | Aug 29 07:31:06 AM UTC 24 | Aug 29 07:31:09 AM UTC 24 | 6499810 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.1736363359 | Aug 29 07:31:07 AM UTC 24 | Aug 29 07:31:10 AM UTC 24 | 24146881 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.3127085543 | Aug 29 07:31:07 AM UTC 24 | Aug 29 07:31:10 AM UTC 24 | 9954034 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.4175529948 | Aug 29 07:31:08 AM UTC 24 | Aug 29 07:31:11 AM UTC 24 | 26441069 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.3234609214 | Aug 29 07:31:09 AM UTC 24 | Aug 29 07:31:13 AM UTC 24 | 13092415 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.196053463 | Aug 29 07:31:10 AM UTC 24 | Aug 29 07:31:14 AM UTC 24 | 9783103 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.2678890748 | Aug 29 07:31:11 AM UTC 24 | Aug 29 07:31:14 AM UTC 24 | 14719981 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.178998047 | Aug 29 07:31:11 AM UTC 24 | Aug 29 07:31:14 AM UTC 24 | 7438415 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.580282844 | Aug 29 07:31:11 AM UTC 24 | Aug 29 07:31:14 AM UTC 24 | 9724627 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.103421413 | Aug 29 07:31:12 AM UTC 24 | Aug 29 07:31:15 AM UTC 24 | 18218250 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.2330348984 | Aug 29 07:31:13 AM UTC 24 | Aug 29 07:31:16 AM UTC 24 | 7521232 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.4045499526 | Aug 29 07:31:14 AM UTC 24 | Aug 29 07:31:17 AM UTC 24 | 15762207 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.3231872080 | Aug 29 07:31:15 AM UTC 24 | Aug 29 07:31:18 AM UTC 24 | 55953703 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.2810146595 | Aug 29 07:31:15 AM UTC 24 | Aug 29 07:31:18 AM UTC 24 | 6261882 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.3514598283 | Aug 29 07:31:15 AM UTC 24 | Aug 29 07:31:18 AM UTC 24 | 25362628 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2375327727 | Aug 29 07:30:12 AM UTC 24 | Aug 29 07:31:19 AM UTC 24 | 1373079249 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.2538354822 | Aug 29 07:31:16 AM UTC 24 | Aug 29 07:31:19 AM UTC 24 | 11395637 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.3596435378 | Aug 29 07:31:15 AM UTC 24 | Aug 29 07:31:19 AM UTC 24 | 24143959 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2574077166 | Aug 29 07:30:48 AM UTC 24 | Aug 29 07:31:20 AM UTC 24 | 720454829 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1897307200 | Aug 29 07:29:25 AM UTC 24 | Aug 29 07:31:24 AM UTC 24 | 1493060073 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2996742885 | Aug 29 07:30:31 AM UTC 24 | Aug 29 07:31:27 AM UTC 24 | 5962604956 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.983945498 | Aug 29 07:28:14 AM UTC 24 | Aug 29 07:31:32 AM UTC 24 | 3913879875 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1882996341 | Aug 29 07:22:47 AM UTC 24 | Aug 29 07:31:47 AM UTC 24 | 7891520881 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1849549661 | Aug 29 07:30:03 AM UTC 24 | Aug 29 07:32:06 AM UTC 24 | 1480005818 ps | ||
| T174 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2679863118 | Aug 29 07:29:20 AM UTC 24 | Aug 29 07:32:13 AM UTC 24 | 8777421544 ps | ||
| T167 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1878542454 | Aug 29 07:29:53 AM UTC 24 | Aug 29 07:32:14 AM UTC 24 | 3890957745 ps | ||
| T182 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.985700782 | Aug 29 07:24:27 AM UTC 24 | Aug 29 07:32:32 AM UTC 24 | 4503209242 ps | ||
| T178 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3804729259 | Aug 29 07:26:35 AM UTC 24 | Aug 29 07:32:33 AM UTC 24 | 9967969065 ps | ||
| T180 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3542375840 | Aug 29 07:28:31 AM UTC 24 | Aug 29 07:32:45 AM UTC 24 | 5286527898 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1735210530 | Aug 29 07:29:03 AM UTC 24 | Aug 29 07:32:54 AM UTC 24 | 6242634994 ps | ||
| T175 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1289630146 | Aug 29 07:29:35 AM UTC 24 | Aug 29 07:32:56 AM UTC 24 | 1639506959 ps | ||
| T169 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.330835027 | Aug 29 07:26:08 AM UTC 24 | Aug 29 07:32:57 AM UTC 24 | 3255434894 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2769783905 | Aug 29 07:22:23 AM UTC 24 | Aug 29 07:33:28 AM UTC 24 | 25904246680 ps | ||
| T179 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3417658329 | Aug 29 07:30:25 AM UTC 24 | Aug 29 07:33:34 AM UTC 24 | 2195381433 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1273517032 | Aug 29 07:27:41 AM UTC 24 | Aug 29 07:33:37 AM UTC 24 | 7941430370 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2746109388 | Aug 29 07:28:14 AM UTC 24 | Aug 29 07:34:21 AM UTC 24 | 4171071807 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3286425074 | Aug 29 07:29:53 AM UTC 24 | Aug 29 07:35:44 AM UTC 24 | 2268508173 ps | ||
| T171 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3623844350 | Aug 29 07:25:59 AM UTC 24 | Aug 29 07:37:46 AM UTC 24 | 4583873002 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.491364269 | Aug 29 07:24:58 AM UTC 24 | Aug 29 07:37:58 AM UTC 24 | 9094191316 ps | ||
| T386 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2111254941 | Aug 29 07:29:33 AM UTC 24 | Aug 29 07:38:00 AM UTC 24 | 6287324623 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3600369283 | Aug 29 07:26:59 AM UTC 24 | Aug 29 07:38:01 AM UTC 24 | 36121630477 ps | ||
| T385 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1233604736 | Aug 29 07:29:00 AM UTC 24 | Aug 29 07:38:05 AM UTC 24 | 43487023156 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2605964565 | Aug 29 07:27:41 AM UTC 24 | Aug 29 07:38:50 AM UTC 24 | 19248159939 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2519604935 | Aug 29 07:30:02 AM UTC 24 | Aug 29 07:39:00 AM UTC 24 | 26789091107 ps | ||
| T177 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.138380636 | Aug 29 07:30:18 AM UTC 24 | Aug 29 07:42:24 AM UTC 24 | 31851258602 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3754961842 | Aug 29 07:24:02 AM UTC 24 | Aug 29 07:42:54 AM UTC 24 | 42015137125 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1005936239 | Aug 29 07:29:20 AM UTC 24 | Aug 29 07:48:37 AM UTC 24 | 24526488197 ps | ||
| T387 | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2496307063 | Aug 29 07:28:31 AM UTC 24 | Aug 29 07:50:15 AM UTC 24 | 27463784236 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_classes.2992042849 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 309440485 ps |
| CPU time | 41.06 seconds |
| Started | Aug 29 07:38:15 AM UTC 24 |
| Finished | Aug 29 07:38:58 AM UTC 24 |
| Peak memory | 262932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992042849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2992042849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/0.alert_handler_sec_cm.649392911 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 941911607 ps |
| CPU time | 37.35 seconds |
| Started | Aug 29 07:38:18 AM UTC 24 |
| Finished | Aug 29 07:38:57 AM UTC 24 |
| Peak memory | 295408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649392911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_h andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.649392911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all_with_rand_reset.2460833584 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 15199993337 ps |
| CPU time | 248.7 seconds |
| Started | Aug 29 07:39:14 AM UTC 24 |
| Finished | Aug 29 07:43:26 AM UTC 24 |
| Peak memory | 279808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2460833584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.al ert_handler_stress_all_with_rand_reset.2460833584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy_stress.2577681051 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 401810716 ps |
| CPU time | 29.54 seconds |
| Started | Aug 29 07:38:17 AM UTC 24 |
| Finished | Aug 29 07:38:48 AM UTC 24 |
| Peak memory | 262920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577681051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2577681051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1608754118 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 500091568 ps |
| CPU time | 33.83 seconds |
| Started | Aug 29 07:22:28 AM UTC 24 |
| Finished | Aug 29 07:23:03 AM UTC 24 |
| Peak memory | 250392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608754118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1608754118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/1.alert_handler_sig_int_fail.2972980874 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 717777075 ps |
| CPU time | 30.31 seconds |
| Started | Aug 29 07:38:43 AM UTC 24 |
| Finished | Aug 29 07:39:15 AM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972980874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2972980874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all_with_rand_reset.2455253231 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3582069829 ps |
| CPU time | 325.45 seconds |
| Started | Aug 29 07:48:11 AM UTC 24 |
| Finished | Aug 29 07:53:41 AM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2455253231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.al ert_handler_stress_all_with_rand_reset.2455253231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all_with_rand_reset.1150747375 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5062977877 ps |
| CPU time | 638.77 seconds |
| Started | Aug 29 07:45:54 AM UTC 24 |
| Finished | Aug 29 07:56:41 AM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1150747375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.al ert_handler_stress_all_with_rand_reset.1150747375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg.2890332629 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 226444755357 ps |
| CPU time | 2729.05 seconds |
| Started | Aug 29 07:40:07 AM UTC 24 |
| Finished | Aug 29 08:26:07 AM UTC 24 |
| Peak memory | 302208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890332629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2890332629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all.3034084336 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 78116802123 ps |
| CPU time | 1364.69 seconds |
| Started | Aug 29 07:40:41 AM UTC 24 |
| Finished | Aug 29 08:03:42 AM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034084336 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all.3034084336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_intr_timeout.2320035358 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3402163947 ps |
| CPU time | 77.64 seconds |
| Started | Aug 29 07:38:31 AM UTC 24 |
| Finished | Aug 29 07:39:50 AM UTC 24 |
| Peak memory | 262964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320035358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2320035358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1623986450 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 8699545355 ps |
| CPU time | 292.15 seconds |
| Started | Aug 29 07:24:29 AM UTC 24 |
| Finished | Aug 29 07:29:25 AM UTC 24 |
| Peak memory | 279452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623986450 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.1623986450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/42.alert_handler_entropy.241707518 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 43795759593 ps |
| CPU time | 3134.12 seconds |
| Started | Aug 29 09:01:43 AM UTC 24 |
| Finished | Aug 29 09:54:34 AM UTC 24 |
| Peak memory | 303568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241707518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.241707518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/42.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1735210530 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 6242634994 ps |
| CPU time | 227.35 seconds |
| Started | Aug 29 07:29:03 AM UTC 24 |
| Finished | Aug 29 07:32:54 AM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735210530 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.1735210530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.491364269 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 9094191316 ps |
| CPU time | 769.47 seconds |
| Started | Aug 29 07:24:58 AM UTC 24 |
| Finished | Aug 29 07:37:58 AM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491364269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow _reg_errors_with_csr_rw.491364269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/26.alert_handler_ping_timeout.3169409488 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 9041984674 ps |
| CPU time | 485.16 seconds |
| Started | Aug 29 08:27:44 AM UTC 24 |
| Finished | Aug 29 08:35:55 AM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169409488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3169409488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg_stub_clk.2129010046 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 113472017671 ps |
| CPU time | 1876.78 seconds |
| Started | Aug 29 07:45:37 AM UTC 24 |
| Finished | Aug 29 08:17:16 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129010046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2129010046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all.3601008857 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 156731522063 ps |
| CPU time | 3214.92 seconds |
| Started | Aug 29 07:43:57 AM UTC 24 |
| Finished | Aug 29 08:38:09 AM UTC 24 |
| Peak memory | 301956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601008857 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all.3601008857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/2.alert_handler_ping_timeout.3750225025 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 53285573940 ps |
| CPU time | 554.15 seconds |
| Started | Aug 29 07:39:53 AM UTC 24 |
| Finished | Aug 29 07:49:14 AM UTC 24 |
| Peak memory | 263300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750225025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3750225025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.4144894726 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 4702501986 ps |
| CPU time | 324.2 seconds |
| Started | Aug 29 07:24:05 AM UTC 24 |
| Finished | Aug 29 07:29:34 AM UTC 24 |
| Peak memory | 285596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144894726 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.4144894726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg.4233217190 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 38021896461 ps |
| CPU time | 2241.31 seconds |
| Started | Aug 29 07:47:16 AM UTC 24 |
| Finished | Aug 29 08:25:02 AM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233217190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.4233217190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all_with_rand_reset.593025813 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1609422287 ps |
| CPU time | 141.29 seconds |
| Started | Aug 29 07:40:43 AM UTC 24 |
| Finished | Aug 29 07:43:07 AM UTC 24 |
| Peak memory | 279420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=593025813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.ale rt_handler_stress_all_with_rand_reset.593025813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy.326744013 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 70034887070 ps |
| CPU time | 1582.74 seconds |
| Started | Aug 29 07:45:08 AM UTC 24 |
| Finished | Aug 29 08:11:49 AM UTC 24 |
| Peak memory | 295740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326744013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.326744013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_intr_test.787102097 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 12241164 ps |
| CPU time | 2.06 seconds |
| Started | Aug 29 07:24:46 AM UTC 24 |
| Finished | Aug 29 07:24:49 AM UTC 24 |
| Peak memory | 250464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787102097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.787102097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1005936239 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 24526488197 ps |
| CPU time | 1143.47 seconds |
| Started | Aug 29 07:29:20 AM UTC 24 |
| Finished | Aug 29 07:48:37 AM UTC 24 |
| Peak memory | 279452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005936239 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shad ow_reg_errors_with_csr_rw.1005936239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_intg_err.446250607 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1006184031 ps |
| CPU time | 35.42 seconds |
| Started | Aug 29 07:22:41 AM UTC 24 |
| Finished | Aug 29 07:23:18 AM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446250607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.446250607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg.1079973192 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 162860901274 ps |
| CPU time | 1709.9 seconds |
| Started | Aug 29 08:14:28 AM UTC 24 |
| Finished | Aug 29 08:43:19 AM UTC 24 |
| Peak memory | 285700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079973192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1079973192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/20.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/8.alert_handler_ping_timeout.3806715070 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 29000094600 ps |
| CPU time | 560.11 seconds |
| Started | Aug 29 07:50:48 AM UTC 24 |
| Finished | Aug 29 08:00:15 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806715070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3806715070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1068663300 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 8804175651 ps |
| CPU time | 336.64 seconds |
| Started | Aug 29 07:23:04 AM UTC 24 |
| Finished | Aug 29 07:28:45 AM UTC 24 |
| Peak memory | 285596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068663300 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.1068663300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all.33583291 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 88212634888 ps |
| CPU time | 506.21 seconds |
| Started | Aug 29 07:42:47 AM UTC 24 |
| Finished | Aug 29 07:51:19 AM UTC 24 |
| Peak memory | 269184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33583291 -assert nopostproc +UVM_TES TNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all.33583291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg.2904705330 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 29864065479 ps |
| CPU time | 1905.29 seconds |
| Started | Aug 29 08:07:53 AM UTC 24 |
| Finished | Aug 29 08:40:01 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904705330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2904705330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all_with_rand_reset.4071412748 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6978959047 ps |
| CPU time | 142.6 seconds |
| Started | Aug 29 07:38:17 AM UTC 24 |
| Finished | Aug 29 07:40:42 AM UTC 24 |
| Peak memory | 279480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4071412748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.al ert_handler_stress_all_with_rand_reset.4071412748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/0.alert_handler_ping_timeout.886507686 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 44616025580 ps |
| CPU time | 578.1 seconds |
| Started | Aug 29 07:38:17 AM UTC 24 |
| Finished | Aug 29 07:48:02 AM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886507686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.886507686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all_with_rand_reset.3358494382 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 3764899731 ps |
| CPU time | 530.34 seconds |
| Started | Aug 29 08:24:58 AM UTC 24 |
| Finished | Aug 29 08:33:56 AM UTC 24 |
| Peak memory | 283568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3358494382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.a lert_handler_stress_all_with_rand_reset.3358494382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3600369283 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 36121630477 ps |
| CPU time | 654.26 seconds |
| Started | Aug 29 07:26:59 AM UTC 24 |
| Finished | Aug 29 07:38:01 AM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600369283 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shad ow_reg_errors_with_csr_rw.3600369283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_rw.989877424 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 229914158 ps |
| CPU time | 13.57 seconds |
| Started | Aug 29 07:23:21 AM UTC 24 |
| Finished | Aug 29 07:23:36 AM UTC 24 |
| Peak memory | 250460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989877424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.989877424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.138380636 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 31851258602 ps |
| CPU time | 716.65 seconds |
| Started | Aug 29 07:30:18 AM UTC 24 |
| Finished | Aug 29 07:42:24 AM UTC 24 |
| Peak memory | 279460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138380636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shado w_reg_errors_with_csr_rw.138380636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/14.alert_handler_ping_timeout.3653129428 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 38241317528 ps |
| CPU time | 533.19 seconds |
| Started | Aug 29 07:59:53 AM UTC 24 |
| Finished | Aug 29 08:08:53 AM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653129428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3653129428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all_with_rand_reset.669962777 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 4832469481 ps |
| CPU time | 364.17 seconds |
| Started | Aug 29 08:23:04 AM UTC 24 |
| Finished | Aug 29 08:29:14 AM UTC 24 |
| Peak memory | 281596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=669962777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.al ert_handler_stress_all_with_rand_reset.669962777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/23.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg.3516226205 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 76977486908 ps |
| CPU time | 2537.07 seconds |
| Started | Aug 29 08:37:24 AM UTC 24 |
| Finished | Aug 29 09:20:11 AM UTC 24 |
| Peak memory | 305004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516226205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3516226205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/29.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all.1794658996 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 52501166554 ps |
| CPU time | 1357.38 seconds |
| Started | Aug 29 08:31:06 AM UTC 24 |
| Finished | Aug 29 08:54:00 AM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794658996 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all.1794658996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/27.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/33.alert_handler_ping_timeout.1703365754 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 6731480244 ps |
| CPU time | 369.45 seconds |
| Started | Aug 29 08:45:13 AM UTC 24 |
| Finished | Aug 29 08:51:28 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703365754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1703365754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2327011492 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 2024405913 ps |
| CPU time | 42.71 seconds |
| Started | Aug 29 07:22:36 AM UTC 24 |
| Finished | Aug 29 07:23:20 AM UTC 24 |
| Peak memory | 260772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327011492 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.2327011492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_intr_test.3034864245 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 21995056 ps |
| CPU time | 2.26 seconds |
| Started | Aug 29 07:27:25 AM UTC 24 |
| Finished | Aug 29 07:27:28 AM UTC 24 |
| Peak memory | 250468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034864245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3034864245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/12.alert_handler_ping_timeout.3235010609 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 51949266247 ps |
| CPU time | 355.5 seconds |
| Started | Aug 29 07:57:01 AM UTC 24 |
| Finished | Aug 29 08:03:01 AM UTC 24 |
| Peak memory | 269192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235010609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3235010609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg.312856545 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 44283745848 ps |
| CPU time | 883.27 seconds |
| Started | Aug 29 07:42:16 AM UTC 24 |
| Finished | Aug 29 07:57:10 AM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312856545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.312856545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all.1113421546 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 173784960059 ps |
| CPU time | 2721.92 seconds |
| Started | Aug 29 09:12:56 AM UTC 24 |
| Finished | Aug 29 09:58:49 AM UTC 24 |
| Peak memory | 302560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113421546 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all.1113421546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/48.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all.1026972140 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 65700840872 ps |
| CPU time | 3783.63 seconds |
| Started | Aug 29 09:16:04 AM UTC 24 |
| Finished | Aug 29 10:19:51 AM UTC 24 |
| Peak memory | 314920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026972140 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all.1026972140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/49.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2496307063 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 27463784236 ps |
| CPU time | 1288.22 seconds |
| Started | Aug 29 07:28:31 AM UTC 24 |
| Finished | Aug 29 07:50:15 AM UTC 24 |
| Peak memory | 279528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496307063 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shad ow_reg_errors_with_csr_rw.2496307063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2679863118 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 8777421544 ps |
| CPU time | 170.05 seconds |
| Started | Aug 29 07:29:20 AM UTC 24 |
| Finished | Aug 29 07:32:13 AM UTC 24 |
| Peak memory | 279592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679863118 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.2679863118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/11.alert_handler_sig_int_fail.1864504278 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 634111815 ps |
| CPU time | 37.24 seconds |
| Started | Aug 29 07:56:01 AM UTC 24 |
| Finished | Aug 29 07:56:40 AM UTC 24 |
| Peak memory | 269432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864504278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1864504278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1289630146 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1639506959 ps |
| CPU time | 197.95 seconds |
| Started | Aug 29 07:29:35 AM UTC 24 |
| Finished | Aug 29 07:32:56 AM UTC 24 |
| Peak memory | 279324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289630146 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.1289630146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all_with_rand_reset.1269756866 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1850398421 ps |
| CPU time | 267.86 seconds |
| Started | Aug 29 07:44:05 AM UTC 24 |
| Finished | Aug 29 07:48:37 AM UTC 24 |
| Peak memory | 279488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1269756866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.al ert_handler_stress_all_with_rand_reset.1269756866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg.3252862394 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 29209176392 ps |
| CPU time | 1806.48 seconds |
| Started | Aug 29 07:38:17 AM UTC 24 |
| Finished | Aug 29 08:08:44 AM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252862394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3252862394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_classes.1105378118 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1889598577 ps |
| CPU time | 43.65 seconds |
| Started | Aug 29 07:53:49 AM UTC 24 |
| Finished | Aug 29 07:54:34 AM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105378118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1105378118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/32.alert_handler_ping_timeout.1402419059 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 18249317919 ps |
| CPU time | 498.64 seconds |
| Started | Aug 29 08:43:24 AM UTC 24 |
| Finished | Aug 29 08:51:50 AM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402419059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1402419059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all_with_rand_reset.1398091947 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 5203743142 ps |
| CPU time | 384.91 seconds |
| Started | Aug 29 08:46:01 AM UTC 24 |
| Finished | Aug 29 08:52:32 AM UTC 24 |
| Peak memory | 279548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1398091947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.a lert_handler_stress_all_with_rand_reset.1398091947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/33.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all_with_rand_reset.999362628 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 16017813551 ps |
| CPU time | 451.49 seconds |
| Started | Aug 29 08:58:15 AM UTC 24 |
| Finished | Aug 29 09:05:53 AM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=999362628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.al ert_handler_stress_all_with_rand_reset.999362628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg.3090434038 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 185595881710 ps |
| CPU time | 1858.7 seconds |
| Started | Aug 29 09:15:50 AM UTC 24 |
| Finished | Aug 29 09:47:11 AM UTC 24 |
| Peak memory | 285476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090434038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3090434038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/49.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_alert_accum.2032709781 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 474951155 ps |
| CPU time | 42.12 seconds |
| Started | Aug 29 07:39:48 AM UTC 24 |
| Finished | Aug 29 07:40:32 AM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032709781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2032709781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2746109388 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 4171071807 ps |
| CPU time | 361.89 seconds |
| Started | Aug 29 07:28:14 AM UTC 24 |
| Finished | Aug 29 07:34:21 AM UTC 24 |
| Peak memory | 283688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746109388 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shad ow_reg_errors_with_csr_rw.2746109388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3822175757 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 54988901 ps |
| CPU time | 3.43 seconds |
| Started | Aug 29 07:29:55 AM UTC 24 |
| Finished | Aug 29 07:29:59 AM UTC 24 |
| Peak memory | 250536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822175757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3822175757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/0.alert_handler_alert_accum_saturation.3894731528 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 165378401 ps |
| CPU time | 6.19 seconds |
| Started | Aug 29 07:38:17 AM UTC 24 |
| Finished | Aug 29 07:38:24 AM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894731528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3894731528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/1.alert_handler_alert_accum_saturation.2705083113 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 19596748 ps |
| CPU time | 3.5 seconds |
| Started | Aug 29 07:39:08 AM UTC 24 |
| Finished | Aug 29 07:39:13 AM UTC 24 |
| Peak memory | 263504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705083113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2705083113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/10.alert_handler_alert_accum_saturation.3457162568 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 119289097 ps |
| CPU time | 5.12 seconds |
| Started | Aug 29 07:55:01 AM UTC 24 |
| Finished | Aug 29 07:55:07 AM UTC 24 |
| Peak memory | 263172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457162568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3457162568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/14.alert_handler_alert_accum_saturation.857114924 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 41438064 ps |
| CPU time | 5.58 seconds |
| Started | Aug 29 08:01:26 AM UTC 24 |
| Finished | Aug 29 08:01:33 AM UTC 24 |
| Peak memory | 263504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857114924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.857114924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_intr_test.3895123264 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 7918118 ps |
| CPU time | 2.39 seconds |
| Started | Aug 29 07:29:08 AM UTC 24 |
| Finished | Aug 29 07:29:12 AM UTC 24 |
| Peak memory | 248284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895123264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3895123264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/14.alert_handler_sig_int_fail.2504016859 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2902169839 ps |
| CPU time | 69.74 seconds |
| Started | Aug 29 07:59:34 AM UTC 24 |
| Finished | Aug 29 08:00:46 AM UTC 24 |
| Peak memory | 269104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504016859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2504016859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/20.alert_handler_ping_timeout.3170131610 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 12706907324 ps |
| CPU time | 577.34 seconds |
| Started | Aug 29 08:14:27 AM UTC 24 |
| Finished | Aug 29 08:24:12 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170131610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3170131610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all.2183452547 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 81766253241 ps |
| CPU time | 1403.04 seconds |
| Started | Aug 29 08:56:28 AM UTC 24 |
| Finished | Aug 29 09:20:07 AM UTC 24 |
| Peak memory | 312124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183452547 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all.2183452547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/39.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all.1620347176 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 226796087884 ps |
| CPU time | 2216.59 seconds |
| Started | Aug 29 09:07:57 AM UTC 24 |
| Finished | Aug 29 09:45:20 AM UTC 24 |
| Peak memory | 316224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620347176 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all.1620347176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/45.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/5.alert_handler_ping_timeout.2478430201 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 29268295736 ps |
| CPU time | 646.19 seconds |
| Started | Aug 29 07:45:12 AM UTC 24 |
| Finished | Aug 29 07:56:06 AM UTC 24 |
| Peak memory | 262968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478430201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2478430201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3542375840 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 5286527898 ps |
| CPU time | 249.73 seconds |
| Started | Aug 29 07:28:31 AM UTC 24 |
| Finished | Aug 29 07:32:45 AM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542375840 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.3542375840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3092964762 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 70779560 ps |
| CPU time | 6.63 seconds |
| Started | Aug 29 07:22:23 AM UTC 24 |
| Finished | Aug 29 07:22:31 AM UTC 24 |
| Peak memory | 262344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092964762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3092964762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1871766724 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 2149304870 ps |
| CPU time | 458.6 seconds |
| Started | Aug 29 07:23:02 AM UTC 24 |
| Finished | Aug 29 07:30:47 AM UTC 24 |
| Peak memory | 279468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871766724 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shado w_reg_errors_with_csr_rw.1871766724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2089448713 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 317948572 ps |
| CPU time | 51.66 seconds |
| Started | Aug 29 07:27:08 AM UTC 24 |
| Finished | Aug 29 07:28:01 AM UTC 24 |
| Peak memory | 252584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089448713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2089448713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_intr_timeout.2499352854 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1128775339 ps |
| CPU time | 33.17 seconds |
| Started | Aug 29 07:41:33 AM UTC 24 |
| Finished | Aug 29 07:42:08 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499352854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2499352854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3623844350 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 4583873002 ps |
| CPU time | 697.22 seconds |
| Started | Aug 29 07:25:59 AM UTC 24 |
| Finished | Aug 29 07:37:46 AM UTC 24 |
| Peak memory | 279532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623844350 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shado w_reg_errors_with_csr_rw.3623844350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/0.alert_handler_smoke.1459872631 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1132083267 ps |
| CPU time | 50.71 seconds |
| Started | Aug 29 07:38:15 AM UTC 24 |
| Finished | Aug 29 07:39:08 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459872631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1459872631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy.1950120662 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 35722465097 ps |
| CPU time | 2560.33 seconds |
| Started | Aug 29 07:38:44 AM UTC 24 |
| Finished | Aug 29 08:21:54 AM UTC 24 |
| Peak memory | 295812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950120662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1950120662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg.2667963099 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 36166443308 ps |
| CPU time | 982.97 seconds |
| Started | Aug 29 07:38:51 AM UTC 24 |
| Finished | Aug 29 07:55:26 AM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667963099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2667963099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg.2352360768 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 61087025863 ps |
| CPU time | 1336.28 seconds |
| Started | Aug 29 07:56:08 AM UTC 24 |
| Finished | Aug 29 08:18:40 AM UTC 24 |
| Peak memory | 301952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352360768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2352360768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg.1025392917 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 24424495452 ps |
| CPU time | 1949.02 seconds |
| Started | Aug 29 08:00:16 AM UTC 24 |
| Finished | Aug 29 08:33:09 AM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025392917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1025392917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/16.alert_handler_sig_int_fail.3186375187 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 162893024 ps |
| CPU time | 28.8 seconds |
| Started | Aug 29 08:04:01 AM UTC 24 |
| Finished | Aug 29 08:04:31 AM UTC 24 |
| Peak memory | 263032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186375187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3186375187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg.2357287564 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 43050964496 ps |
| CPU time | 2410.54 seconds |
| Started | Aug 29 08:12:37 AM UTC 24 |
| Finished | Aug 29 08:53:13 AM UTC 24 |
| Peak memory | 301888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357287564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2357287564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/22.alert_handler_sig_int_fail.58368845 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 152591647 ps |
| CPU time | 30.01 seconds |
| Started | Aug 29 08:18:53 AM UTC 24 |
| Finished | Aug 29 08:19:24 AM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58368845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig _int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.58368845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/28.alert_handler_sig_int_fail.495636116 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 526741750 ps |
| CPU time | 42.78 seconds |
| Started | Aug 29 08:33:58 AM UTC 24 |
| Finished | Aug 29 08:34:42 AM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495636116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.495636116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all_with_rand_reset.428534571 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 4197221055 ps |
| CPU time | 394.69 seconds |
| Started | Aug 29 08:35:06 AM UTC 24 |
| Finished | Aug 29 08:41:46 AM UTC 24 |
| Peak memory | 279476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=428534571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.al ert_handler_stress_all_with_rand_reset.428534571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/28.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/30.alert_handler_sig_int_fail.480760232 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 366058978 ps |
| CPU time | 7.75 seconds |
| Started | Aug 29 08:38:44 AM UTC 24 |
| Finished | Aug 29 08:38:53 AM UTC 24 |
| Peak memory | 252696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480760232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.480760232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/33.alert_handler_sig_int_fail.3763815395 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 260284847 ps |
| CPU time | 41.97 seconds |
| Started | Aug 29 08:45:02 AM UTC 24 |
| Finished | Aug 29 08:45:46 AM UTC 24 |
| Peak memory | 269036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763815395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3763815395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg_stub_clk.379344110 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 38042834966 ps |
| CPU time | 3201.14 seconds |
| Started | Aug 29 08:03:02 AM UTC 24 |
| Finished | Aug 29 08:57:02 AM UTC 24 |
| Peak memory | 304616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379344110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.379344110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.811867915 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 66067752 ps |
| CPU time | 3.5 seconds |
| Started | Aug 29 07:29:37 AM UTC 24 |
| Finished | Aug 29 07:29:41 AM UTC 24 |
| Peak memory | 250536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811867915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.811867915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1878542454 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 3890957745 ps |
| CPU time | 138.68 seconds |
| Started | Aug 29 07:29:53 AM UTC 24 |
| Finished | Aug 29 07:32:14 AM UTC 24 |
| Peak memory | 281504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878542454 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.1878542454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3804729259 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 9967969065 ps |
| CPU time | 352.65 seconds |
| Started | Aug 29 07:26:35 AM UTC 24 |
| Finished | Aug 29 07:32:33 AM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804729259 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shado w_reg_errors_with_csr_rw.3804729259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2474772381 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 4976734435 ps |
| CPU time | 136.52 seconds |
| Started | Aug 29 07:24:46 AM UTC 24 |
| Finished | Aug 29 07:27:05 AM UTC 24 |
| Peak memory | 260768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474772381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2474772381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1897307200 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1493060073 ps |
| CPU time | 116.61 seconds |
| Started | Aug 29 07:29:25 AM UTC 24 |
| Finished | Aug 29 07:31:24 AM UTC 24 |
| Peak memory | 252448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897307200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1897307200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2996742885 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 5962604956 ps |
| CPU time | 54.17 seconds |
| Started | Aug 29 07:30:31 AM UTC 24 |
| Finished | Aug 29 07:31:27 AM UTC 24 |
| Peak memory | 250600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996742885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2996742885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2112914538 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 942759524 ps |
| CPU time | 76.34 seconds |
| Started | Aug 29 07:28:17 AM UTC 24 |
| Finished | Aug 29 07:29:36 AM UTC 24 |
| Peak memory | 252520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112914538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2112914538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3994749250 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 321187953 ps |
| CPU time | 12.62 seconds |
| Started | Aug 29 07:28:48 AM UTC 24 |
| Finished | Aug 29 07:29:02 AM UTC 24 |
| Peak memory | 250400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994749250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3994749250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1496136674 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 114452998 ps |
| CPU time | 6.78 seconds |
| Started | Aug 29 07:29:04 AM UTC 24 |
| Finished | Aug 29 07:29:12 AM UTC 24 |
| Peak memory | 250400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496136674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1496136674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2375327727 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1373079249 ps |
| CPU time | 65.71 seconds |
| Started | Aug 29 07:30:12 AM UTC 24 |
| Finished | Aug 29 07:31:19 AM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375327727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2375327727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3583628957 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 219704114 ps |
| CPU time | 37.48 seconds |
| Started | Aug 29 07:23:15 AM UTC 24 |
| Finished | Aug 29 07:23:54 AM UTC 24 |
| Peak memory | 252436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583628957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3583628957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_intg_err.799483504 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 54785644 ps |
| CPU time | 3.46 seconds |
| Started | Aug 29 07:23:44 AM UTC 24 |
| Finished | Aug 29 07:23:49 AM UTC 24 |
| Peak memory | 252516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799483504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.799483504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3547746116 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 137113741 ps |
| CPU time | 10.89 seconds |
| Started | Aug 29 07:24:14 AM UTC 24 |
| Finished | Aug 29 07:24:26 AM UTC 24 |
| Peak memory | 250388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547746116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3547746116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2586563892 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 612557446 ps |
| CPU time | 35.17 seconds |
| Started | Aug 29 07:25:15 AM UTC 24 |
| Finished | Aug 29 07:25:51 AM UTC 24 |
| Peak memory | 260768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586563892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2586563892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1533536264 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 98971518 ps |
| CPU time | 4.46 seconds |
| Started | Aug 29 07:26:12 AM UTC 24 |
| Finished | Aug 29 07:26:18 AM UTC 24 |
| Peak memory | 250388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533536264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1533536264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1616639906 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 53839315 ps |
| CPU time | 3.48 seconds |
| Started | Aug 29 07:26:41 AM UTC 24 |
| Finished | Aug 29 07:26:46 AM UTC 24 |
| Peak memory | 250532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616639906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1616639906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_alerts.4171358159 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 825326239 ps |
| CPU time | 74.04 seconds |
| Started | Aug 29 07:39:26 AM UTC 24 |
| Finished | Aug 29 07:40:42 AM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171358159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.4171358159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_intr_timeout.1357992598 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 328283171 ps |
| CPU time | 46.41 seconds |
| Started | Aug 29 07:43:10 AM UTC 24 |
| Finished | Aug 29 07:43:58 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357992598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1357992598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3369993978 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 7273085710 ps |
| CPU time | 312.34 seconds |
| Started | Aug 29 07:22:23 AM UTC 24 |
| Finished | Aug 29 07:27:40 AM UTC 24 |
| Peak memory | 252500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369993978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3369993978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2834747963 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 5764033105 ps |
| CPU time | 386.65 seconds |
| Started | Aug 29 07:22:23 AM UTC 24 |
| Finished | Aug 29 07:28:55 AM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834747963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2834747963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1585560179 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 148405075 ps |
| CPU time | 9.64 seconds |
| Started | Aug 29 07:22:26 AM UTC 24 |
| Finished | Aug 29 07:22:37 AM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585560179 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_ rw_with_rand_reset.1585560179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_rw.3424335448 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 34096137 ps |
| CPU time | 5.64 seconds |
| Started | Aug 29 07:22:23 AM UTC 24 |
| Finished | Aug 29 07:22:30 AM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424335448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3424335448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_intr_test.2302845346 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 9091492 ps |
| CPU time | 2.06 seconds |
| Started | Aug 29 07:22:23 AM UTC 24 |
| Finished | Aug 29 07:22:26 AM UTC 24 |
| Peak memory | 250392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302845346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2302845346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2655579291 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 256092700 ps |
| CPU time | 28.33 seconds |
| Started | Aug 29 07:22:26 AM UTC 24 |
| Finished | Aug 29 07:22:56 AM UTC 24 |
| Peak memory | 260628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655579291 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.2655579291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3335978368 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 13661899821 ps |
| CPU time | 394.55 seconds |
| Started | Aug 29 07:22:23 AM UTC 24 |
| Finished | Aug 29 07:29:03 AM UTC 24 |
| Peak memory | 279628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335978368 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.3335978368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2769783905 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 25904246680 ps |
| CPU time | 656.76 seconds |
| Started | Aug 29 07:22:23 AM UTC 24 |
| Finished | Aug 29 07:33:28 AM UTC 24 |
| Peak memory | 283692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769783905 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shado w_reg_errors_with_csr_rw.2769783905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_errors.2569849704 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 379644348 ps |
| CPU time | 14.24 seconds |
| Started | Aug 29 07:22:23 AM UTC 24 |
| Finished | Aug 29 07:22:38 AM UTC 24 |
| Peak memory | 262880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569849704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2569849704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2611449133 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 46306734 ps |
| CPU time | 4.06 seconds |
| Started | Aug 29 07:22:23 AM UTC 24 |
| Finished | Aug 29 07:22:28 AM UTC 24 |
| Peak memory | 250528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611449133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2611449133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1098711179 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 12746625894 ps |
| CPU time | 198.37 seconds |
| Started | Aug 29 07:22:36 AM UTC 24 |
| Finished | Aug 29 07:25:57 AM UTC 24 |
| Peak memory | 250452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098711179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1098711179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3429810928 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 25620268838 ps |
| CPU time | 406.57 seconds |
| Started | Aug 29 07:22:33 AM UTC 24 |
| Finished | Aug 29 07:29:25 AM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429810928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3429810928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2501516686 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 256602195 ps |
| CPU time | 9.19 seconds |
| Started | Aug 29 07:22:31 AM UTC 24 |
| Finished | Aug 29 07:22:41 AM UTC 24 |
| Peak memory | 262616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501516686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2501516686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.68023462 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 170705944 ps |
| CPU time | 17.34 seconds |
| Started | Aug 29 07:22:37 AM UTC 24 |
| Finished | Aug 29 07:22:55 AM UTC 24 |
| Peak memory | 254624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68023462 -assert nop ostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_rw _with_rand_reset.68023462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_rw.172372954 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 33911280 ps |
| CPU time | 8.86 seconds |
| Started | Aug 29 07:22:32 AM UTC 24 |
| Finished | Aug 29 07:22:42 AM UTC 24 |
| Peak memory | 250336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172372954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.172372954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_intr_test.2271294756 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 68844385 ps |
| CPU time | 2.42 seconds |
| Started | Aug 29 07:22:29 AM UTC 24 |
| Finished | Aug 29 07:22:32 AM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271294756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2271294756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2930436984 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 5660370881 ps |
| CPU time | 246.99 seconds |
| Started | Aug 29 07:22:26 AM UTC 24 |
| Finished | Aug 29 07:26:37 AM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930436984 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.2930436984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2968790379 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 13791077488 ps |
| CPU time | 440.32 seconds |
| Started | Aug 29 07:22:26 AM UTC 24 |
| Finished | Aug 29 07:29:53 AM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968790379 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shado w_reg_errors_with_csr_rw.2968790379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_errors.1997732095 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 65878573 ps |
| CPU time | 5.84 seconds |
| Started | Aug 29 07:22:26 AM UTC 24 |
| Finished | Aug 29 07:22:33 AM UTC 24 |
| Peak memory | 262884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997732095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1997732095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.352447161 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 64205588 ps |
| CPU time | 14.08 seconds |
| Started | Aug 29 07:27:38 AM UTC 24 |
| Finished | Aug 29 07:27:53 AM UTC 24 |
| Peak memory | 254556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352447161 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_mem_ rw_with_rand_reset.352447161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_rw.3972021472 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 51416393 ps |
| CPU time | 7.53 seconds |
| Started | Aug 29 07:27:29 AM UTC 24 |
| Finished | Aug 29 07:27:38 AM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972021472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3972021472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3545906641 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 5789374755 ps |
| CPU time | 36.16 seconds |
| Started | Aug 29 07:27:36 AM UTC 24 |
| Finished | Aug 29 07:28:14 AM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545906641 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outstanding.3545906641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2793877489 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2296398362 ps |
| CPU time | 171.31 seconds |
| Started | Aug 29 07:26:59 AM UTC 24 |
| Finished | Aug 29 07:29:53 AM UTC 24 |
| Peak memory | 279388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793877489 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.2793877489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_errors.3579831972 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 283689363 ps |
| CPU time | 17.39 seconds |
| Started | Aug 29 07:27:06 AM UTC 24 |
| Finished | Aug 29 07:27:24 AM UTC 24 |
| Peak memory | 262884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579831972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3579831972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3484528989 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 86111797 ps |
| CPU time | 12.06 seconds |
| Started | Aug 29 07:28:08 AM UTC 24 |
| Finished | Aug 29 07:28:21 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484528989 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_mem _rw_with_rand_reset.3484528989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_rw.709665820 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 106795084 ps |
| CPU time | 8.3 seconds |
| Started | Aug 29 07:28:04 AM UTC 24 |
| Finished | Aug 29 07:28:13 AM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709665820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.709665820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_intr_test.966778069 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 12127214 ps |
| CPU time | 2.12 seconds |
| Started | Aug 29 07:28:03 AM UTC 24 |
| Finished | Aug 29 07:28:06 AM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966778069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.966778069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3044654881 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 522398746 ps |
| CPU time | 54.49 seconds |
| Started | Aug 29 07:28:07 AM UTC 24 |
| Finished | Aug 29 07:29:03 AM UTC 24 |
| Peak memory | 262680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044654881 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outstanding.3044654881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1273517032 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 7941430370 ps |
| CPU time | 350.98 seconds |
| Started | Aug 29 07:27:41 AM UTC 24 |
| Finished | Aug 29 07:33:37 AM UTC 24 |
| Peak memory | 285596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273517032 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.1273517032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2605964565 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 19248159939 ps |
| CPU time | 659.82 seconds |
| Started | Aug 29 07:27:41 AM UTC 24 |
| Finished | Aug 29 07:38:50 AM UTC 24 |
| Peak memory | 279528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605964565 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shad ow_reg_errors_with_csr_rw.2605964565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_errors.772442897 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 37852497 ps |
| CPU time | 7.5 seconds |
| Started | Aug 29 07:27:55 AM UTC 24 |
| Finished | Aug 29 07:28:03 AM UTC 24 |
| Peak memory | 266980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772442897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.772442897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1722823868 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 56421169 ps |
| CPU time | 4.04 seconds |
| Started | Aug 29 07:28:02 AM UTC 24 |
| Finished | Aug 29 07:28:07 AM UTC 24 |
| Peak memory | 250400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722823868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1722823868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.778550495 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 159431841 ps |
| CPU time | 21.21 seconds |
| Started | Aug 29 07:28:26 AM UTC 24 |
| Finished | Aug 29 07:28:49 AM UTC 24 |
| Peak memory | 268892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778550495 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_mem_ rw_with_rand_reset.778550495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_rw.2236975022 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 50143192 ps |
| CPU time | 7.24 seconds |
| Started | Aug 29 07:28:22 AM UTC 24 |
| Finished | Aug 29 07:28:30 AM UTC 24 |
| Peak memory | 250460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236975022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2236975022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_intr_test.2991314585 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 11312206 ps |
| CPU time | 2.24 seconds |
| Started | Aug 29 07:28:21 AM UTC 24 |
| Finished | Aug 29 07:28:24 AM UTC 24 |
| Peak memory | 250468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991314585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2991314585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1190256488 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 1108093037 ps |
| CPU time | 31.43 seconds |
| Started | Aug 29 07:28:25 AM UTC 24 |
| Finished | Aug 29 07:28:58 AM UTC 24 |
| Peak memory | 262680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190256488 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outstanding.1190256488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.983945498 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 3913879875 ps |
| CPU time | 194.67 seconds |
| Started | Aug 29 07:28:14 AM UTC 24 |
| Finished | Aug 29 07:31:32 AM UTC 24 |
| Peak memory | 285740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983945498 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.983945498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_errors.1135625427 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 178581309 ps |
| CPU time | 7.95 seconds |
| Started | Aug 29 07:28:16 AM UTC 24 |
| Finished | Aug 29 07:28:25 AM UTC 24 |
| Peak memory | 262748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135625427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1135625427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3928428947 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 204086183 ps |
| CPU time | 13.49 seconds |
| Started | Aug 29 07:28:59 AM UTC 24 |
| Finished | Aug 29 07:29:14 AM UTC 24 |
| Peak memory | 268888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928428947 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_mem _rw_with_rand_reset.3928428947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_rw.4029950457 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 443169360 ps |
| CPU time | 12.83 seconds |
| Started | Aug 29 07:28:53 AM UTC 24 |
| Finished | Aug 29 07:29:08 AM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029950457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.4029950457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_intr_test.926713108 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 11165741 ps |
| CPU time | 2.04 seconds |
| Started | Aug 29 07:28:49 AM UTC 24 |
| Finished | Aug 29 07:28:53 AM UTC 24 |
| Peak memory | 250468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926713108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.926713108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3034416696 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 194464452 ps |
| CPU time | 35.31 seconds |
| Started | Aug 29 07:28:56 AM UTC 24 |
| Finished | Aug 29 07:29:33 AM UTC 24 |
| Peak memory | 260632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034416696 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outstanding.3034416696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_errors.656289094 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 193212942 ps |
| CPU time | 11.17 seconds |
| Started | Aug 29 07:28:46 AM UTC 24 |
| Finished | Aug 29 07:28:59 AM UTC 24 |
| Peak memory | 266840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656289094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.656289094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.823486607 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 130200429 ps |
| CPU time | 8.33 seconds |
| Started | Aug 29 07:29:15 AM UTC 24 |
| Finished | Aug 29 07:29:24 AM UTC 24 |
| Peak memory | 252580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823486607 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_mem_ rw_with_rand_reset.823486607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_rw.1505493357 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 67191003 ps |
| CPU time | 8.42 seconds |
| Started | Aug 29 07:29:12 AM UTC 24 |
| Finished | Aug 29 07:29:22 AM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505493357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1505493357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2429660674 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 2567566998 ps |
| CPU time | 40.18 seconds |
| Started | Aug 29 07:29:12 AM UTC 24 |
| Finished | Aug 29 07:29:54 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429660674 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outstanding.2429660674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1233604736 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 43487023156 ps |
| CPU time | 537.66 seconds |
| Started | Aug 29 07:29:00 AM UTC 24 |
| Finished | Aug 29 07:38:05 AM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233604736 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shad ow_reg_errors_with_csr_rw.1233604736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_errors.1980029879 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 124639381 ps |
| CPU time | 13.79 seconds |
| Started | Aug 29 07:29:04 AM UTC 24 |
| Finished | Aug 29 07:29:19 AM UTC 24 |
| Peak memory | 262748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980029879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1980029879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.588395692 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 112337861 ps |
| CPU time | 9.71 seconds |
| Started | Aug 29 07:29:32 AM UTC 24 |
| Finished | Aug 29 07:29:43 AM UTC 24 |
| Peak memory | 262884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588395692 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_mem_ rw_with_rand_reset.588395692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_rw.343849394 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 50705208 ps |
| CPU time | 7.82 seconds |
| Started | Aug 29 07:29:26 AM UTC 24 |
| Finished | Aug 29 07:29:35 AM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343849394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.343849394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_intr_test.2063964010 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 16517751 ps |
| CPU time | 2.06 seconds |
| Started | Aug 29 07:29:26 AM UTC 24 |
| Finished | Aug 29 07:29:29 AM UTC 24 |
| Peak memory | 248284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063964010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2063964010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1900282593 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 353774376 ps |
| CPU time | 28.08 seconds |
| Started | Aug 29 07:29:30 AM UTC 24 |
| Finished | Aug 29 07:30:00 AM UTC 24 |
| Peak memory | 262816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900282593 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outstanding.1900282593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_errors.3957524586 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 31720902 ps |
| CPU time | 7.48 seconds |
| Started | Aug 29 07:29:23 AM UTC 24 |
| Finished | Aug 29 07:29:31 AM UTC 24 |
| Peak memory | 262820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957524586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3957524586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2559370746 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 379686801 ps |
| CPU time | 11.92 seconds |
| Started | Aug 29 07:29:53 AM UTC 24 |
| Finished | Aug 29 07:30:06 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559370746 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_mem _rw_with_rand_reset.2559370746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.8600853 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 63175230 ps |
| CPU time | 7.07 seconds |
| Started | Aug 29 07:29:44 AM UTC 24 |
| Finished | Aug 29 07:29:52 AM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8600853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.8600853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.1230829448 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 10096306 ps |
| CPU time | 2.38 seconds |
| Started | Aug 29 07:29:42 AM UTC 24 |
| Finished | Aug 29 07:29:45 AM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230829448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1230829448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3418617761 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 683555685 ps |
| CPU time | 67.84 seconds |
| Started | Aug 29 07:29:46 AM UTC 24 |
| Finished | Aug 29 07:30:56 AM UTC 24 |
| Peak memory | 262680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418617761 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outstanding.3418617761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2111254941 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 6287324623 ps |
| CPU time | 498.9 seconds |
| Started | Aug 29 07:29:33 AM UTC 24 |
| Finished | Aug 29 07:38:00 AM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111254941 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shad ow_reg_errors_with_csr_rw.2111254941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.2726695264 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 126339292 ps |
| CPU time | 15.01 seconds |
| Started | Aug 29 07:29:36 AM UTC 24 |
| Finished | Aug 29 07:29:52 AM UTC 24 |
| Peak memory | 262748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726695264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2726695264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3217324392 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 71354854 ps |
| CPU time | 8.56 seconds |
| Started | Aug 29 07:30:00 AM UTC 24 |
| Finished | Aug 29 07:30:10 AM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217324392 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_mem _rw_with_rand_reset.3217324392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.2603838026 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 179457433 ps |
| CPU time | 11.4 seconds |
| Started | Aug 29 07:29:58 AM UTC 24 |
| Finished | Aug 29 07:30:11 AM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603838026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2603838026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.122311693 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 11495638 ps |
| CPU time | 2.08 seconds |
| Started | Aug 29 07:29:58 AM UTC 24 |
| Finished | Aug 29 07:30:01 AM UTC 24 |
| Peak memory | 250468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122311693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.122311693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3069904613 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1630737575 ps |
| CPU time | 61.9 seconds |
| Started | Aug 29 07:30:00 AM UTC 24 |
| Finished | Aug 29 07:31:04 AM UTC 24 |
| Peak memory | 260528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069904613 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outstanding.3069904613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3286425074 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2268508173 ps |
| CPU time | 346.36 seconds |
| Started | Aug 29 07:29:53 AM UTC 24 |
| Finished | Aug 29 07:35:44 AM UTC 24 |
| Peak memory | 285608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286425074 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shad ow_reg_errors_with_csr_rw.3286425074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.487719489 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 308863414 ps |
| CPU time | 20.33 seconds |
| Started | Aug 29 07:29:55 AM UTC 24 |
| Finished | Aug 29 07:30:16 AM UTC 24 |
| Peak memory | 262948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487719489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.487719489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.795915272 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 29525582 ps |
| CPU time | 6.93 seconds |
| Started | Aug 29 07:30:18 AM UTC 24 |
| Finished | Aug 29 07:30:26 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795915272 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_mem_ rw_with_rand_reset.795915272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.1662907998 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 65849820 ps |
| CPU time | 6.94 seconds |
| Started | Aug 29 07:30:16 AM UTC 24 |
| Finished | Aug 29 07:30:24 AM UTC 24 |
| Peak memory | 250320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662907998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1662907998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.1935477188 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 26267964 ps |
| CPU time | 2.22 seconds |
| Started | Aug 29 07:30:12 AM UTC 24 |
| Finished | Aug 29 07:30:15 AM UTC 24 |
| Peak memory | 250468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935477188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1935477188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.4137511014 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 1316754051 ps |
| CPU time | 37.86 seconds |
| Started | Aug 29 07:30:17 AM UTC 24 |
| Finished | Aug 29 07:30:56 AM UTC 24 |
| Peak memory | 262680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137511014 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outstanding.4137511014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1849549661 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1480005818 ps |
| CPU time | 120.02 seconds |
| Started | Aug 29 07:30:03 AM UTC 24 |
| Finished | Aug 29 07:32:06 AM UTC 24 |
| Peak memory | 269224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849549661 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.1849549661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2519604935 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 26789091107 ps |
| CPU time | 530.81 seconds |
| Started | Aug 29 07:30:02 AM UTC 24 |
| Finished | Aug 29 07:39:00 AM UTC 24 |
| Peak memory | 279452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519604935 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shad ow_reg_errors_with_csr_rw.2519604935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.2207776381 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 50524817 ps |
| CPU time | 9.32 seconds |
| Started | Aug 29 07:30:07 AM UTC 24 |
| Finished | Aug 29 07:30:17 AM UTC 24 |
| Peak memory | 266844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207776381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2207776381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1844949483 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 102227096 ps |
| CPU time | 6.87 seconds |
| Started | Aug 29 07:30:50 AM UTC 24 |
| Finished | Aug 29 07:30:58 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844949483 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_mem _rw_with_rand_reset.1844949483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.2390752622 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 252486996 ps |
| CPU time | 8.15 seconds |
| Started | Aug 29 07:30:40 AM UTC 24 |
| Finished | Aug 29 07:30:50 AM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390752622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2390752622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.1422429688 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 8128045 ps |
| CPU time | 1.66 seconds |
| Started | Aug 29 07:30:36 AM UTC 24 |
| Finished | Aug 29 07:30:39 AM UTC 24 |
| Peak memory | 248844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422429688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1422429688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2574077166 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 720454829 ps |
| CPU time | 30.34 seconds |
| Started | Aug 29 07:30:48 AM UTC 24 |
| Finished | Aug 29 07:31:20 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574077166 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outstanding.2574077166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3417658329 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2195381433 ps |
| CPU time | 185.54 seconds |
| Started | Aug 29 07:30:25 AM UTC 24 |
| Finished | Aug 29 07:33:34 AM UTC 24 |
| Peak memory | 279392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417658329 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.3417658329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.1987073867 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 42019260 ps |
| CPU time | 7.49 seconds |
| Started | Aug 29 07:30:27 AM UTC 24 |
| Finished | Aug 29 07:30:36 AM UTC 24 |
| Peak memory | 266844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987073867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.1987073867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.4175269524 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 597577374 ps |
| CPU time | 106.23 seconds |
| Started | Aug 29 07:22:58 AM UTC 24 |
| Finished | Aug 29 07:24:46 AM UTC 24 |
| Peak memory | 250328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175269524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.4175269524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1882996341 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 7891520881 ps |
| CPU time | 532.24 seconds |
| Started | Aug 29 07:22:47 AM UTC 24 |
| Finished | Aug 29 07:31:47 AM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882996341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1882996341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1041888071 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 481046243 ps |
| CPU time | 14.98 seconds |
| Started | Aug 29 07:22:43 AM UTC 24 |
| Finished | Aug 29 07:23:00 AM UTC 24 |
| Peak memory | 262560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041888071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1041888071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3842653662 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 428551486 ps |
| CPU time | 8.33 seconds |
| Started | Aug 29 07:23:00 AM UTC 24 |
| Finished | Aug 29 07:23:09 AM UTC 24 |
| Peak memory | 268896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842653662 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_ rw_with_rand_reset.3842653662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_rw.4168980779 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 94254023 ps |
| CPU time | 12.1 seconds |
| Started | Aug 29 07:22:45 AM UTC 24 |
| Finished | Aug 29 07:22:59 AM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168980779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.4168980779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_intr_test.2235733821 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 19302786 ps |
| CPU time | 2.03 seconds |
| Started | Aug 29 07:22:43 AM UTC 24 |
| Finished | Aug 29 07:22:46 AM UTC 24 |
| Peak memory | 250216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235733821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2235733821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3860340999 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 1390006714 ps |
| CPU time | 35.67 seconds |
| Started | Aug 29 07:22:58 AM UTC 24 |
| Finished | Aug 29 07:23:35 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860340999 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.3860340999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.270565735 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 5974035126 ps |
| CPU time | 451.75 seconds |
| Started | Aug 29 07:22:39 AM UTC 24 |
| Finished | Aug 29 07:30:17 AM UTC 24 |
| Peak memory | 279460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270565735 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.270565735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1254716548 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2582430383 ps |
| CPU time | 489.58 seconds |
| Started | Aug 29 07:22:39 AM UTC 24 |
| Finished | Aug 29 07:30:56 AM UTC 24 |
| Peak memory | 279456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254716548 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shado w_reg_errors_with_csr_rw.1254716548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_errors.350011889 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 2250117265 ps |
| CPU time | 43.76 seconds |
| Started | Aug 29 07:22:39 AM UTC 24 |
| Finished | Aug 29 07:23:25 AM UTC 24 |
| Peak memory | 269152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350011889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.350011889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.3773881620 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 10724212 ps |
| CPU time | 2.01 seconds |
| Started | Aug 29 07:30:56 AM UTC 24 |
| Finished | Aug 29 07:30:59 AM UTC 24 |
| Peak memory | 248844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773881620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3773881620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/20.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.1849123043 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 6822939 ps |
| CPU time | 2.29 seconds |
| Started | Aug 29 07:30:58 AM UTC 24 |
| Finished | Aug 29 07:31:01 AM UTC 24 |
| Peak memory | 250532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849123043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1849123043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/21.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.59711736 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 24644432 ps |
| CPU time | 2.07 seconds |
| Started | Aug 29 07:30:58 AM UTC 24 |
| Finished | Aug 29 07:31:01 AM UTC 24 |
| Peak memory | 250400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59711736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_ SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handle r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.59711736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/22.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.2032248840 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 26225099 ps |
| CPU time | 2 seconds |
| Started | Aug 29 07:30:59 AM UTC 24 |
| Finished | Aug 29 07:31:02 AM UTC 24 |
| Peak memory | 248844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032248840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2032248840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/23.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.1505744372 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 17621261 ps |
| CPU time | 2.14 seconds |
| Started | Aug 29 07:31:00 AM UTC 24 |
| Finished | Aug 29 07:31:03 AM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505744372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1505744372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/24.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.3754318584 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 10253067 ps |
| CPU time | 2.19 seconds |
| Started | Aug 29 07:31:02 AM UTC 24 |
| Finished | Aug 29 07:31:05 AM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754318584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3754318584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/25.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.1135348729 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 24163366 ps |
| CPU time | 2.35 seconds |
| Started | Aug 29 07:31:02 AM UTC 24 |
| Finished | Aug 29 07:31:05 AM UTC 24 |
| Peak memory | 250400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135348729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1135348729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/26.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.1306620767 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 8701887 ps |
| CPU time | 2.09 seconds |
| Started | Aug 29 07:31:02 AM UTC 24 |
| Finished | Aug 29 07:31:05 AM UTC 24 |
| Peak memory | 250468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306620767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1306620767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/27.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.3847876086 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 8730419 ps |
| CPU time | 2.25 seconds |
| Started | Aug 29 07:31:03 AM UTC 24 |
| Finished | Aug 29 07:31:06 AM UTC 24 |
| Peak memory | 250532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847876086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3847876086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/28.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.991160084 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 6308513 ps |
| CPU time | 2.21 seconds |
| Started | Aug 29 07:31:04 AM UTC 24 |
| Finished | Aug 29 07:31:07 AM UTC 24 |
| Peak memory | 248356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991160084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.991160084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/29.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2231369270 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 13901322375 ps |
| CPU time | 288.79 seconds |
| Started | Aug 29 07:23:24 AM UTC 24 |
| Finished | Aug 29 07:28:17 AM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231369270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2231369270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.341310059 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 3406419102 ps |
| CPU time | 165.47 seconds |
| Started | Aug 29 07:23:22 AM UTC 24 |
| Finished | Aug 29 07:26:11 AM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341310059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.341310059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3616223224 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 200940214 ps |
| CPU time | 12.55 seconds |
| Started | Aug 29 07:23:19 AM UTC 24 |
| Finished | Aug 29 07:23:33 AM UTC 24 |
| Peak memory | 262752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616223224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3616223224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1911465860 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 51052110 ps |
| CPU time | 8.76 seconds |
| Started | Aug 29 07:23:34 AM UTC 24 |
| Finished | Aug 29 07:23:44 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911465860 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_ rw_with_rand_reset.1911465860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_intr_test.580589032 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 15632068 ps |
| CPU time | 2.23 seconds |
| Started | Aug 29 07:23:19 AM UTC 24 |
| Finished | Aug 29 07:23:22 AM UTC 24 |
| Peak memory | 248480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580589032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.580589032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1766249409 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 909026578 ps |
| CPU time | 31.81 seconds |
| Started | Aug 29 07:23:26 AM UTC 24 |
| Finished | Aug 29 07:23:59 AM UTC 24 |
| Peak memory | 262820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766249409 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.1766249409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_errors.2720299106 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 114606874 ps |
| CPU time | 7.18 seconds |
| Started | Aug 29 07:23:10 AM UTC 24 |
| Finished | Aug 29 07:23:18 AM UTC 24 |
| Peak memory | 262748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720299106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2720299106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.3446581009 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 7757650 ps |
| CPU time | 2.36 seconds |
| Started | Aug 29 07:31:05 AM UTC 24 |
| Finished | Aug 29 07:31:08 AM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446581009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3446581009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/30.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.701184623 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 6499810 ps |
| CPU time | 2.26 seconds |
| Started | Aug 29 07:31:06 AM UTC 24 |
| Finished | Aug 29 07:31:09 AM UTC 24 |
| Peak memory | 250468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701184623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.701184623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/31.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.3323891913 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 18463081 ps |
| CPU time | 2.18 seconds |
| Started | Aug 29 07:31:06 AM UTC 24 |
| Finished | Aug 29 07:31:09 AM UTC 24 |
| Peak memory | 250468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323891913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3323891913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/32.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.4108552826 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 12315351 ps |
| CPU time | 2.16 seconds |
| Started | Aug 29 07:31:06 AM UTC 24 |
| Finished | Aug 29 07:31:09 AM UTC 24 |
| Peak memory | 248284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108552826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.4108552826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/33.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.1736363359 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 24146881 ps |
| CPU time | 1.83 seconds |
| Started | Aug 29 07:31:07 AM UTC 24 |
| Finished | Aug 29 07:31:10 AM UTC 24 |
| Peak memory | 248776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736363359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1736363359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/34.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.3127085543 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 9954034 ps |
| CPU time | 2.07 seconds |
| Started | Aug 29 07:31:07 AM UTC 24 |
| Finished | Aug 29 07:31:10 AM UTC 24 |
| Peak memory | 250468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127085543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3127085543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/35.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.4175529948 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 26441069 ps |
| CPU time | 2.13 seconds |
| Started | Aug 29 07:31:08 AM UTC 24 |
| Finished | Aug 29 07:31:11 AM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175529948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.4175529948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/36.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.3234609214 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 13092415 ps |
| CPU time | 2.62 seconds |
| Started | Aug 29 07:31:09 AM UTC 24 |
| Finished | Aug 29 07:31:13 AM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234609214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3234609214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/37.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.196053463 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 9783103 ps |
| CPU time | 2.09 seconds |
| Started | Aug 29 07:31:10 AM UTC 24 |
| Finished | Aug 29 07:31:14 AM UTC 24 |
| Peak memory | 250468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196053463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.196053463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/38.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.178998047 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 7438415 ps |
| CPU time | 2.26 seconds |
| Started | Aug 29 07:31:11 AM UTC 24 |
| Finished | Aug 29 07:31:14 AM UTC 24 |
| Peak memory | 250468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178998047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.178998047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/39.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1055095217 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 3944069801 ps |
| CPU time | 317.48 seconds |
| Started | Aug 29 07:23:57 AM UTC 24 |
| Finished | Aug 29 07:29:19 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055095217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1055095217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2846861875 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 9604886550 ps |
| CPU time | 288.68 seconds |
| Started | Aug 29 07:23:54 AM UTC 24 |
| Finished | Aug 29 07:28:48 AM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846861875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2846861875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.657964344 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 311761302 ps |
| CPU time | 14.09 seconds |
| Started | Aug 29 07:23:49 AM UTC 24 |
| Finished | Aug 29 07:24:05 AM UTC 24 |
| Peak memory | 262616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657964344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.657964344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3035050859 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 119636606 ps |
| CPU time | 7.68 seconds |
| Started | Aug 29 07:24:02 AM UTC 24 |
| Finished | Aug 29 07:24:10 AM UTC 24 |
| Peak memory | 268960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035050859 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_ rw_with_rand_reset.3035050859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_rw.199456106 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 56654687 ps |
| CPU time | 5.31 seconds |
| Started | Aug 29 07:23:49 AM UTC 24 |
| Finished | Aug 29 07:23:56 AM UTC 24 |
| Peak memory | 252512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199456106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.199456106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_intr_test.1564884748 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 8742356 ps |
| CPU time | 2.42 seconds |
| Started | Aug 29 07:23:45 AM UTC 24 |
| Finished | Aug 29 07:23:49 AM UTC 24 |
| Peak memory | 250468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564884748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1564884748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2705242188 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 94381124 ps |
| CPU time | 19.85 seconds |
| Started | Aug 29 07:24:00 AM UTC 24 |
| Finished | Aug 29 07:24:21 AM UTC 24 |
| Peak memory | 260708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705242188 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.2705242188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3286600578 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 4728507836 ps |
| CPU time | 197.82 seconds |
| Started | Aug 29 07:23:37 AM UTC 24 |
| Finished | Aug 29 07:26:58 AM UTC 24 |
| Peak memory | 279528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286600578 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.3286600578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3642193798 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2309677930 ps |
| CPU time | 438.09 seconds |
| Started | Aug 29 07:23:36 AM UTC 24 |
| Finished | Aug 29 07:31:00 AM UTC 24 |
| Peak memory | 279460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642193798 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shado w_reg_errors_with_csr_rw.3642193798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_errors.2475856860 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 309722259 ps |
| CPU time | 17.98 seconds |
| Started | Aug 29 07:23:42 AM UTC 24 |
| Finished | Aug 29 07:24:01 AM UTC 24 |
| Peak memory | 266916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475856860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2475856860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.2678890748 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 14719981 ps |
| CPU time | 2.2 seconds |
| Started | Aug 29 07:31:11 AM UTC 24 |
| Finished | Aug 29 07:31:14 AM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678890748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2678890748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/40.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.580282844 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 9724627 ps |
| CPU time | 2.35 seconds |
| Started | Aug 29 07:31:11 AM UTC 24 |
| Finished | Aug 29 07:31:14 AM UTC 24 |
| Peak memory | 250404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580282844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.580282844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/41.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.103421413 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 18218250 ps |
| CPU time | 2.07 seconds |
| Started | Aug 29 07:31:12 AM UTC 24 |
| Finished | Aug 29 07:31:15 AM UTC 24 |
| Peak memory | 248420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103421413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.103421413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/42.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.2330348984 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 7521232 ps |
| CPU time | 2.35 seconds |
| Started | Aug 29 07:31:13 AM UTC 24 |
| Finished | Aug 29 07:31:16 AM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330348984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2330348984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/43.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.4045499526 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 15762207 ps |
| CPU time | 2.49 seconds |
| Started | Aug 29 07:31:14 AM UTC 24 |
| Finished | Aug 29 07:31:17 AM UTC 24 |
| Peak memory | 250404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045499526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.4045499526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/44.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.3231872080 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 55953703 ps |
| CPU time | 2.16 seconds |
| Started | Aug 29 07:31:15 AM UTC 24 |
| Finished | Aug 29 07:31:18 AM UTC 24 |
| Peak memory | 250260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231872080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3231872080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/45.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.2810146595 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 6261882 ps |
| CPU time | 2.25 seconds |
| Started | Aug 29 07:31:15 AM UTC 24 |
| Finished | Aug 29 07:31:18 AM UTC 24 |
| Peak memory | 248284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810146595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2810146595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/46.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.3514598283 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 25362628 ps |
| CPU time | 2.23 seconds |
| Started | Aug 29 07:31:15 AM UTC 24 |
| Finished | Aug 29 07:31:18 AM UTC 24 |
| Peak memory | 250468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514598283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3514598283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/47.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.3596435378 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 24143959 ps |
| CPU time | 3.23 seconds |
| Started | Aug 29 07:31:15 AM UTC 24 |
| Finished | Aug 29 07:31:19 AM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596435378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3596435378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/48.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.2538354822 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 11395637 ps |
| CPU time | 2.04 seconds |
| Started | Aug 29 07:31:16 AM UTC 24 |
| Finished | Aug 29 07:31:19 AM UTC 24 |
| Peak memory | 250404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538354822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2538354822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/49.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2168334868 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 149679090 ps |
| CPU time | 16.98 seconds |
| Started | Aug 29 07:24:27 AM UTC 24 |
| Finished | Aug 29 07:24:45 AM UTC 24 |
| Peak memory | 252576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168334868 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_mem_ rw_with_rand_reset.2168334868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_rw.13831712 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 301293401 ps |
| CPU time | 5.19 seconds |
| Started | Aug 29 07:24:21 AM UTC 24 |
| Finished | Aug 29 07:24:28 AM UTC 24 |
| Peak memory | 252376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13831712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_han dler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.13831712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_intr_test.1553054960 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 28260011 ps |
| CPU time | 1.88 seconds |
| Started | Aug 29 07:24:20 AM UTC 24 |
| Finished | Aug 29 07:24:23 AM UTC 24 |
| Peak memory | 246792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553054960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1553054960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.428551260 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 172158489 ps |
| CPU time | 19.76 seconds |
| Started | Aug 29 07:24:24 AM UTC 24 |
| Finished | Aug 29 07:24:45 AM UTC 24 |
| Peak memory | 260636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428551260 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outstanding.428551260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3754961842 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 42015137125 ps |
| CPU time | 1118.75 seconds |
| Started | Aug 29 07:24:02 AM UTC 24 |
| Finished | Aug 29 07:42:54 AM UTC 24 |
| Peak memory | 285740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754961842 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shado w_reg_errors_with_csr_rw.3754961842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_errors.4280586253 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 174253217 ps |
| CPU time | 20.02 seconds |
| Started | Aug 29 07:24:11 AM UTC 24 |
| Finished | Aug 29 07:24:32 AM UTC 24 |
| Peak memory | 262820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280586253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.4280586253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1132949323 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 293330539 ps |
| CPU time | 9.13 seconds |
| Started | Aug 29 07:24:50 AM UTC 24 |
| Finished | Aug 29 07:25:00 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132949323 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_mem_ rw_with_rand_reset.1132949323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_rw.1882241392 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 100482032 ps |
| CPU time | 10.57 seconds |
| Started | Aug 29 07:24:47 AM UTC 24 |
| Finished | Aug 29 07:24:59 AM UTC 24 |
| Peak memory | 252372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882241392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1882241392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.763365099 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 533218764 ps |
| CPU time | 57.87 seconds |
| Started | Aug 29 07:24:47 AM UTC 24 |
| Finished | Aug 29 07:25:47 AM UTC 24 |
| Peak memory | 260628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763365099 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outstanding.763365099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.985700782 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4503209242 ps |
| CPU time | 478.44 seconds |
| Started | Aug 29 07:24:27 AM UTC 24 |
| Finished | Aug 29 07:32:32 AM UTC 24 |
| Peak memory | 279452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985700782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow _reg_errors_with_csr_rw.985700782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_errors.428995918 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 678721152 ps |
| CPU time | 22.19 seconds |
| Started | Aug 29 07:24:34 AM UTC 24 |
| Finished | Aug 29 07:24:57 AM UTC 24 |
| Peak memory | 262816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428995918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.428995918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.19015187 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 665297364 ps |
| CPU time | 8.16 seconds |
| Started | Aug 29 07:25:58 AM UTC 24 |
| Finished | Aug 29 07:26:07 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19015187 -assert nop ostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_mem_rw _with_rand_reset.19015187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_rw.2906377459 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 64465331 ps |
| CPU time | 4.9 seconds |
| Started | Aug 29 07:25:52 AM UTC 24 |
| Finished | Aug 29 07:25:58 AM UTC 24 |
| Peak memory | 250324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906377459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2906377459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_intr_test.2525664708 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 6468887 ps |
| CPU time | 2.16 seconds |
| Started | Aug 29 07:25:48 AM UTC 24 |
| Finished | Aug 29 07:25:51 AM UTC 24 |
| Peak memory | 248284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525664708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2525664708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2361962243 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 85290522 ps |
| CPU time | 17.79 seconds |
| Started | Aug 29 07:25:52 AM UTC 24 |
| Finished | Aug 29 07:26:11 AM UTC 24 |
| Peak memory | 252440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361962243 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outstanding.2361962243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.73444376 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 15607853881 ps |
| CPU time | 361.31 seconds |
| Started | Aug 29 07:24:59 AM UTC 24 |
| Finished | Aug 29 07:31:06 AM UTC 24 |
| Peak memory | 285600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73444376 -assert nopostproc +UVM_TESTNAME=alert_handler_ba se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.73444376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_errors.1053000772 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 364251197 ps |
| CPU time | 10.99 seconds |
| Started | Aug 29 07:25:01 AM UTC 24 |
| Finished | Aug 29 07:25:14 AM UTC 24 |
| Peak memory | 264796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053000772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1053000772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2858238392 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 98828782 ps |
| CPU time | 12.42 seconds |
| Started | Aug 29 07:26:34 AM UTC 24 |
| Finished | Aug 29 07:26:48 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858238392 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_mem_ rw_with_rand_reset.2858238392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_rw.653897235 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 128596120 ps |
| CPU time | 14.37 seconds |
| Started | Aug 29 07:26:19 AM UTC 24 |
| Finished | Aug 29 07:26:34 AM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653897235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.653897235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_intr_test.247174595 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 7476017 ps |
| CPU time | 2.05 seconds |
| Started | Aug 29 07:26:16 AM UTC 24 |
| Finished | Aug 29 07:26:19 AM UTC 24 |
| Peak memory | 250464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247174595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.247174595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3983186107 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 354427115 ps |
| CPU time | 19 seconds |
| Started | Aug 29 07:26:20 AM UTC 24 |
| Finished | Aug 29 07:26:41 AM UTC 24 |
| Peak memory | 262820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983186107 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outstanding.3983186107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.330835027 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 3255434894 ps |
| CPU time | 403.27 seconds |
| Started | Aug 29 07:26:08 AM UTC 24 |
| Finished | Aug 29 07:32:57 AM UTC 24 |
| Peak memory | 279536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330835027 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.330835027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_errors.2069401723 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 791670101 ps |
| CPU time | 20.19 seconds |
| Started | Aug 29 07:26:11 AM UTC 24 |
| Finished | Aug 29 07:26:33 AM UTC 24 |
| Peak memory | 262812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069401723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2069401723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.45685405 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 323902291 ps |
| CPU time | 11.44 seconds |
| Started | Aug 29 07:26:54 AM UTC 24 |
| Finished | Aug 29 07:27:07 AM UTC 24 |
| Peak memory | 252504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45685405 -assert nop ostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_mem_rw _with_rand_reset.45685405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_rw.1781828578 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 66244760 ps |
| CPU time | 8.3 seconds |
| Started | Aug 29 07:26:48 AM UTC 24 |
| Finished | Aug 29 07:26:58 AM UTC 24 |
| Peak memory | 252508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781828578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1781828578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_intr_test.242280307 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 10600653 ps |
| CPU time | 2.24 seconds |
| Started | Aug 29 07:26:46 AM UTC 24 |
| Finished | Aug 29 07:26:49 AM UTC 24 |
| Peak memory | 250328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242280307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.242280307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.489034364 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 2882471172 ps |
| CPU time | 69.94 seconds |
| Started | Aug 29 07:26:50 AM UTC 24 |
| Finished | Aug 29 07:28:02 AM UTC 24 |
| Peak memory | 260692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489034364 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outstanding.489034364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4222809098 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 10800628815 ps |
| CPU time | 203.54 seconds |
| Started | Aug 29 07:26:35 AM UTC 24 |
| Finished | Aug 29 07:30:02 AM UTC 24 |
| Peak memory | 279592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222809098 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.4222809098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_errors.2191631759 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 268844736 ps |
| CPU time | 14.33 seconds |
| Started | Aug 29 07:26:38 AM UTC 24 |
| Finished | Aug 29 07:26:54 AM UTC 24 |
| Peak memory | 262756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191631759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2191631759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_alert_accum.611531716 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 6496846937 ps |
| CPU time | 280.15 seconds |
| Started | Aug 29 07:38:17 AM UTC 24 |
| Finished | Aug 29 07:43:01 AM UTC 24 |
| Peak memory | 265012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611531716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.611531716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_intr_timeout.162376965 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 166080125 ps |
| CPU time | 17.5 seconds |
| Started | Aug 29 07:38:15 AM UTC 24 |
| Finished | Aug 29 07:38:34 AM UTC 24 |
| Peak memory | 267100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162376965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.162376965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg_stub_clk.2385492802 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 24902414991 ps |
| CPU time | 853.06 seconds |
| Started | Aug 29 07:38:17 AM UTC 24 |
| Finished | Aug 29 07:52:41 AM UTC 24 |
| Peak memory | 285832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385492802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2385492802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_alerts.4172012616 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 437920535 ps |
| CPU time | 13.59 seconds |
| Started | Aug 29 07:38:15 AM UTC 24 |
| Finished | Aug 29 07:38:30 AM UTC 24 |
| Peak memory | 266692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172012616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.4172012616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/0.alert_handler_sig_int_fail.2134323027 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2457237219 ps |
| CPU time | 62.31 seconds |
| Started | Aug 29 07:38:17 AM UTC 24 |
| Finished | Aug 29 07:39:21 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134323027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2134323027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all.174677349 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 16570433314 ps |
| CPU time | 1641.82 seconds |
| Started | Aug 29 07:38:17 AM UTC 24 |
| Finished | Aug 29 08:05:59 AM UTC 24 |
| Peak memory | 301880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174677349 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all.174677349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/0.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy_stress.3139686620 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 11549412502 ps |
| CPU time | 80.82 seconds |
| Started | Aug 29 07:38:59 AM UTC 24 |
| Finished | Aug 29 07:40:21 AM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139686620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3139686620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_alert_accum.1517338724 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 8265053688 ps |
| CPU time | 172 seconds |
| Started | Aug 29 07:38:35 AM UTC 24 |
| Finished | Aug 29 07:41:30 AM UTC 24 |
| Peak memory | 269128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517338724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1517338724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg_stub_clk.3306414228 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 70791627738 ps |
| CPU time | 2872.47 seconds |
| Started | Aug 29 07:38:58 AM UTC 24 |
| Finished | Aug 29 08:27:24 AM UTC 24 |
| Peak memory | 301880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306414228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3306414228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/1.alert_handler_ping_timeout.2717961033 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 39776558917 ps |
| CPU time | 420.83 seconds |
| Started | Aug 29 07:38:49 AM UTC 24 |
| Finished | Aug 29 07:45:55 AM UTC 24 |
| Peak memory | 263364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717961033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2717961033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_alerts.2900135369 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2756690873 ps |
| CPU time | 67.42 seconds |
| Started | Aug 29 07:38:18 AM UTC 24 |
| Finished | Aug 29 07:39:28 AM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900135369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2900135369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_classes.3133621120 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 129640064 ps |
| CPU time | 14.91 seconds |
| Started | Aug 29 07:38:26 AM UTC 24 |
| Finished | Aug 29 07:38:42 AM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133621120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3133621120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/1.alert_handler_sec_cm.3231574828 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 462509505 ps |
| CPU time | 30.61 seconds |
| Started | Aug 29 07:39:16 AM UTC 24 |
| Finished | Aug 29 07:39:48 AM UTC 24 |
| Peak memory | 297320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231574828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3231574828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/1.alert_handler_smoke.2369573836 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 215080125 ps |
| CPU time | 23.01 seconds |
| Started | Aug 29 07:38:18 AM UTC 24 |
| Finished | Aug 29 07:38:43 AM UTC 24 |
| Peak memory | 267068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369573836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2369573836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all.742676938 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 21532781295 ps |
| CPU time | 806.04 seconds |
| Started | Aug 29 07:39:01 AM UTC 24 |
| Finished | Aug 29 07:52:38 AM UTC 24 |
| Peak memory | 279352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742676938 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all.742676938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/1.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy.1819806003 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 26261294622 ps |
| CPU time | 1716.6 seconds |
| Started | Aug 29 07:54:32 AM UTC 24 |
| Finished | Aug 29 08:23:31 AM UTC 24 |
| Peak memory | 279428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819806003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1819806003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy_stress.757175056 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 4733696362 ps |
| CPU time | 52.46 seconds |
| Started | Aug 29 07:54:42 AM UTC 24 |
| Finished | Aug 29 07:55:36 AM UTC 24 |
| Peak memory | 262968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757175056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.757175056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_alert_accum.3357039505 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 5043566177 ps |
| CPU time | 425.29 seconds |
| Started | Aug 29 07:54:01 AM UTC 24 |
| Finished | Aug 29 08:01:13 AM UTC 24 |
| Peak memory | 269340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357039505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3357039505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_intr_timeout.795999694 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1510812441 ps |
| CPU time | 30.99 seconds |
| Started | Aug 29 07:53:59 AM UTC 24 |
| Finished | Aug 29 07:54:31 AM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795999694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.795999694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg.4080200505 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 48850668091 ps |
| CPU time | 3389.31 seconds |
| Started | Aug 29 07:54:36 AM UTC 24 |
| Finished | Aug 29 08:51:45 AM UTC 24 |
| Peak memory | 302560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080200505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.4080200505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg_stub_clk.385805925 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 81439556542 ps |
| CPU time | 1744.37 seconds |
| Started | Aug 29 07:54:41 AM UTC 24 |
| Finished | Aug 29 08:24:06 AM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385805925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.385805925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/10.alert_handler_ping_timeout.3005511262 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 43864440176 ps |
| CPU time | 466.69 seconds |
| Started | Aug 29 07:54:35 AM UTC 24 |
| Finished | Aug 29 08:02:27 AM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005511262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3005511262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_alerts.3901422744 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 95965397 ps |
| CPU time | 11.88 seconds |
| Started | Aug 29 07:53:45 AM UTC 24 |
| Finished | Aug 29 07:53:58 AM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901422744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3901422744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/10.alert_handler_sig_int_fail.166007887 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1101634873 ps |
| CPU time | 27.05 seconds |
| Started | Aug 29 07:54:06 AM UTC 24 |
| Finished | Aug 29 07:54:35 AM UTC 24 |
| Peak memory | 263264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166007887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.166007887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/10.alert_handler_smoke.3022571572 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2938231024 ps |
| CPU time | 57.76 seconds |
| Started | Aug 29 07:53:42 AM UTC 24 |
| Finished | Aug 29 07:54:41 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022571572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3022571572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all.2953990302 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 6816724279 ps |
| CPU time | 223.86 seconds |
| Started | Aug 29 07:54:58 AM UTC 24 |
| Finished | Aug 29 07:58:46 AM UTC 24 |
| Peak memory | 269192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953990302 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all.2953990302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all_with_rand_reset.3232061236 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5873964653 ps |
| CPU time | 174.73 seconds |
| Started | Aug 29 07:55:08 AM UTC 24 |
| Finished | Aug 29 07:58:06 AM UTC 24 |
| Peak memory | 279548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3232061236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.a lert_handler_stress_all_with_rand_reset.3232061236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/10.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/11.alert_handler_alert_accum_saturation.2663488311 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 138076117 ps |
| CPU time | 5.16 seconds |
| Started | Aug 29 07:56:23 AM UTC 24 |
| Finished | Aug 29 07:56:29 AM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663488311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2663488311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy.2803859485 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 612805076019 ps |
| CPU time | 2091.52 seconds |
| Started | Aug 29 07:56:04 AM UTC 24 |
| Finished | Aug 29 08:31:21 AM UTC 24 |
| Peak memory | 297784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803859485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2803859485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy_stress.2223915428 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1041059165 ps |
| CPU time | 32.58 seconds |
| Started | Aug 29 07:56:14 AM UTC 24 |
| Finished | Aug 29 07:56:48 AM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223915428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2223915428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_alert_accum.3171427903 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2432006472 ps |
| CPU time | 78.22 seconds |
| Started | Aug 29 07:55:59 AM UTC 24 |
| Finished | Aug 29 07:57:19 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171427903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3171427903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_intr_timeout.1806039809 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1225861504 ps |
| CPU time | 29.83 seconds |
| Started | Aug 29 07:55:59 AM UTC 24 |
| Finished | Aug 29 07:56:30 AM UTC 24 |
| Peak memory | 262896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806039809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1806039809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg_stub_clk.1502667423 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 19600176100 ps |
| CPU time | 1412.57 seconds |
| Started | Aug 29 07:56:08 AM UTC 24 |
| Finished | Aug 29 08:19:57 AM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502667423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1502667423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/11.alert_handler_ping_timeout.2268698504 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 63396541566 ps |
| CPU time | 715.88 seconds |
| Started | Aug 29 07:56:04 AM UTC 24 |
| Finished | Aug 29 08:08:09 AM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268698504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2268698504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_alerts.1085300459 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1982018943 ps |
| CPU time | 84.43 seconds |
| Started | Aug 29 07:55:37 AM UTC 24 |
| Finished | Aug 29 07:57:03 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085300459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1085300459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_classes.2997635582 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 350582079 ps |
| CPU time | 28.59 seconds |
| Started | Aug 29 07:55:49 AM UTC 24 |
| Finished | Aug 29 07:56:19 AM UTC 24 |
| Peak memory | 263260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997635582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2997635582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/11.alert_handler_smoke.3524267066 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 252632850 ps |
| CPU time | 18.73 seconds |
| Started | Aug 29 07:55:28 AM UTC 24 |
| Finished | Aug 29 07:55:48 AM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524267066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3524267066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all.459094699 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 18162654392 ps |
| CPU time | 1150.93 seconds |
| Started | Aug 29 07:56:20 AM UTC 24 |
| Finished | Aug 29 08:15:45 AM UTC 24 |
| Peak memory | 279428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459094699 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all.459094699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all_with_rand_reset.565540978 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 3416579446 ps |
| CPU time | 110.71 seconds |
| Started | Aug 29 07:56:27 AM UTC 24 |
| Finished | Aug 29 07:58:20 AM UTC 24 |
| Peak memory | 279476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=565540978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.al ert_handler_stress_all_with_rand_reset.565540978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/12.alert_handler_alert_accum_saturation.1615692332 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 32307821 ps |
| CPU time | 5.38 seconds |
| Started | Aug 29 07:57:21 AM UTC 24 |
| Finished | Aug 29 07:57:27 AM UTC 24 |
| Peak memory | 263568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615692332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1615692332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy.1405766436 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 42373940581 ps |
| CPU time | 1663.53 seconds |
| Started | Aug 29 07:56:59 AM UTC 24 |
| Finished | Aug 29 08:25:02 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405766436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1405766436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy_stress.229126724 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 510243378 ps |
| CPU time | 18.82 seconds |
| Started | Aug 29 07:57:08 AM UTC 24 |
| Finished | Aug 29 07:57:28 AM UTC 24 |
| Peak memory | 263232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229126724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.229126724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_alert_accum.1373040867 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 884468584 ps |
| CPU time | 119.66 seconds |
| Started | Aug 29 07:56:42 AM UTC 24 |
| Finished | Aug 29 07:58:44 AM UTC 24 |
| Peak memory | 268592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373040867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1373040867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_intr_timeout.339582388 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1255139066 ps |
| CPU time | 19.8 seconds |
| Started | Aug 29 07:56:42 AM UTC 24 |
| Finished | Aug 29 07:57:03 AM UTC 24 |
| Peak memory | 262572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339582388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.339582388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg.1034205527 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 70611864271 ps |
| CPU time | 1539.37 seconds |
| Started | Aug 29 07:57:03 AM UTC 24 |
| Finished | Aug 29 08:23:02 AM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034205527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1034205527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg_stub_clk.3335844981 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 597796348118 ps |
| CPU time | 2292.52 seconds |
| Started | Aug 29 07:57:04 AM UTC 24 |
| Finished | Aug 29 08:35:46 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335844981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3335844981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_alerts.3735522349 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 458073046 ps |
| CPU time | 27.39 seconds |
| Started | Aug 29 07:56:31 AM UTC 24 |
| Finished | Aug 29 07:57:00 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735522349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3735522349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_classes.3381587953 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2090083004 ps |
| CPU time | 24.76 seconds |
| Started | Aug 29 07:56:32 AM UTC 24 |
| Finished | Aug 29 07:56:58 AM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381587953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3381587953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/12.alert_handler_sig_int_fail.1986271929 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 710875756 ps |
| CPU time | 66.67 seconds |
| Started | Aug 29 07:56:49 AM UTC 24 |
| Finished | Aug 29 07:57:57 AM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986271929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1986271929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/12.alert_handler_smoke.488592419 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 2804966517 ps |
| CPU time | 36.55 seconds |
| Started | Aug 29 07:56:30 AM UTC 24 |
| Finished | Aug 29 07:57:08 AM UTC 24 |
| Peak memory | 269104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488592419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.488592419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all.2834305453 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 83672278272 ps |
| CPU time | 2775.93 seconds |
| Started | Aug 29 07:57:11 AM UTC 24 |
| Finished | Aug 29 08:43:59 AM UTC 24 |
| Peak memory | 302212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834305453 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all.2834305453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/12.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/13.alert_handler_alert_accum_saturation.2666695452 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 29452918 ps |
| CPU time | 5.28 seconds |
| Started | Aug 29 07:58:47 AM UTC 24 |
| Finished | Aug 29 07:58:53 AM UTC 24 |
| Peak memory | 263312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666695452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2666695452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy.1560578205 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 57062530319 ps |
| CPU time | 978.22 seconds |
| Started | Aug 29 07:58:12 AM UTC 24 |
| Finished | Aug 29 08:14:43 AM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560578205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1560578205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy_stress.3403579944 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 901108128 ps |
| CPU time | 57.55 seconds |
| Started | Aug 29 07:58:45 AM UTC 24 |
| Finished | Aug 29 07:59:44 AM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403579944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3403579944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_alert_accum.581519588 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 45121747842 ps |
| CPU time | 328.07 seconds |
| Started | Aug 29 07:58:07 AM UTC 24 |
| Finished | Aug 29 08:03:40 AM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581519588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.581519588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_intr_timeout.654638023 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 868102793 ps |
| CPU time | 31.04 seconds |
| Started | Aug 29 07:57:58 AM UTC 24 |
| Finished | Aug 29 07:58:31 AM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654638023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.654638023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg.1218047605 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 53693348434 ps |
| CPU time | 1677.73 seconds |
| Started | Aug 29 07:58:20 AM UTC 24 |
| Finished | Aug 29 08:26:38 AM UTC 24 |
| Peak memory | 300100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218047605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1218047605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg_stub_clk.3821332185 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 123975645964 ps |
| CPU time | 2302.58 seconds |
| Started | Aug 29 07:58:31 AM UTC 24 |
| Finished | Aug 29 08:37:22 AM UTC 24 |
| Peak memory | 295740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821332185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3821332185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/13.alert_handler_ping_timeout.231536766 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 34643465795 ps |
| CPU time | 435.06 seconds |
| Started | Aug 29 07:58:17 AM UTC 24 |
| Finished | Aug 29 08:05:38 AM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231536766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.231536766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_alerts.1775945875 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1805372768 ps |
| CPU time | 45.16 seconds |
| Started | Aug 29 07:57:29 AM UTC 24 |
| Finished | Aug 29 07:58:16 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775945875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1775945875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_classes.676812644 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 870515753 ps |
| CPU time | 78.27 seconds |
| Started | Aug 29 07:57:37 AM UTC 24 |
| Finished | Aug 29 07:58:57 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676812644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.676812644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/13.alert_handler_sig_int_fail.2435186551 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 764984288 ps |
| CPU time | 68.25 seconds |
| Started | Aug 29 07:58:09 AM UTC 24 |
| Finished | Aug 29 07:59:19 AM UTC 24 |
| Peak memory | 262892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435186551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2435186551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/13.alert_handler_smoke.3339494311 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 303064534 ps |
| CPU time | 40.07 seconds |
| Started | Aug 29 07:57:29 AM UTC 24 |
| Finished | Aug 29 07:58:11 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339494311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3339494311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all.1638301801 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 8036606906 ps |
| CPU time | 640.19 seconds |
| Started | Aug 29 07:58:45 AM UTC 24 |
| Finished | Aug 29 08:09:33 AM UTC 24 |
| Peak memory | 285508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638301801 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all.1638301801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all_with_rand_reset.4101003560 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 4963717947 ps |
| CPU time | 167.9 seconds |
| Started | Aug 29 07:58:51 AM UTC 24 |
| Finished | Aug 29 08:01:42 AM UTC 24 |
| Peak memory | 279472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4101003560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.a lert_handler_stress_all_with_rand_reset.4101003560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/13.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy.3163141931 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 10561092942 ps |
| CPU time | 1209.19 seconds |
| Started | Aug 29 07:59:45 AM UTC 24 |
| Finished | Aug 29 08:20:09 AM UTC 24 |
| Peak memory | 295812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163141931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3163141931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy_stress.229416326 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1431941205 ps |
| CPU time | 25.7 seconds |
| Started | Aug 29 08:00:58 AM UTC 24 |
| Finished | Aug 29 08:01:25 AM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229416326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.229416326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_alert_accum.195099149 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 17125044264 ps |
| CPU time | 237.89 seconds |
| Started | Aug 29 07:59:31 AM UTC 24 |
| Finished | Aug 29 08:03:33 AM UTC 24 |
| Peak memory | 269184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195099149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.195099149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_intr_timeout.3849533266 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 87871334 ps |
| CPU time | 9.11 seconds |
| Started | Aug 29 07:59:20 AM UTC 24 |
| Finished | Aug 29 07:59:31 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849533266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3849533266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg_stub_clk.1624110086 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 48641411760 ps |
| CPU time | 3038.74 seconds |
| Started | Aug 29 08:00:47 AM UTC 24 |
| Finished | Aug 29 08:52:02 AM UTC 24 |
| Peak memory | 298464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624110086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1624110086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_alerts.3503259883 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 983420176 ps |
| CPU time | 52.72 seconds |
| Started | Aug 29 07:58:59 AM UTC 24 |
| Finished | Aug 29 07:59:53 AM UTC 24 |
| Peak memory | 269052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503259883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3503259883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_classes.2077838454 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1274707121 ps |
| CPU time | 28.13 seconds |
| Started | Aug 29 07:59:04 AM UTC 24 |
| Finished | Aug 29 07:59:33 AM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077838454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2077838454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/14.alert_handler_smoke.1581877677 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 179275701 ps |
| CPU time | 7.39 seconds |
| Started | Aug 29 07:58:54 AM UTC 24 |
| Finished | Aug 29 07:59:03 AM UTC 24 |
| Peak memory | 265024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581877677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1581877677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all.560363768 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 31243868147 ps |
| CPU time | 2193.41 seconds |
| Started | Aug 29 08:01:13 AM UTC 24 |
| Finished | Aug 29 08:38:12 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560363768 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all.560363768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/14.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/15.alert_handler_alert_accum_saturation.2292128478 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 12754603 ps |
| CPU time | 3.92 seconds |
| Started | Aug 29 08:03:19 AM UTC 24 |
| Finished | Aug 29 08:03:23 AM UTC 24 |
| Peak memory | 263504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292128478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2292128478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy.3179678404 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 154864265183 ps |
| CPU time | 2576.87 seconds |
| Started | Aug 29 08:02:32 AM UTC 24 |
| Finished | Aug 29 08:46:00 AM UTC 24 |
| Peak memory | 295736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179678404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3179678404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy_stress.4004495846 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 1322002002 ps |
| CPU time | 13.61 seconds |
| Started | Aug 29 08:03:03 AM UTC 24 |
| Finished | Aug 29 08:03:18 AM UTC 24 |
| Peak memory | 263300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004495846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.4004495846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_alert_accum.2248082502 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 235242005 ps |
| CPU time | 11.79 seconds |
| Started | Aug 29 08:02:23 AM UTC 24 |
| Finished | Aug 29 08:02:36 AM UTC 24 |
| Peak memory | 267068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248082502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2248082502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_intr_timeout.4074511938 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 4293614257 ps |
| CPU time | 77.26 seconds |
| Started | Aug 29 08:01:43 AM UTC 24 |
| Finished | Aug 29 08:03:02 AM UTC 24 |
| Peak memory | 263100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074511938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.4074511938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg.1628868050 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 52580912878 ps |
| CPU time | 1425.43 seconds |
| Started | Aug 29 08:02:43 AM UTC 24 |
| Finished | Aug 29 08:26:46 AM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628868050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1628868050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/15.alert_handler_ping_timeout.2988272438 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 9726694621 ps |
| CPU time | 577.47 seconds |
| Started | Aug 29 08:02:37 AM UTC 24 |
| Finished | Aug 29 08:12:23 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988272438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2988272438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_alerts.577695664 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 617103958 ps |
| CPU time | 56.15 seconds |
| Started | Aug 29 08:01:33 AM UTC 24 |
| Finished | Aug 29 08:02:31 AM UTC 24 |
| Peak memory | 262968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577695664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.577695664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_classes.2209828313 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 737895136 ps |
| CPU time | 41.03 seconds |
| Started | Aug 29 08:01:40 AM UTC 24 |
| Finished | Aug 29 08:02:23 AM UTC 24 |
| Peak memory | 269404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209828313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2209828313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/15.alert_handler_sig_int_fail.1277974622 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1120914497 ps |
| CPU time | 81.92 seconds |
| Started | Aug 29 08:02:29 AM UTC 24 |
| Finished | Aug 29 08:03:52 AM UTC 24 |
| Peak memory | 263288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277974622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1277974622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/15.alert_handler_smoke.87948336 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 47442247 ps |
| CPU time | 7.7 seconds |
| Started | Aug 29 08:01:30 AM UTC 24 |
| Finished | Aug 29 08:01:39 AM UTC 24 |
| Peak memory | 264944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87948336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smo ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.87948336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all.3963964776 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 31806384020 ps |
| CPU time | 1812.55 seconds |
| Started | Aug 29 08:03:12 AM UTC 24 |
| Finished | Aug 29 08:33:47 AM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963964776 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all.3963964776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/15.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/16.alert_handler_alert_accum_saturation.3179680009 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 434524272 ps |
| CPU time | 4.9 seconds |
| Started | Aug 29 08:05:39 AM UTC 24 |
| Finished | Aug 29 08:05:45 AM UTC 24 |
| Peak memory | 263172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179680009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3179680009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy_stress.2838410791 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1632964363 ps |
| CPU time | 36.56 seconds |
| Started | Aug 29 08:04:34 AM UTC 24 |
| Finished | Aug 29 08:05:12 AM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838410791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2838410791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_alert_accum.2124857294 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 5197576394 ps |
| CPU time | 343.85 seconds |
| Started | Aug 29 08:03:54 AM UTC 24 |
| Finished | Aug 29 08:09:42 AM UTC 24 |
| Peak memory | 269212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124857294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2124857294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_intr_timeout.200084972 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2087251769 ps |
| CPU time | 29.37 seconds |
| Started | Aug 29 08:03:49 AM UTC 24 |
| Finished | Aug 29 08:04:19 AM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200084972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.200084972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg.3532343496 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 38688307896 ps |
| CPU time | 2530.64 seconds |
| Started | Aug 29 08:04:25 AM UTC 24 |
| Finished | Aug 29 08:47:05 AM UTC 24 |
| Peak memory | 285768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532343496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3532343496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg_stub_clk.927325706 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 38052440980 ps |
| CPU time | 2774.3 seconds |
| Started | Aug 29 08:04:32 AM UTC 24 |
| Finished | Aug 29 08:51:20 AM UTC 24 |
| Peak memory | 302280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927325706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.927325706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/16.alert_handler_ping_timeout.3612759010 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 40585481587 ps |
| CPU time | 420.27 seconds |
| Started | Aug 29 08:04:20 AM UTC 24 |
| Finished | Aug 29 08:11:26 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612759010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3612759010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_alerts.412467909 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1006504222 ps |
| CPU time | 51.73 seconds |
| Started | Aug 29 08:03:40 AM UTC 24 |
| Finished | Aug 29 08:04:33 AM UTC 24 |
| Peak memory | 269368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412467909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.412467909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_classes.3063199462 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1945957904 ps |
| CPU time | 38.1 seconds |
| Started | Aug 29 08:03:44 AM UTC 24 |
| Finished | Aug 29 08:04:24 AM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063199462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3063199462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/16.alert_handler_smoke.3284521589 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1128747792 ps |
| CPU time | 43.17 seconds |
| Started | Aug 29 08:03:34 AM UTC 24 |
| Finished | Aug 29 08:04:19 AM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284521589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3284521589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all.2975413498 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 304191448490 ps |
| CPU time | 3453.06 seconds |
| Started | Aug 29 08:05:14 AM UTC 24 |
| Finished | Aug 29 09:03:26 AM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975413498 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all.2975413498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/16.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/17.alert_handler_alert_accum_saturation.1672500536 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 180698481 ps |
| CPU time | 6.1 seconds |
| Started | Aug 29 08:09:35 AM UTC 24 |
| Finished | Aug 29 08:09:42 AM UTC 24 |
| Peak memory | 263184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672500536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1672500536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy.3082632787 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 33973615642 ps |
| CPU time | 2337.02 seconds |
| Started | Aug 29 08:07:34 AM UTC 24 |
| Finished | Aug 29 08:46:58 AM UTC 24 |
| Peak memory | 298116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082632787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3082632787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy_stress.1444092128 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 772068908 ps |
| CPU time | 49.01 seconds |
| Started | Aug 29 08:08:46 AM UTC 24 |
| Finished | Aug 29 08:09:36 AM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444092128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1444092128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_alert_accum.1357514697 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2732548352 ps |
| CPU time | 244.77 seconds |
| Started | Aug 29 08:06:49 AM UTC 24 |
| Finished | Aug 29 08:10:58 AM UTC 24 |
| Peak memory | 269212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357514697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1357514697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_intr_timeout.381007456 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 146770616 ps |
| CPU time | 20.94 seconds |
| Started | Aug 29 08:06:26 AM UTC 24 |
| Finished | Aug 29 08:06:48 AM UTC 24 |
| Peak memory | 269440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381007456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.381007456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg_stub_clk.217053531 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 16075883551 ps |
| CPU time | 1635.63 seconds |
| Started | Aug 29 08:08:10 AM UTC 24 |
| Finished | Aug 29 08:35:45 AM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217053531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.217053531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/17.alert_handler_ping_timeout.1515671539 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 5131202979 ps |
| CPU time | 242.39 seconds |
| Started | Aug 29 08:07:52 AM UTC 24 |
| Finished | Aug 29 08:11:58 AM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515671539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1515671539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_alerts.1822521672 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 764294249 ps |
| CPU time | 35.75 seconds |
| Started | Aug 29 08:06:12 AM UTC 24 |
| Finished | Aug 29 08:06:49 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822521672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1822521672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_classes.4131885324 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 3630749318 ps |
| CPU time | 84.3 seconds |
| Started | Aug 29 08:06:26 AM UTC 24 |
| Finished | Aug 29 08:07:52 AM UTC 24 |
| Peak memory | 263164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131885324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.4131885324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/17.alert_handler_sig_int_fail.2582631070 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 365537773 ps |
| CPU time | 41.44 seconds |
| Started | Aug 29 08:06:50 AM UTC 24 |
| Finished | Aug 29 08:07:32 AM UTC 24 |
| Peak memory | 269176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582631070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2582631070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/17.alert_handler_smoke.223775729 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 55602143 ps |
| CPU time | 8.21 seconds |
| Started | Aug 29 08:06:02 AM UTC 24 |
| Finished | Aug 29 08:06:11 AM UTC 24 |
| Peak memory | 265020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223775729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.223775729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all.2498867805 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 14626160841 ps |
| CPU time | 1699.99 seconds |
| Started | Aug 29 08:08:54 AM UTC 24 |
| Finished | Aug 29 08:37:34 AM UTC 24 |
| Peak memory | 302084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498867805 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all.2498867805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/17.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/18.alert_handler_alert_accum_saturation.1827647363 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 33555801 ps |
| CPU time | 4.99 seconds |
| Started | Aug 29 08:11:36 AM UTC 24 |
| Finished | Aug 29 08:11:42 AM UTC 24 |
| Peak memory | 263504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827647363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1827647363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy.135815193 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 58126362707 ps |
| CPU time | 3116.35 seconds |
| Started | Aug 29 08:10:20 AM UTC 24 |
| Finished | Aug 29 09:02:53 AM UTC 24 |
| Peak memory | 304612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135815193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.135815193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy_stress.1752598909 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1587030273 ps |
| CPU time | 30.1 seconds |
| Started | Aug 29 08:11:14 AM UTC 24 |
| Finished | Aug 29 08:11:46 AM UTC 24 |
| Peak memory | 263300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752598909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1752598909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_alert_accum.2338083246 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 7166053610 ps |
| CPU time | 211.38 seconds |
| Started | Aug 29 08:09:55 AM UTC 24 |
| Finished | Aug 29 08:13:30 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338083246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2338083246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_intr_timeout.3825226065 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 679713324 ps |
| CPU time | 24.41 seconds |
| Started | Aug 29 08:09:54 AM UTC 24 |
| Finished | Aug 29 08:10:20 AM UTC 24 |
| Peak memory | 263292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825226065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3825226065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg.2760087572 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 25703234343 ps |
| CPU time | 2170.84 seconds |
| Started | Aug 29 08:10:59 AM UTC 24 |
| Finished | Aug 29 08:47:35 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760087572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2760087572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg_stub_clk.1007255913 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 28370635509 ps |
| CPU time | 1768.31 seconds |
| Started | Aug 29 08:11:03 AM UTC 24 |
| Finished | Aug 29 08:40:52 AM UTC 24 |
| Peak memory | 301960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007255913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1007255913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/18.alert_handler_ping_timeout.638877247 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2434416618 ps |
| CPU time | 106.64 seconds |
| Started | Aug 29 08:10:28 AM UTC 24 |
| Finished | Aug 29 08:12:18 AM UTC 24 |
| Peak memory | 269192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638877247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.638877247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_alerts.1652058977 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 579863544 ps |
| CPU time | 17.26 seconds |
| Started | Aug 29 08:09:44 AM UTC 24 |
| Finished | Aug 29 08:10:02 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652058977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1652058977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_classes.1871207597 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2337912432 ps |
| CPU time | 108.35 seconds |
| Started | Aug 29 08:09:44 AM UTC 24 |
| Finished | Aug 29 08:11:35 AM UTC 24 |
| Peak memory | 263068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871207597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1871207597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/18.alert_handler_sig_int_fail.525280942 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 356165630 ps |
| CPU time | 22.95 seconds |
| Started | Aug 29 08:10:03 AM UTC 24 |
| Finished | Aug 29 08:10:27 AM UTC 24 |
| Peak memory | 269152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525280942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.525280942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/18.alert_handler_smoke.2379525652 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 141012515 ps |
| CPU time | 9.65 seconds |
| Started | Aug 29 08:09:44 AM UTC 24 |
| Finished | Aug 29 08:09:54 AM UTC 24 |
| Peak memory | 267000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379525652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2379525652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all.1768335091 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 190890892908 ps |
| CPU time | 3372.41 seconds |
| Started | Aug 29 08:11:27 AM UTC 24 |
| Finished | Aug 29 09:08:18 AM UTC 24 |
| Peak memory | 304684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768335091 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all.1768335091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all_with_rand_reset.574852475 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 4144673361 ps |
| CPU time | 153.67 seconds |
| Started | Aug 29 08:11:41 AM UTC 24 |
| Finished | Aug 29 08:14:17 AM UTC 24 |
| Peak memory | 279476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=574852475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.al ert_handler_stress_all_with_rand_reset.574852475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/19.alert_handler_alert_accum_saturation.140902468 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 13725631 ps |
| CPU time | 3.62 seconds |
| Started | Aug 29 08:13:00 AM UTC 24 |
| Finished | Aug 29 08:13:04 AM UTC 24 |
| Peak memory | 263504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140902468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.140902468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy.3424201513 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 96349070660 ps |
| CPU time | 3199.6 seconds |
| Started | Aug 29 08:12:24 AM UTC 24 |
| Finished | Aug 29 09:06:19 AM UTC 24 |
| Peak memory | 304680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424201513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3424201513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy_stress.3901536101 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 296361154 ps |
| CPU time | 14.8 seconds |
| Started | Aug 29 08:12:42 AM UTC 24 |
| Finished | Aug 29 08:12:58 AM UTC 24 |
| Peak memory | 263236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901536101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3901536101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_alert_accum.1240485989 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 20491423977 ps |
| CPU time | 397.91 seconds |
| Started | Aug 29 08:12:06 AM UTC 24 |
| Finished | Aug 29 08:18:50 AM UTC 24 |
| Peak memory | 269436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240485989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1240485989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_intr_timeout.1772579329 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1283897113 ps |
| CPU time | 34.51 seconds |
| Started | Aug 29 08:11:59 AM UTC 24 |
| Finished | Aug 29 08:12:35 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772579329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1772579329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg_stub_clk.1477930637 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 288317822341 ps |
| CPU time | 1926.81 seconds |
| Started | Aug 29 08:12:39 AM UTC 24 |
| Finished | Aug 29 08:45:08 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477930637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1477930637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/19.alert_handler_ping_timeout.1533080561 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 38385895806 ps |
| CPU time | 362.16 seconds |
| Started | Aug 29 08:12:37 AM UTC 24 |
| Finished | Aug 29 08:18:43 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533080561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1533080561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_alerts.4061748337 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 103740514 ps |
| CPU time | 18.24 seconds |
| Started | Aug 29 08:11:46 AM UTC 24 |
| Finished | Aug 29 08:12:06 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061748337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.4061748337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_classes.849772152 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 438252481 ps |
| CPU time | 50.51 seconds |
| Started | Aug 29 08:11:51 AM UTC 24 |
| Finished | Aug 29 08:12:43 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849772152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.849772152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/19.alert_handler_sig_int_fail.1857128544 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 499258921 ps |
| CPU time | 21.35 seconds |
| Started | Aug 29 08:12:18 AM UTC 24 |
| Finished | Aug 29 08:12:41 AM UTC 24 |
| Peak memory | 262892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857128544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1857128544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/19.alert_handler_smoke.2265976453 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 3137816354 ps |
| CPU time | 76.23 seconds |
| Started | Aug 29 08:11:42 AM UTC 24 |
| Finished | Aug 29 08:13:00 AM UTC 24 |
| Peak memory | 269440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265976453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2265976453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all.2348090864 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 396831257 ps |
| CPU time | 35.65 seconds |
| Started | Aug 29 08:12:44 AM UTC 24 |
| Finished | Aug 29 08:13:21 AM UTC 24 |
| Peak memory | 263236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348090864 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all.2348090864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all_with_rand_reset.1646187530 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 5124479001 ps |
| CPU time | 630.45 seconds |
| Started | Aug 29 08:13:01 AM UTC 24 |
| Finished | Aug 29 08:23:40 AM UTC 24 |
| Peak memory | 281852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1646187530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.a lert_handler_stress_all_with_rand_reset.1646187530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/2.alert_handler_alert_accum_saturation.1261598237 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 79477877 ps |
| CPU time | 5.45 seconds |
| Started | Aug 29 07:40:43 AM UTC 24 |
| Finished | Aug 29 07:40:50 AM UTC 24 |
| Peak memory | 263172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261598237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1261598237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy.1874056165 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 24281339124 ps |
| CPU time | 785.4 seconds |
| Started | Aug 29 07:39:52 AM UTC 24 |
| Finished | Aug 29 07:53:06 AM UTC 24 |
| Peak memory | 281736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874056165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1874056165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy_stress.3932879802 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 733006448 ps |
| CPU time | 47.04 seconds |
| Started | Aug 29 07:40:33 AM UTC 24 |
| Finished | Aug 29 07:41:22 AM UTC 24 |
| Peak memory | 262912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932879802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3932879802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_intr_timeout.1643487658 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 307300300 ps |
| CPU time | 9.36 seconds |
| Started | Aug 29 07:39:39 AM UTC 24 |
| Finished | Aug 29 07:39:50 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643487658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1643487658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg_stub_clk.3804863918 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 50472763683 ps |
| CPU time | 1854.85 seconds |
| Started | Aug 29 07:40:23 AM UTC 24 |
| Finished | Aug 29 08:11:39 AM UTC 24 |
| Peak memory | 295940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804863918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3804863918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_classes.2735709298 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 826271228 ps |
| CPU time | 70 seconds |
| Started | Aug 29 07:39:28 AM UTC 24 |
| Finished | Aug 29 07:40:40 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735709298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2735709298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/2.alert_handler_sec_cm.1187597448 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 740758108 ps |
| CPU time | 17.85 seconds |
| Started | Aug 29 07:40:50 AM UTC 24 |
| Finished | Aug 29 07:41:10 AM UTC 24 |
| Peak memory | 297328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187597448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1187597448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/2.alert_handler_sig_int_fail.1518276545 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 160468967 ps |
| CPU time | 14.31 seconds |
| Started | Aug 29 07:39:50 AM UTC 24 |
| Finished | Aug 29 07:40:06 AM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518276545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1518276545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/2.alert_handler_smoke.864769834 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 991792912 ps |
| CPU time | 28.88 seconds |
| Started | Aug 29 07:39:22 AM UTC 24 |
| Finished | Aug 29 07:39:52 AM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864769834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.864769834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/2.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/20.alert_handler_entropy.202829725 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 141279485488 ps |
| CPU time | 2285.95 seconds |
| Started | Aug 29 08:14:18 AM UTC 24 |
| Finished | Aug 29 08:52:50 AM UTC 24 |
| Peak memory | 301956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202829725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.202829725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/20.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_alert_accum.3524490131 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 12250827162 ps |
| CPU time | 281.22 seconds |
| Started | Aug 29 08:13:55 AM UTC 24 |
| Finished | Aug 29 08:18:41 AM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524490131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3524490131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_intr_timeout.3241117257 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 8673865996 ps |
| CPU time | 40.71 seconds |
| Started | Aug 29 08:13:53 AM UTC 24 |
| Finished | Aug 29 08:14:35 AM UTC 24 |
| Peak memory | 269180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241117257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3241117257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg_stub_clk.2018096254 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 18749529943 ps |
| CPU time | 1508.1 seconds |
| Started | Aug 29 08:14:30 AM UTC 24 |
| Finished | Aug 29 08:39:58 AM UTC 24 |
| Peak memory | 295740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018096254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2018096254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_alerts.1678438132 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1223368811 ps |
| CPU time | 36.7 seconds |
| Started | Aug 29 08:13:21 AM UTC 24 |
| Finished | Aug 29 08:13:59 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678438132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1678438132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/20.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_classes.3049695207 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 457179782 ps |
| CPU time | 56.29 seconds |
| Started | Aug 29 08:13:31 AM UTC 24 |
| Finished | Aug 29 08:14:29 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049695207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3049695207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/20.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/20.alert_handler_smoke.4128257347 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1504636136 ps |
| CPU time | 47.38 seconds |
| Started | Aug 29 08:13:05 AM UTC 24 |
| Finished | Aug 29 08:13:54 AM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128257347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.4128257347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/20.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all.4084788107 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 255231521041 ps |
| CPU time | 2303.54 seconds |
| Started | Aug 29 08:14:36 AM UTC 24 |
| Finished | Aug 29 08:53:25 AM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084788107 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all.4084788107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/20.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all_with_rand_reset.1949772788 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 41780639336 ps |
| CPU time | 389.87 seconds |
| Started | Aug 29 08:14:45 AM UTC 24 |
| Finished | Aug 29 08:21:20 AM UTC 24 |
| Peak memory | 283644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1949772788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.a lert_handler_stress_all_with_rand_reset.1949772788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/21.alert_handler_entropy.1808519744 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 151197657428 ps |
| CPU time | 2456.7 seconds |
| Started | Aug 29 08:17:34 AM UTC 24 |
| Finished | Aug 29 08:58:59 AM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808519744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1808519744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/21.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_alert_accum.934860403 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 492877595 ps |
| CPU time | 15.3 seconds |
| Started | Aug 29 08:17:18 AM UTC 24 |
| Finished | Aug 29 08:17:35 AM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934860403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.934860403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_intr_timeout.1798665903 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 284994262 ps |
| CPU time | 28.13 seconds |
| Started | Aug 29 08:17:04 AM UTC 24 |
| Finished | Aug 29 08:17:33 AM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798665903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1798665903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg.2676233837 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 15093591960 ps |
| CPU time | 1688.4 seconds |
| Started | Aug 29 08:17:52 AM UTC 24 |
| Finished | Aug 29 08:46:22 AM UTC 24 |
| Peak memory | 302216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676233837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2676233837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/21.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg_stub_clk.712251927 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 10147734133 ps |
| CPU time | 1082.52 seconds |
| Started | Aug 29 08:18:17 AM UTC 24 |
| Finished | Aug 29 08:36:34 AM UTC 24 |
| Peak memory | 297792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712251927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.712251927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/21.alert_handler_ping_timeout.1088503603 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2450609084 ps |
| CPU time | 115 seconds |
| Started | Aug 29 08:17:35 AM UTC 24 |
| Finished | Aug 29 08:19:32 AM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088503603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1088503603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_alerts.279212692 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2248759802 ps |
| CPU time | 97.62 seconds |
| Started | Aug 29 08:16:37 AM UTC 24 |
| Finished | Aug 29 08:18:16 AM UTC 24 |
| Peak memory | 263288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279212692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.279212692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/21.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_classes.835473971 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1319638204 ps |
| CPU time | 40.44 seconds |
| Started | Aug 29 08:16:51 AM UTC 24 |
| Finished | Aug 29 08:17:33 AM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835473971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.835473971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/21.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/21.alert_handler_sig_int_fail.159635088 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 777109731 ps |
| CPU time | 66.42 seconds |
| Started | Aug 29 08:17:34 AM UTC 24 |
| Finished | Aug 29 08:18:42 AM UTC 24 |
| Peak memory | 269152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159635088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.159635088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/21.alert_handler_smoke.2903216255 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1083408115 ps |
| CPU time | 73.91 seconds |
| Started | Aug 29 08:15:47 AM UTC 24 |
| Finished | Aug 29 08:17:02 AM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903216255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2903216255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/21.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all.3393746999 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 91922509195 ps |
| CPU time | 2405.31 seconds |
| Started | Aug 29 08:18:42 AM UTC 24 |
| Finished | Aug 29 08:59:14 AM UTC 24 |
| Peak memory | 302020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393746999 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all.3393746999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/21.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/22.alert_handler_entropy.2432830638 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 42109379341 ps |
| CPU time | 2825.39 seconds |
| Started | Aug 29 08:19:13 AM UTC 24 |
| Finished | Aug 29 09:06:51 AM UTC 24 |
| Peak memory | 298460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432830638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2432830638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/22.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_alert_accum.278107075 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 3482161912 ps |
| CPU time | 82.19 seconds |
| Started | Aug 29 08:18:53 AM UTC 24 |
| Finished | Aug 29 08:20:17 AM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278107075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.278107075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_intr_timeout.984735470 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 203142402 ps |
| CPU time | 18.08 seconds |
| Started | Aug 29 08:18:52 AM UTC 24 |
| Finished | Aug 29 08:19:12 AM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984735470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.984735470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg.2992755420 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 125588113917 ps |
| CPU time | 1741.95 seconds |
| Started | Aug 29 08:19:25 AM UTC 24 |
| Finished | Aug 29 08:48:47 AM UTC 24 |
| Peak memory | 281480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992755420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2992755420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/22.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg_stub_clk.3757392496 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 7880427511 ps |
| CPU time | 862.49 seconds |
| Started | Aug 29 08:19:33 AM UTC 24 |
| Finished | Aug 29 08:34:06 AM UTC 24 |
| Peak memory | 285832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757392496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3757392496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/22.alert_handler_ping_timeout.906717001 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 9414288105 ps |
| CPU time | 241.47 seconds |
| Started | Aug 29 08:19:24 AM UTC 24 |
| Finished | Aug 29 08:23:29 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906717001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.906717001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_alerts.3386795108 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1119509713 ps |
| CPU time | 97.79 seconds |
| Started | Aug 29 08:18:45 AM UTC 24 |
| Finished | Aug 29 08:20:25 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386795108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3386795108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/22.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_classes.551018122 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 553843500 ps |
| CPU time | 5.27 seconds |
| Started | Aug 29 08:18:45 AM UTC 24 |
| Finished | Aug 29 08:18:52 AM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551018122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.551018122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/22.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/22.alert_handler_smoke.3079215995 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 757123798 ps |
| CPU time | 53.84 seconds |
| Started | Aug 29 08:18:45 AM UTC 24 |
| Finished | Aug 29 08:19:41 AM UTC 24 |
| Peak memory | 269376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079215995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3079215995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/22.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all.2087273709 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 14094412487 ps |
| CPU time | 1565.23 seconds |
| Started | Aug 29 08:19:42 AM UTC 24 |
| Finished | Aug 29 08:46:06 AM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087273709 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all.2087273709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/22.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/23.alert_handler_entropy.561886346 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 144088412324 ps |
| CPU time | 2205.01 seconds |
| Started | Aug 29 08:21:27 AM UTC 24 |
| Finished | Aug 29 08:58:37 AM UTC 24 |
| Peak memory | 302216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561886346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.561886346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/23.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_alert_accum.3042931062 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 9902263091 ps |
| CPU time | 205.09 seconds |
| Started | Aug 29 08:20:59 AM UTC 24 |
| Finished | Aug 29 08:24:28 AM UTC 24 |
| Peak memory | 269532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042931062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3042931062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_intr_timeout.1768960079 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 945199857 ps |
| CPU time | 30.74 seconds |
| Started | Aug 29 08:20:54 AM UTC 24 |
| Finished | Aug 29 08:21:26 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768960079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1768960079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg.24693629 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 64315637252 ps |
| CPU time | 1755.85 seconds |
| Started | Aug 29 08:21:35 AM UTC 24 |
| Finished | Aug 29 08:51:11 AM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24693629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.24693629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/23.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/23.alert_handler_ping_timeout.3405824596 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 20702916170 ps |
| CPU time | 389.82 seconds |
| Started | Aug 29 08:21:32 AM UTC 24 |
| Finished | Aug 29 08:28:07 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405824596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3405824596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_alerts.2114362609 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 3786332087 ps |
| CPU time | 74.13 seconds |
| Started | Aug 29 08:20:18 AM UTC 24 |
| Finished | Aug 29 08:21:34 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114362609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2114362609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/23.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_classes.1182598634 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 312081836 ps |
| CPU time | 31.5 seconds |
| Started | Aug 29 08:20:26 AM UTC 24 |
| Finished | Aug 29 08:20:59 AM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182598634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1182598634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/23.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/23.alert_handler_sig_int_fail.2274232521 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 42336920 ps |
| CPU time | 9.63 seconds |
| Started | Aug 29 08:21:20 AM UTC 24 |
| Finished | Aug 29 08:21:31 AM UTC 24 |
| Peak memory | 262968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274232521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2274232521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/23.alert_handler_smoke.1634474998 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 3802115976 ps |
| CPU time | 81.11 seconds |
| Started | Aug 29 08:20:12 AM UTC 24 |
| Finished | Aug 29 08:21:35 AM UTC 24 |
| Peak memory | 269504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634474998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1634474998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/23.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all.3148033835 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 15248701706 ps |
| CPU time | 198.47 seconds |
| Started | Aug 29 08:21:56 AM UTC 24 |
| Finished | Aug 29 08:25:17 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148033835 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all.3148033835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/23.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/24.alert_handler_entropy.1394654232 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 97580770278 ps |
| CPU time | 2790.04 seconds |
| Started | Aug 29 08:24:13 AM UTC 24 |
| Finished | Aug 29 09:11:14 AM UTC 24 |
| Peak memory | 302888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394654232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1394654232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/24.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_alert_accum.1840839362 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 3946199177 ps |
| CPU time | 151.99 seconds |
| Started | Aug 29 08:24:09 AM UTC 24 |
| Finished | Aug 29 08:26:44 AM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840839362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1840839362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_intr_timeout.2846137522 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 4761008029 ps |
| CPU time | 41.35 seconds |
| Started | Aug 29 08:23:57 AM UTC 24 |
| Finished | Aug 29 08:24:40 AM UTC 24 |
| Peak memory | 269436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846137522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2846137522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg.1861973475 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 17648885107 ps |
| CPU time | 1176.17 seconds |
| Started | Aug 29 08:24:40 AM UTC 24 |
| Finished | Aug 29 08:44:31 AM UTC 24 |
| Peak memory | 285832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861973475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1861973475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/24.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg_stub_clk.1684607432 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 28676940298 ps |
| CPU time | 2391.39 seconds |
| Started | Aug 29 08:24:50 AM UTC 24 |
| Finished | Aug 29 09:05:10 AM UTC 24 |
| Peak memory | 299332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684607432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1684607432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/24.alert_handler_ping_timeout.1569335288 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 10478402406 ps |
| CPU time | 114.03 seconds |
| Started | Aug 29 08:24:28 AM UTC 24 |
| Finished | Aug 29 08:26:25 AM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569335288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1569335288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_alerts.1353300873 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 904163734 ps |
| CPU time | 77.08 seconds |
| Started | Aug 29 08:23:32 AM UTC 24 |
| Finished | Aug 29 08:24:51 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353300873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1353300873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/24.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_classes.873753704 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 107507187 ps |
| CPU time | 14.09 seconds |
| Started | Aug 29 08:23:41 AM UTC 24 |
| Finished | Aug 29 08:23:56 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873753704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.873753704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/24.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/24.alert_handler_sig_int_fail.2163771288 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1085089814 ps |
| CPU time | 34.92 seconds |
| Started | Aug 29 08:24:12 AM UTC 24 |
| Finished | Aug 29 08:24:48 AM UTC 24 |
| Peak memory | 269240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163771288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2163771288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/24.alert_handler_smoke.1187166603 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 3647635464 ps |
| CPU time | 40 seconds |
| Started | Aug 29 08:23:29 AM UTC 24 |
| Finished | Aug 29 08:24:11 AM UTC 24 |
| Peak memory | 269440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187166603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1187166603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/24.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all.222033807 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 59937945787 ps |
| CPU time | 1510.81 seconds |
| Started | Aug 29 08:24:53 AM UTC 24 |
| Finished | Aug 29 08:50:23 AM UTC 24 |
| Peak memory | 285828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222033807 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all.222033807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/24.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/25.alert_handler_entropy.2717264350 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 134114030634 ps |
| CPU time | 2721.51 seconds |
| Started | Aug 29 08:26:04 AM UTC 24 |
| Finished | Aug 29 09:11:58 AM UTC 24 |
| Peak memory | 288220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717264350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2717264350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/25.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_alert_accum.1638423226 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 767381231 ps |
| CPU time | 50.21 seconds |
| Started | Aug 29 08:25:49 AM UTC 24 |
| Finished | Aug 29 08:26:41 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638423226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1638423226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/25.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_intr_timeout.692513357 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 903924739 ps |
| CPU time | 29.84 seconds |
| Started | Aug 29 08:25:40 AM UTC 24 |
| Finished | Aug 29 08:26:11 AM UTC 24 |
| Peak memory | 269376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692513357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.692513357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg.1748827199 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 19514490568 ps |
| CPU time | 1568.19 seconds |
| Started | Aug 29 08:26:12 AM UTC 24 |
| Finished | Aug 29 08:52:39 AM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748827199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1748827199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/25.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg_stub_clk.3184033576 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 12195742423 ps |
| CPU time | 1752.22 seconds |
| Started | Aug 29 08:26:16 AM UTC 24 |
| Finished | Aug 29 08:55:50 AM UTC 24 |
| Peak memory | 302216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184033576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3184033576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/25.alert_handler_ping_timeout.3169810892 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 27588562043 ps |
| CPU time | 291.61 seconds |
| Started | Aug 29 08:26:09 AM UTC 24 |
| Finished | Aug 29 08:31:05 AM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169810892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3169810892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_alerts.2213006433 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1591352134 ps |
| CPU time | 40.89 seconds |
| Started | Aug 29 08:25:05 AM UTC 24 |
| Finished | Aug 29 08:25:48 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213006433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2213006433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/25.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_classes.1466947049 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 678423550 ps |
| CPU time | 43.52 seconds |
| Started | Aug 29 08:25:18 AM UTC 24 |
| Finished | Aug 29 08:26:03 AM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466947049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1466947049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/25.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/25.alert_handler_sig_int_fail.1414552279 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 425230271 ps |
| CPU time | 10.32 seconds |
| Started | Aug 29 08:26:03 AM UTC 24 |
| Finished | Aug 29 08:26:15 AM UTC 24 |
| Peak memory | 263224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414552279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1414552279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/25.alert_handler_smoke.1253003927 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1218033145 ps |
| CPU time | 55.2 seconds |
| Started | Aug 29 08:25:05 AM UTC 24 |
| Finished | Aug 29 08:26:02 AM UTC 24 |
| Peak memory | 269376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253003927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1253003927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/25.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all.1897768410 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 99494125026 ps |
| CPU time | 3053.19 seconds |
| Started | Aug 29 08:26:26 AM UTC 24 |
| Finished | Aug 29 09:17:56 AM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897768410 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all.1897768410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/25.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/26.alert_handler_entropy.3145677596 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 57521971601 ps |
| CPU time | 1446.53 seconds |
| Started | Aug 29 08:27:42 AM UTC 24 |
| Finished | Aug 29 08:52:07 AM UTC 24 |
| Peak memory | 301880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145677596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3145677596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/26.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_alert_accum.1627213670 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 5936310715 ps |
| CPU time | 114.82 seconds |
| Started | Aug 29 08:27:26 AM UTC 24 |
| Finished | Aug 29 08:29:23 AM UTC 24 |
| Peak memory | 269140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627213670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1627213670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/26.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_intr_timeout.3723249005 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1412914061 ps |
| CPU time | 36.58 seconds |
| Started | Aug 29 08:26:48 AM UTC 24 |
| Finished | Aug 29 08:27:27 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723249005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3723249005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg.1952088955 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 62123589024 ps |
| CPU time | 1681.01 seconds |
| Started | Aug 29 08:27:45 AM UTC 24 |
| Finished | Aug 29 08:56:05 AM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952088955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1952088955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/26.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg_stub_clk.698817634 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 53496974835 ps |
| CPU time | 2237.76 seconds |
| Started | Aug 29 08:27:59 AM UTC 24 |
| Finished | Aug 29 09:05:44 AM UTC 24 |
| Peak memory | 301872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698817634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.698817634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_alerts.2126511944 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2239051945 ps |
| CPU time | 56.09 seconds |
| Started | Aug 29 08:26:45 AM UTC 24 |
| Finished | Aug 29 08:27:42 AM UTC 24 |
| Peak memory | 263036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126511944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2126511944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/26.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_classes.3017983170 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 1338427009 ps |
| CPU time | 51.86 seconds |
| Started | Aug 29 08:26:48 AM UTC 24 |
| Finished | Aug 29 08:27:42 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017983170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3017983170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/26.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/26.alert_handler_sig_int_fail.1930758392 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 635124872 ps |
| CPU time | 29.62 seconds |
| Started | Aug 29 08:27:27 AM UTC 24 |
| Finished | Aug 29 08:27:58 AM UTC 24 |
| Peak memory | 262892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930758392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1930758392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/26.alert_handler_smoke.1119105414 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 5500200272 ps |
| CPU time | 60.97 seconds |
| Started | Aug 29 08:26:42 AM UTC 24 |
| Finished | Aug 29 08:27:44 AM UTC 24 |
| Peak memory | 269440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119105414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1119105414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/26.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all.1097083173 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 46428590078 ps |
| CPU time | 1671 seconds |
| Started | Aug 29 08:28:05 AM UTC 24 |
| Finished | Aug 29 08:56:19 AM UTC 24 |
| Peak memory | 300164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097083173 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all.1097083173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/26.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all_with_rand_reset.1871570282 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2103043884 ps |
| CPU time | 278.02 seconds |
| Started | Aug 29 08:28:09 AM UTC 24 |
| Finished | Aug 29 08:32:51 AM UTC 24 |
| Peak memory | 281532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1871570282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.a lert_handler_stress_all_with_rand_reset.1871570282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/27.alert_handler_entropy.4222378248 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 18669305326 ps |
| CPU time | 1170.53 seconds |
| Started | Aug 29 08:30:07 AM UTC 24 |
| Finished | Aug 29 08:49:53 AM UTC 24 |
| Peak memory | 283780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222378248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.4222378248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/27.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_alert_accum.2744843486 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 4705625954 ps |
| CPU time | 287.27 seconds |
| Started | Aug 29 08:29:55 AM UTC 24 |
| Finished | Aug 29 08:34:47 AM UTC 24 |
| Peak memory | 269212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744843486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2744843486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/27.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_intr_timeout.1182310657 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 667276131 ps |
| CPU time | 35.48 seconds |
| Started | Aug 29 08:29:41 AM UTC 24 |
| Finished | Aug 29 08:30:19 AM UTC 24 |
| Peak memory | 262896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182310657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1182310657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg.981843247 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 29735524784 ps |
| CPU time | 2116.46 seconds |
| Started | Aug 29 08:31:02 AM UTC 24 |
| Finished | Aug 29 09:06:43 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981843247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.981843247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/27.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg_stub_clk.2918141317 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 501508452891 ps |
| CPU time | 1811.89 seconds |
| Started | Aug 29 08:31:06 AM UTC 24 |
| Finished | Aug 29 09:01:40 AM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918141317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2918141317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/27.alert_handler_ping_timeout.307043955 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 6894043474 ps |
| CPU time | 425.47 seconds |
| Started | Aug 29 08:30:20 AM UTC 24 |
| Finished | Aug 29 08:37:31 AM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307043955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.307043955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_alerts.3910271077 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 61254824 ps |
| CPU time | 7.03 seconds |
| Started | Aug 29 08:29:24 AM UTC 24 |
| Finished | Aug 29 08:29:33 AM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910271077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3910271077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/27.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_classes.1797801435 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 426642592 ps |
| CPU time | 20.01 seconds |
| Started | Aug 29 08:29:34 AM UTC 24 |
| Finished | Aug 29 08:29:55 AM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797801435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1797801435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/27.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/27.alert_handler_sig_int_fail.2708110967 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 223272323 ps |
| CPU time | 7.77 seconds |
| Started | Aug 29 08:29:56 AM UTC 24 |
| Finished | Aug 29 08:30:06 AM UTC 24 |
| Peak memory | 262968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708110967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2708110967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/27.alert_handler_smoke.381499311 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 268174121 ps |
| CPU time | 38.94 seconds |
| Started | Aug 29 08:29:15 AM UTC 24 |
| Finished | Aug 29 08:29:56 AM UTC 24 |
| Peak memory | 269244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381499311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.381499311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/27.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all_with_rand_reset.704818560 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 10518103665 ps |
| CPU time | 455.21 seconds |
| Started | Aug 29 08:31:23 AM UTC 24 |
| Finished | Aug 29 08:39:06 AM UTC 24 |
| Peak memory | 283576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=704818560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.al ert_handler_stress_all_with_rand_reset.704818560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/28.alert_handler_entropy.1810013474 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 69649458057 ps |
| CPU time | 1038.84 seconds |
| Started | Aug 29 08:34:03 AM UTC 24 |
| Finished | Aug 29 08:51:35 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810013474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1810013474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/28.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_alert_accum.3107229356 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 5504680972 ps |
| CPU time | 454.5 seconds |
| Started | Aug 29 08:33:50 AM UTC 24 |
| Finished | Aug 29 08:41:32 AM UTC 24 |
| Peak memory | 269468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107229356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3107229356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/28.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_intr_timeout.3684216179 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 587583716 ps |
| CPU time | 19.24 seconds |
| Started | Aug 29 08:33:49 AM UTC 24 |
| Finished | Aug 29 08:34:10 AM UTC 24 |
| Peak memory | 262896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684216179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3684216179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg.590065814 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 92534245116 ps |
| CPU time | 1805.22 seconds |
| Started | Aug 29 08:34:11 AM UTC 24 |
| Finished | Aug 29 09:04:38 AM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590065814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.590065814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/28.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg_stub_clk.3471708859 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 6635968484 ps |
| CPU time | 552.25 seconds |
| Started | Aug 29 08:34:43 AM UTC 24 |
| Finished | Aug 29 08:44:03 AM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471708859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3471708859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/28.alert_handler_ping_timeout.4258589751 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 7916529114 ps |
| CPU time | 369.59 seconds |
| Started | Aug 29 08:34:08 AM UTC 24 |
| Finished | Aug 29 08:40:23 AM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258589751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4258589751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_alerts.3220265796 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 310722860 ps |
| CPU time | 26.68 seconds |
| Started | Aug 29 08:33:11 AM UTC 24 |
| Finished | Aug 29 08:33:39 AM UTC 24 |
| Peak memory | 267324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220265796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3220265796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/28.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_classes.328930776 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 129654502 ps |
| CPU time | 20.45 seconds |
| Started | Aug 29 08:33:40 AM UTC 24 |
| Finished | Aug 29 08:34:02 AM UTC 24 |
| Peak memory | 263164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328930776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.328930776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/28.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/28.alert_handler_smoke.3614014631 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 4671225241 ps |
| CPU time | 56.16 seconds |
| Started | Aug 29 08:32:52 AM UTC 24 |
| Finished | Aug 29 08:33:50 AM UTC 24 |
| Peak memory | 269440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614014631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3614014631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/28.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all.883863022 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 169728058721 ps |
| CPU time | 3201.88 seconds |
| Started | Aug 29 08:34:48 AM UTC 24 |
| Finished | Aug 29 09:28:48 AM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883863022 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all.883863022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/28.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/29.alert_handler_entropy.2531023807 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 403048539469 ps |
| CPU time | 1800.8 seconds |
| Started | Aug 29 08:37:19 AM UTC 24 |
| Finished | Aug 29 09:07:42 AM UTC 24 |
| Peak memory | 298116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531023807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2531023807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/29.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_alert_accum.1544940042 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 1213915479 ps |
| CPU time | 41.36 seconds |
| Started | Aug 29 08:36:36 AM UTC 24 |
| Finished | Aug 29 08:37:19 AM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544940042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1544940042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/29.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_intr_timeout.1389076354 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1397702325 ps |
| CPU time | 72.29 seconds |
| Started | Aug 29 08:36:26 AM UTC 24 |
| Finished | Aug 29 08:37:40 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389076354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1389076354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg_stub_clk.268323313 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 22570050077 ps |
| CPU time | 1116.83 seconds |
| Started | Aug 29 08:37:32 AM UTC 24 |
| Finished | Aug 29 08:56:24 AM UTC 24 |
| Peak memory | 285640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268323313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.268323313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/29.alert_handler_ping_timeout.1502919882 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 5939154510 ps |
| CPU time | 376.74 seconds |
| Started | Aug 29 08:37:20 AM UTC 24 |
| Finished | Aug 29 08:43:42 AM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502919882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1502919882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_alerts.3886520973 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 1400549330 ps |
| CPU time | 35.06 seconds |
| Started | Aug 29 08:35:48 AM UTC 24 |
| Finished | Aug 29 08:36:25 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886520973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3886520973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/29.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_classes.382048034 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 2785512521 ps |
| CPU time | 78.86 seconds |
| Started | Aug 29 08:35:56 AM UTC 24 |
| Finished | Aug 29 08:37:17 AM UTC 24 |
| Peak memory | 262964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382048034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.382048034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/29.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/29.alert_handler_sig_int_fail.141600562 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 22409650727 ps |
| CPU time | 80.57 seconds |
| Started | Aug 29 08:36:43 AM UTC 24 |
| Finished | Aug 29 08:38:06 AM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141600562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.141600562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/29.alert_handler_smoke.1754816124 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 414806670 ps |
| CPU time | 52.37 seconds |
| Started | Aug 29 08:35:48 AM UTC 24 |
| Finished | Aug 29 08:36:42 AM UTC 24 |
| Peak memory | 269376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754816124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1754816124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/29.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all.320529791 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 57992970151 ps |
| CPU time | 3317.02 seconds |
| Started | Aug 29 08:37:37 AM UTC 24 |
| Finished | Aug 29 09:33:31 AM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320529791 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all.320529791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/29.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/3.alert_handler_alert_accum_saturation.2609796461 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 76040215 ps |
| CPU time | 5.01 seconds |
| Started | Aug 29 07:42:53 AM UTC 24 |
| Finished | Aug 29 07:42:59 AM UTC 24 |
| Peak memory | 263172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609796461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2609796461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy.171567875 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 24708037241 ps |
| CPU time | 2175.17 seconds |
| Started | Aug 29 07:42:09 AM UTC 24 |
| Finished | Aug 29 08:18:50 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171567875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.171567875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy_stress.502482041 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 301121593 ps |
| CPU time | 21.42 seconds |
| Started | Aug 29 07:42:33 AM UTC 24 |
| Finished | Aug 29 07:42:55 AM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502482041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.502482041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_alert_accum.973747235 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 3869367421 ps |
| CPU time | 169.78 seconds |
| Started | Aug 29 07:41:43 AM UTC 24 |
| Finished | Aug 29 07:44:36 AM UTC 24 |
| Peak memory | 269468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973747235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.973747235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg_stub_clk.162676645 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 137349127278 ps |
| CPU time | 2520.2 seconds |
| Started | Aug 29 07:42:25 AM UTC 24 |
| Finished | Aug 29 08:24:56 AM UTC 24 |
| Peak memory | 302216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162676645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.162676645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/3.alert_handler_ping_timeout.3644477500 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 15787709316 ps |
| CPU time | 412.59 seconds |
| Started | Aug 29 07:42:11 AM UTC 24 |
| Finished | Aug 29 07:49:09 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644477500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3644477500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_alerts.213765473 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 258747546 ps |
| CPU time | 8.43 seconds |
| Started | Aug 29 07:41:23 AM UTC 24 |
| Finished | Aug 29 07:41:32 AM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213765473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.213765473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_classes.2865545186 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 264345707 ps |
| CPU time | 13.88 seconds |
| Started | Aug 29 07:41:31 AM UTC 24 |
| Finished | Aug 29 07:41:46 AM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865545186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2865545186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/3.alert_handler_sec_cm.2394647396 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1639275648 ps |
| CPU time | 20.97 seconds |
| Started | Aug 29 07:42:56 AM UTC 24 |
| Finished | Aug 29 07:43:18 AM UTC 24 |
| Peak memory | 297456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394647396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2394647396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/3.alert_handler_sig_int_fail.1963237240 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 957389887 ps |
| CPU time | 25.68 seconds |
| Started | Aug 29 07:41:47 AM UTC 24 |
| Finished | Aug 29 07:42:15 AM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963237240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1963237240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/3.alert_handler_smoke.853807501 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 1050726012 ps |
| CPU time | 30.69 seconds |
| Started | Aug 29 07:41:11 AM UTC 24 |
| Finished | Aug 29 07:41:43 AM UTC 24 |
| Peak memory | 269244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853807501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.853807501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/3.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/30.alert_handler_entropy.1979980347 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 217099558994 ps |
| CPU time | 3530.4 seconds |
| Started | Aug 29 08:38:50 AM UTC 24 |
| Finished | Aug 29 09:38:21 AM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979980347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1979980347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/30.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_alert_accum.1963768996 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 3845623427 ps |
| CPU time | 224.4 seconds |
| Started | Aug 29 08:38:44 AM UTC 24 |
| Finished | Aug 29 08:42:32 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963768996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1963768996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/30.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_intr_timeout.989769450 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 220036164 ps |
| CPU time | 22.78 seconds |
| Started | Aug 29 08:38:18 AM UTC 24 |
| Finished | Aug 29 08:38:42 AM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989769450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.989769450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg.420340724 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 37946835140 ps |
| CPU time | 2405.74 seconds |
| Started | Aug 29 08:39:07 AM UTC 24 |
| Finished | Aug 29 09:19:40 AM UTC 24 |
| Peak memory | 288292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420340724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.420340724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/30.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg_stub_clk.3131795789 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 34565136193 ps |
| CPU time | 1218.57 seconds |
| Started | Aug 29 08:39:16 AM UTC 24 |
| Finished | Aug 29 08:59:50 AM UTC 24 |
| Peak memory | 302216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131795789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3131795789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/30.alert_handler_ping_timeout.2196150165 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 7840175758 ps |
| CPU time | 333.46 seconds |
| Started | Aug 29 08:38:54 AM UTC 24 |
| Finished | Aug 29 08:44:32 AM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196150165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2196150165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_alerts.1093944265 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 312567225 ps |
| CPU time | 36.25 seconds |
| Started | Aug 29 08:38:12 AM UTC 24 |
| Finished | Aug 29 08:38:49 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093944265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1093944265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/30.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_classes.3110620910 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3358588294 ps |
| CPU time | 78.25 seconds |
| Started | Aug 29 08:38:14 AM UTC 24 |
| Finished | Aug 29 08:39:34 AM UTC 24 |
| Peak memory | 269340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110620910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3110620910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/30.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/30.alert_handler_smoke.1429972799 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 1544884024 ps |
| CPU time | 65.9 seconds |
| Started | Aug 29 08:38:07 AM UTC 24 |
| Finished | Aug 29 08:39:14 AM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429972799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1429972799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/30.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all.3446488334 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 54248399624 ps |
| CPU time | 292.36 seconds |
| Started | Aug 29 08:39:35 AM UTC 24 |
| Finished | Aug 29 08:44:32 AM UTC 24 |
| Peak memory | 269508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446488334 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all.3446488334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/30.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all_with_rand_reset.2059145585 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 20493345981 ps |
| CPU time | 729.87 seconds |
| Started | Aug 29 08:39:39 AM UTC 24 |
| Finished | Aug 29 08:51:58 AM UTC 24 |
| Peak memory | 295856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2059145585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.a lert_handler_stress_all_with_rand_reset.2059145585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/31.alert_handler_entropy.1360028893 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 137351481686 ps |
| CPU time | 2976.99 seconds |
| Started | Aug 29 08:40:43 AM UTC 24 |
| Finished | Aug 29 09:30:52 AM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360028893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1360028893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/31.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_alert_accum.4085589691 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 5269927826 ps |
| CPU time | 289.11 seconds |
| Started | Aug 29 08:40:19 AM UTC 24 |
| Finished | Aug 29 08:45:12 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085589691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.4085589691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/31.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_intr_timeout.1420625537 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 287066161 ps |
| CPU time | 37.49 seconds |
| Started | Aug 29 08:40:12 AM UTC 24 |
| Finished | Aug 29 08:40:51 AM UTC 24 |
| Peak memory | 262896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420625537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1420625537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg.4158816662 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 12786142831 ps |
| CPU time | 976.79 seconds |
| Started | Aug 29 08:40:56 AM UTC 24 |
| Finished | Aug 29 08:57:24 AM UTC 24 |
| Peak memory | 301960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158816662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.4158816662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/31.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg_stub_clk.1150964416 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 67349816279 ps |
| CPU time | 2077.57 seconds |
| Started | Aug 29 08:40:57 AM UTC 24 |
| Finished | Aug 29 09:16:00 AM UTC 24 |
| Peak memory | 302152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150964416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1150964416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/31.alert_handler_ping_timeout.4098141002 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 10975157664 ps |
| CPU time | 660.33 seconds |
| Started | Aug 29 08:40:52 AM UTC 24 |
| Finished | Aug 29 08:52:01 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098141002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.4098141002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_alerts.519710526 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 552895989 ps |
| CPU time | 13.54 seconds |
| Started | Aug 29 08:40:03 AM UTC 24 |
| Finished | Aug 29 08:40:18 AM UTC 24 |
| Peak memory | 262896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519710526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.519710526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/31.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_classes.3705801556 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 1157409485 ps |
| CPU time | 99.31 seconds |
| Started | Aug 29 08:40:07 AM UTC 24 |
| Finished | Aug 29 08:41:48 AM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705801556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3705801556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/31.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/31.alert_handler_sig_int_fail.2838826911 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 1742592002 ps |
| CPU time | 30.41 seconds |
| Started | Aug 29 08:40:23 AM UTC 24 |
| Finished | Aug 29 08:40:56 AM UTC 24 |
| Peak memory | 269036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838826911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2838826911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/31.alert_handler_smoke.3116074924 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1087286384 ps |
| CPU time | 39.4 seconds |
| Started | Aug 29 08:40:01 AM UTC 24 |
| Finished | Aug 29 08:40:42 AM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116074924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3116074924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/31.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all.2188808824 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 25702617542 ps |
| CPU time | 1741.46 seconds |
| Started | Aug 29 08:41:34 AM UTC 24 |
| Finished | Aug 29 09:10:57 AM UTC 24 |
| Peak memory | 285116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188808824 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all.2188808824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/31.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/32.alert_handler_entropy.4026169790 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 27272553616 ps |
| CPU time | 933.76 seconds |
| Started | Aug 29 08:43:21 AM UTC 24 |
| Finished | Aug 29 08:59:06 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026169790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.4026169790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/32.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_alert_accum.58695241 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 10252169059 ps |
| CPU time | 51.38 seconds |
| Started | Aug 29 08:43:06 AM UTC 24 |
| Finished | Aug 29 08:43:59 AM UTC 24 |
| Peak memory | 269176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58695241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc _alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.58695241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/32.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_intr_timeout.475330792 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 577681737 ps |
| CPU time | 24.05 seconds |
| Started | Aug 29 08:42:48 AM UTC 24 |
| Finished | Aug 29 08:43:14 AM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475330792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.475330792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg.4244825746 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 56307112383 ps |
| CPU time | 1346.06 seconds |
| Started | Aug 29 08:43:43 AM UTC 24 |
| Finished | Aug 29 09:06:25 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244825746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.4244825746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/32.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg_stub_clk.2338102404 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 265691728379 ps |
| CPU time | 2534.26 seconds |
| Started | Aug 29 08:43:55 AM UTC 24 |
| Finished | Aug 29 09:26:41 AM UTC 24 |
| Peak memory | 300512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338102404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2338102404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_alerts.416519012 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2766254855 ps |
| CPU time | 55.36 seconds |
| Started | Aug 29 08:41:50 AM UTC 24 |
| Finished | Aug 29 08:42:47 AM UTC 24 |
| Peak memory | 269496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416519012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.416519012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/32.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_classes.3489104172 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1180025531 ps |
| CPU time | 29.4 seconds |
| Started | Aug 29 08:42:34 AM UTC 24 |
| Finished | Aug 29 08:43:05 AM UTC 24 |
| Peak memory | 263292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489104172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3489104172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/32.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/32.alert_handler_sig_int_fail.325404722 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 2048077559 ps |
| CPU time | 36.88 seconds |
| Started | Aug 29 08:43:15 AM UTC 24 |
| Finished | Aug 29 08:43:54 AM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325404722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.325404722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/32.alert_handler_smoke.1701342330 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 2140265302 ps |
| CPU time | 92.91 seconds |
| Started | Aug 29 08:41:48 AM UTC 24 |
| Finished | Aug 29 08:43:23 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701342330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1701342330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/32.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all.584516942 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 242876962876 ps |
| CPU time | 1881.96 seconds |
| Started | Aug 29 08:44:00 AM UTC 24 |
| Finished | Aug 29 09:15:45 AM UTC 24 |
| Peak memory | 301888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584516942 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all.584516942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/32.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all_with_rand_reset.2906029460 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2995450650 ps |
| CPU time | 172.28 seconds |
| Started | Aug 29 08:44:05 AM UTC 24 |
| Finished | Aug 29 08:47:00 AM UTC 24 |
| Peak memory | 279796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2906029460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.a lert_handler_stress_all_with_rand_reset.2906029460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/33.alert_handler_entropy.3574963168 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 85720535511 ps |
| CPU time | 1459.74 seconds |
| Started | Aug 29 08:45:11 AM UTC 24 |
| Finished | Aug 29 09:09:48 AM UTC 24 |
| Peak memory | 279356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574963168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3574963168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/33.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_alert_accum.499793929 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 3907096665 ps |
| CPU time | 144.99 seconds |
| Started | Aug 29 08:44:53 AM UTC 24 |
| Finished | Aug 29 08:47:21 AM UTC 24 |
| Peak memory | 262964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499793929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.499793929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/33.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_intr_timeout.3985276156 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 202737434 ps |
| CPU time | 26.02 seconds |
| Started | Aug 29 08:44:33 AM UTC 24 |
| Finished | Aug 29 08:45:01 AM UTC 24 |
| Peak memory | 262896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985276156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3985276156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg.14843338 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 8235531215 ps |
| CPU time | 701.92 seconds |
| Started | Aug 29 08:45:17 AM UTC 24 |
| Finished | Aug 29 08:57:08 AM UTC 24 |
| Peak memory | 279424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14843338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.14843338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/33.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg_stub_clk.2347155706 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 34918799807 ps |
| CPU time | 1062.59 seconds |
| Started | Aug 29 08:45:47 AM UTC 24 |
| Finished | Aug 29 09:03:44 AM UTC 24 |
| Peak memory | 285640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347155706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2347155706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_alerts.2440144212 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2646767998 ps |
| CPU time | 41.27 seconds |
| Started | Aug 29 08:44:33 AM UTC 24 |
| Finished | Aug 29 08:45:16 AM UTC 24 |
| Peak memory | 263036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440144212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2440144212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/33.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_classes.2188211623 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 173020801 ps |
| CPU time | 17.04 seconds |
| Started | Aug 29 08:44:33 AM UTC 24 |
| Finished | Aug 29 08:44:51 AM UTC 24 |
| Peak memory | 269404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188211623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2188211623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/33.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/33.alert_handler_smoke.3246850225 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 1148247146 ps |
| CPU time | 105.51 seconds |
| Started | Aug 29 08:44:05 AM UTC 24 |
| Finished | Aug 29 08:45:53 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246850225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3246850225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/33.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all.790828431 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 242891586671 ps |
| CPU time | 3785.73 seconds |
| Started | Aug 29 08:45:54 AM UTC 24 |
| Finished | Aug 29 09:49:43 AM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790828431 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all.790828431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/33.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/34.alert_handler_entropy.3218673705 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 75023573197 ps |
| CPU time | 2067.47 seconds |
| Started | Aug 29 08:47:02 AM UTC 24 |
| Finished | Aug 29 09:21:55 AM UTC 24 |
| Peak memory | 304676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218673705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3218673705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/34.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_alert_accum.1873833700 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 3366261232 ps |
| CPU time | 156.66 seconds |
| Started | Aug 29 08:46:37 AM UTC 24 |
| Finished | Aug 29 08:49:17 AM UTC 24 |
| Peak memory | 269136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873833700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1873833700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/34.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_intr_timeout.2375588756 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 270120255 ps |
| CPU time | 39.29 seconds |
| Started | Aug 29 08:46:32 AM UTC 24 |
| Finished | Aug 29 08:47:13 AM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375588756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2375588756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg.3417888154 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 116866976657 ps |
| CPU time | 754.29 seconds |
| Started | Aug 29 08:47:11 AM UTC 24 |
| Finished | Aug 29 08:59:55 AM UTC 24 |
| Peak memory | 279356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417888154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3417888154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/34.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg_stub_clk.341804387 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 14402240711 ps |
| CPU time | 806.84 seconds |
| Started | Aug 29 08:47:16 AM UTC 24 |
| Finished | Aug 29 09:00:54 AM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341804387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.341804387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/34.alert_handler_ping_timeout.2911040938 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 40296312536 ps |
| CPU time | 208.15 seconds |
| Started | Aug 29 08:47:08 AM UTC 24 |
| Finished | Aug 29 08:50:39 AM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911040938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2911040938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_alerts.1339416769 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 93385674 ps |
| CPU time | 13.22 seconds |
| Started | Aug 29 08:46:21 AM UTC 24 |
| Finished | Aug 29 08:46:35 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339416769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1339416769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/34.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_classes.3628349436 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 731982024 ps |
| CPU time | 42.18 seconds |
| Started | Aug 29 08:46:25 AM UTC 24 |
| Finished | Aug 29 08:47:09 AM UTC 24 |
| Peak memory | 269404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628349436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3628349436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/34.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/34.alert_handler_sig_int_fail.1635998010 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 560177576 ps |
| CPU time | 30.49 seconds |
| Started | Aug 29 08:47:02 AM UTC 24 |
| Finished | Aug 29 08:47:34 AM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635998010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1635998010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/34.alert_handler_smoke.376835879 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 1325384470 ps |
| CPU time | 22.6 seconds |
| Started | Aug 29 08:46:08 AM UTC 24 |
| Finished | Aug 29 08:46:31 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376835879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.376835879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/34.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all.2568847394 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 3639182808 ps |
| CPU time | 390.5 seconds |
| Started | Aug 29 08:47:20 AM UTC 24 |
| Finished | Aug 29 08:53:56 AM UTC 24 |
| Peak memory | 279432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568847394 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all.2568847394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/34.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all_with_rand_reset.1612589942 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 5445676476 ps |
| CPU time | 350.53 seconds |
| Started | Aug 29 08:47:22 AM UTC 24 |
| Finished | Aug 29 08:53:18 AM UTC 24 |
| Peak memory | 281520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1612589942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.a lert_handler_stress_all_with_rand_reset.1612589942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/35.alert_handler_entropy.525132727 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 103416765668 ps |
| CPU time | 1688.56 seconds |
| Started | Aug 29 08:48:49 AM UTC 24 |
| Finished | Aug 29 09:17:18 AM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525132727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.525132727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/35.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_alert_accum.3015003964 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1116770874 ps |
| CPU time | 74.48 seconds |
| Started | Aug 29 08:48:30 AM UTC 24 |
| Finished | Aug 29 08:49:46 AM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015003964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3015003964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/35.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_intr_timeout.1576307892 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 100468288 ps |
| CPU time | 12.89 seconds |
| Started | Aug 29 08:48:14 AM UTC 24 |
| Finished | Aug 29 08:48:28 AM UTC 24 |
| Peak memory | 262896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576307892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1576307892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg.2650670399 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 12940535862 ps |
| CPU time | 1158.85 seconds |
| Started | Aug 29 08:49:19 AM UTC 24 |
| Finished | Aug 29 09:08:51 AM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650670399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2650670399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/35.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg_stub_clk.335686298 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 18494098972 ps |
| CPU time | 1415.92 seconds |
| Started | Aug 29 08:49:48 AM UTC 24 |
| Finished | Aug 29 09:13:41 AM UTC 24 |
| Peak memory | 301960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335686298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.335686298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/35.alert_handler_ping_timeout.1541874769 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 7077805088 ps |
| CPU time | 416.98 seconds |
| Started | Aug 29 08:49:00 AM UTC 24 |
| Finished | Aug 29 08:56:03 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541874769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1541874769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_alerts.649630115 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 355855479 ps |
| CPU time | 28.43 seconds |
| Started | Aug 29 08:47:38 AM UTC 24 |
| Finished | Aug 29 08:48:08 AM UTC 24 |
| Peak memory | 262968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649630115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.649630115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/35.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_classes.1712281579 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 215841238 ps |
| CPU time | 30.02 seconds |
| Started | Aug 29 08:48:09 AM UTC 24 |
| Finished | Aug 29 08:48:41 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712281579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1712281579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/35.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/35.alert_handler_sig_int_fail.3697625660 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 120534027 ps |
| CPU time | 14.33 seconds |
| Started | Aug 29 08:48:42 AM UTC 24 |
| Finished | Aug 29 08:48:58 AM UTC 24 |
| Peak memory | 262896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697625660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3697625660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/35.alert_handler_smoke.4067977652 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 354258158 ps |
| CPU time | 36.38 seconds |
| Started | Aug 29 08:47:35 AM UTC 24 |
| Finished | Aug 29 08:48:13 AM UTC 24 |
| Peak memory | 269376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067977652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.4067977652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/35.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all.1233208451 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 698788231396 ps |
| CPU time | 4350.21 seconds |
| Started | Aug 29 08:49:55 AM UTC 24 |
| Finished | Aug 29 10:03:13 AM UTC 24 |
| Peak memory | 321064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233208451 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all.1233208451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/35.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all_with_rand_reset.3439785181 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2866694296 ps |
| CPU time | 303.98 seconds |
| Started | Aug 29 08:50:26 AM UTC 24 |
| Finished | Aug 29 08:55:35 AM UTC 24 |
| Peak memory | 279612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3439785181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.a lert_handler_stress_all_with_rand_reset.3439785181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/36.alert_handler_entropy.1724531433 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 104216676968 ps |
| CPU time | 3319.51 seconds |
| Started | Aug 29 08:51:37 AM UTC 24 |
| Finished | Aug 29 09:47:34 AM UTC 24 |
| Peak memory | 304604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724531433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1724531433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/36.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_alert_accum.1846737716 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1911437140 ps |
| CPU time | 83.89 seconds |
| Started | Aug 29 08:51:23 AM UTC 24 |
| Finished | Aug 29 08:52:49 AM UTC 24 |
| Peak memory | 269276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846737716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1846737716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/36.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_intr_timeout.1578398059 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 581333144 ps |
| CPU time | 20.5 seconds |
| Started | Aug 29 08:51:23 AM UTC 24 |
| Finished | Aug 29 08:51:44 AM UTC 24 |
| Peak memory | 269052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578398059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1578398059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg.2603762874 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 246830213848 ps |
| CPU time | 3332.59 seconds |
| Started | Aug 29 08:51:49 AM UTC 24 |
| Finished | Aug 29 09:48:01 AM UTC 24 |
| Peak memory | 304936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603762874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2603762874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/36.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg_stub_clk.1473246841 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 29005541118 ps |
| CPU time | 2063.82 seconds |
| Started | Aug 29 08:51:52 AM UTC 24 |
| Finished | Aug 29 09:26:41 AM UTC 24 |
| Peak memory | 285504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473246841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1473246841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/36.alert_handler_ping_timeout.3636194439 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 52762159073 ps |
| CPU time | 758.39 seconds |
| Started | Aug 29 08:51:45 AM UTC 24 |
| Finished | Aug 29 09:04:33 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636194439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3636194439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_alerts.2255977001 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 229490983 ps |
| CPU time | 9.23 seconds |
| Started | Aug 29 08:51:08 AM UTC 24 |
| Finished | Aug 29 08:51:18 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255977001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2255977001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/36.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_classes.1364237187 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1887455756 ps |
| CPU time | 80.51 seconds |
| Started | Aug 29 08:51:14 AM UTC 24 |
| Finished | Aug 29 08:52:36 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364237187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1364237187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/36.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/36.alert_handler_sig_int_fail.1052015265 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 362171125 ps |
| CPU time | 44.44 seconds |
| Started | Aug 29 08:51:29 AM UTC 24 |
| Finished | Aug 29 08:52:15 AM UTC 24 |
| Peak memory | 269036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052015265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1052015265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/36.alert_handler_smoke.1280516871 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1256649609 ps |
| CPU time | 24.7 seconds |
| Started | Aug 29 08:50:40 AM UTC 24 |
| Finished | Aug 29 08:51:07 AM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280516871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1280516871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/36.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all.22473828 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 35764883641 ps |
| CPU time | 2378.6 seconds |
| Started | Aug 29 08:52:01 AM UTC 24 |
| Finished | Aug 29 09:32:07 AM UTC 24 |
| Peak memory | 304936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22473828 -assert nopostproc +UVM_TES TNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all.22473828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/36.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all_with_rand_reset.1525247097 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1827817815 ps |
| CPU time | 266.45 seconds |
| Started | Aug 29 08:52:04 AM UTC 24 |
| Finished | Aug 29 08:56:35 AM UTC 24 |
| Peak memory | 281456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1525247097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.a lert_handler_stress_all_with_rand_reset.1525247097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/37.alert_handler_entropy.3584278503 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 12988138629 ps |
| CPU time | 1114.18 seconds |
| Started | Aug 29 08:52:42 AM UTC 24 |
| Finished | Aug 29 09:11:30 AM UTC 24 |
| Peak memory | 295812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584278503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3584278503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/37.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_alert_accum.3300003523 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 4604563389 ps |
| CPU time | 171.46 seconds |
| Started | Aug 29 08:52:35 AM UTC 24 |
| Finished | Aug 29 08:55:29 AM UTC 24 |
| Peak memory | 268876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300003523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3300003523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/37.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_intr_timeout.1790588620 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 2433163771 ps |
| CPU time | 45.41 seconds |
| Started | Aug 29 08:52:35 AM UTC 24 |
| Finished | Aug 29 08:53:22 AM UTC 24 |
| Peak memory | 262868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790588620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1790588620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg.4162907567 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 25091482540 ps |
| CPU time | 1797.44 seconds |
| Started | Aug 29 08:52:53 AM UTC 24 |
| Finished | Aug 29 09:23:11 AM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162907567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.4162907567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/37.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg_stub_clk.3402844317 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 103152828616 ps |
| CPU time | 1399 seconds |
| Started | Aug 29 08:52:55 AM UTC 24 |
| Finished | Aug 29 09:16:30 AM UTC 24 |
| Peak memory | 285504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402844317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3402844317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/37.alert_handler_ping_timeout.3814292487 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 4710378586 ps |
| CPU time | 233.79 seconds |
| Started | Aug 29 08:52:53 AM UTC 24 |
| Finished | Aug 29 08:56:50 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814292487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3814292487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_alerts.644708951 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 226191318 ps |
| CPU time | 21.48 seconds |
| Started | Aug 29 08:52:10 AM UTC 24 |
| Finished | Aug 29 08:52:33 AM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644708951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.644708951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/37.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_classes.381472231 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 491528582 ps |
| CPU time | 34.02 seconds |
| Started | Aug 29 08:52:17 AM UTC 24 |
| Finished | Aug 29 08:52:52 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381472231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.381472231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/37.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/37.alert_handler_sig_int_fail.3384691625 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 2509602471 ps |
| CPU time | 33.01 seconds |
| Started | Aug 29 08:52:38 AM UTC 24 |
| Finished | Aug 29 08:53:12 AM UTC 24 |
| Peak memory | 262956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384691625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3384691625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/37.alert_handler_smoke.1153689646 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 644430222 ps |
| CPU time | 57.74 seconds |
| Started | Aug 29 08:52:04 AM UTC 24 |
| Finished | Aug 29 08:53:04 AM UTC 24 |
| Peak memory | 269376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153689646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1153689646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/37.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all.3007596841 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 811950005001 ps |
| CPU time | 4440.67 seconds |
| Started | Aug 29 08:53:05 AM UTC 24 |
| Finished | Aug 29 10:07:56 AM UTC 24 |
| Peak memory | 318944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007596841 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all.3007596841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/37.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/38.alert_handler_entropy.4079833122 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 10708685327 ps |
| CPU time | 1052.79 seconds |
| Started | Aug 29 08:53:49 AM UTC 24 |
| Finished | Aug 29 09:11:35 AM UTC 24 |
| Peak memory | 301880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079833122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.4079833122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/38.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_alert_accum.4029196229 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1888078137 ps |
| CPU time | 102.88 seconds |
| Started | Aug 29 08:53:34 AM UTC 24 |
| Finished | Aug 29 08:55:19 AM UTC 24 |
| Peak memory | 269076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029196229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.4029196229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/38.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_intr_timeout.2755189003 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 288549442 ps |
| CPU time | 23.26 seconds |
| Started | Aug 29 08:53:29 AM UTC 24 |
| Finished | Aug 29 08:53:53 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755189003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2755189003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg.3179770303 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 38959636457 ps |
| CPU time | 2323.45 seconds |
| Started | Aug 29 08:53:57 AM UTC 24 |
| Finished | Aug 29 09:33:08 AM UTC 24 |
| Peak memory | 304684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179770303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3179770303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/38.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg_stub_clk.732870712 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 26416240535 ps |
| CPU time | 2005.7 seconds |
| Started | Aug 29 08:54:02 AM UTC 24 |
| Finished | Aug 29 09:27:52 AM UTC 24 |
| Peak memory | 297864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732870712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.732870712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/38.alert_handler_ping_timeout.1743815986 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 20341711715 ps |
| CPU time | 302.7 seconds |
| Started | Aug 29 08:53:54 AM UTC 24 |
| Finished | Aug 29 08:59:01 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743815986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1743815986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_alerts.2467688426 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 896467192 ps |
| CPU time | 69.95 seconds |
| Started | Aug 29 08:53:20 AM UTC 24 |
| Finished | Aug 29 08:54:32 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467688426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2467688426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/38.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_classes.3230047427 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 283634312 ps |
| CPU time | 7.65 seconds |
| Started | Aug 29 08:53:23 AM UTC 24 |
| Finished | Aug 29 08:53:32 AM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230047427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3230047427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/38.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/38.alert_handler_sig_int_fail.3923816790 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 1575643657 ps |
| CPU time | 36.93 seconds |
| Started | Aug 29 08:53:38 AM UTC 24 |
| Finished | Aug 29 08:54:16 AM UTC 24 |
| Peak memory | 262892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923816790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3923816790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/38.alert_handler_smoke.1911769644 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 370322786 ps |
| CPU time | 18.53 seconds |
| Started | Aug 29 08:53:17 AM UTC 24 |
| Finished | Aug 29 08:53:37 AM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911769644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1911769644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/38.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all.3291506739 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 49096463122 ps |
| CPU time | 1412.38 seconds |
| Started | Aug 29 08:54:18 AM UTC 24 |
| Finished | Aug 29 09:18:07 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291506739 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all.3291506739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/38.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all_with_rand_reset.1144354548 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 5782604468 ps |
| CPU time | 233.36 seconds |
| Started | Aug 29 08:54:33 AM UTC 24 |
| Finished | Aug 29 08:58:30 AM UTC 24 |
| Peak memory | 279804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1144354548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.a lert_handler_stress_all_with_rand_reset.1144354548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/38.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/39.alert_handler_entropy.3807100493 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 256074447906 ps |
| CPU time | 2504.9 seconds |
| Started | Aug 29 08:56:09 AM UTC 24 |
| Finished | Aug 29 09:38:22 AM UTC 24 |
| Peak memory | 304680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807100493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3807100493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/39.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_alert_accum.1330310460 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 2101839692 ps |
| CPU time | 246.26 seconds |
| Started | Aug 29 08:55:59 AM UTC 24 |
| Finished | Aug 29 09:00:09 AM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330310460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1330310460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/39.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_intr_timeout.763311586 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 812310568 ps |
| CPU time | 74.64 seconds |
| Started | Aug 29 08:55:53 AM UTC 24 |
| Finished | Aug 29 08:57:09 AM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763311586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.763311586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg.2068479333 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 26809235298 ps |
| CPU time | 1660.9 seconds |
| Started | Aug 29 08:56:25 AM UTC 24 |
| Finished | Aug 29 09:24:25 AM UTC 24 |
| Peak memory | 285828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068479333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2068479333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/39.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg_stub_clk.802425296 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 74405077060 ps |
| CPU time | 1721.38 seconds |
| Started | Aug 29 08:56:25 AM UTC 24 |
| Finished | Aug 29 09:25:24 AM UTC 24 |
| Peak memory | 298120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802425296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.802425296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/39.alert_handler_ping_timeout.376192314 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 8996507800 ps |
| CPU time | 490.19 seconds |
| Started | Aug 29 08:56:22 AM UTC 24 |
| Finished | Aug 29 09:04:39 AM UTC 24 |
| Peak memory | 263036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376192314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.376192314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_alerts.1266592158 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 1780472291 ps |
| CPU time | 49.3 seconds |
| Started | Aug 29 08:55:31 AM UTC 24 |
| Finished | Aug 29 08:56:22 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266592158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1266592158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/39.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_classes.2614550864 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 2312702116 ps |
| CPU time | 59.91 seconds |
| Started | Aug 29 08:55:36 AM UTC 24 |
| Finished | Aug 29 08:56:38 AM UTC 24 |
| Peak memory | 269212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614550864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2614550864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/39.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/39.alert_handler_sig_int_fail.1480345135 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1795327423 ps |
| CPU time | 16.86 seconds |
| Started | Aug 29 08:56:04 AM UTC 24 |
| Finished | Aug 29 08:56:22 AM UTC 24 |
| Peak memory | 263224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480345135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1480345135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/39.alert_handler_smoke.2416891622 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 417956831 ps |
| CPU time | 35.9 seconds |
| Started | Aug 29 08:55:20 AM UTC 24 |
| Finished | Aug 29 08:55:57 AM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416891622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2416891622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/39.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/4.alert_handler_alert_accum_saturation.2559963246 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 16036609 ps |
| CPU time | 3.93 seconds |
| Started | Aug 29 07:43:59 AM UTC 24 |
| Finished | Aug 29 07:44:04 AM UTC 24 |
| Peak memory | 263504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559963246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2559963246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy.1153219832 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 187757348846 ps |
| CPU time | 3355.71 seconds |
| Started | Aug 29 07:43:27 AM UTC 24 |
| Finished | Aug 29 08:40:02 AM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153219832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1153219832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy_stress.3979247367 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 817707697 ps |
| CPU time | 17.53 seconds |
| Started | Aug 29 07:43:51 AM UTC 24 |
| Finished | Aug 29 07:44:09 AM UTC 24 |
| Peak memory | 262912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979247367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3979247367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_alert_accum.1900245999 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1487941725 ps |
| CPU time | 29.57 seconds |
| Started | Aug 29 07:43:19 AM UTC 24 |
| Finished | Aug 29 07:43:50 AM UTC 24 |
| Peak memory | 269072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900245999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1900245999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg.2326407795 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 163918052513 ps |
| CPU time | 3358.29 seconds |
| Started | Aug 29 07:43:32 AM UTC 24 |
| Finished | Aug 29 08:40:10 AM UTC 24 |
| Peak memory | 295804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326407795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2326407795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg_stub_clk.3679829945 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 13620514117 ps |
| CPU time | 1205.62 seconds |
| Started | Aug 29 07:43:38 AM UTC 24 |
| Finished | Aug 29 08:03:58 AM UTC 24 |
| Peak memory | 301956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679829945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3679829945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/4.alert_handler_ping_timeout.4224871863 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10006865208 ps |
| CPU time | 104.08 seconds |
| Started | Aug 29 07:43:31 AM UTC 24 |
| Finished | Aug 29 07:45:17 AM UTC 24 |
| Peak memory | 262968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224871863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.4224871863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_alerts.3238471844 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2569370854 ps |
| CPU time | 60.58 seconds |
| Started | Aug 29 07:43:02 AM UTC 24 |
| Finished | Aug 29 07:44:05 AM UTC 24 |
| Peak memory | 262956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238471844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3238471844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_classes.927954693 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 287647250 ps |
| CPU time | 28.32 seconds |
| Started | Aug 29 07:43:08 AM UTC 24 |
| Finished | Aug 29 07:43:37 AM UTC 24 |
| Peak memory | 269244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927954693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.927954693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/4.alert_handler_sec_cm.2464647423 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 929396676 ps |
| CPU time | 24.36 seconds |
| Started | Aug 29 07:44:06 AM UTC 24 |
| Finished | Aug 29 07:44:32 AM UTC 24 |
| Peak memory | 297456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464647423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2464647423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/4.alert_handler_sig_int_fail.3455268311 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 58437856 ps |
| CPU time | 6.9 seconds |
| Started | Aug 29 07:43:23 AM UTC 24 |
| Finished | Aug 29 07:43:31 AM UTC 24 |
| Peak memory | 265284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455268311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3455268311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/4.alert_handler_smoke.2864371386 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 928954029 ps |
| CPU time | 75.84 seconds |
| Started | Aug 29 07:43:00 AM UTC 24 |
| Finished | Aug 29 07:44:18 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864371386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2864371386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/4.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/40.alert_handler_entropy.967999083 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 105186505403 ps |
| CPU time | 2022.14 seconds |
| Started | Aug 29 08:57:11 AM UTC 24 |
| Finished | Aug 29 09:31:17 AM UTC 24 |
| Peak memory | 297788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967999083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.967999083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/40.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_alert_accum.629269253 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 17558716188 ps |
| CPU time | 358.35 seconds |
| Started | Aug 29 08:57:05 AM UTC 24 |
| Finished | Aug 29 09:03:09 AM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629269253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.629269253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/40.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_intr_timeout.3254477510 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 931568841 ps |
| CPU time | 26.72 seconds |
| Started | Aug 29 08:56:57 AM UTC 24 |
| Finished | Aug 29 08:57:25 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254477510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3254477510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg.1441016926 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 84943284175 ps |
| CPU time | 1357.14 seconds |
| Started | Aug 29 08:57:28 AM UTC 24 |
| Finished | Aug 29 09:20:22 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441016926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1441016926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/40.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg_stub_clk.2701725711 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 88941360418 ps |
| CPU time | 2994.85 seconds |
| Started | Aug 29 08:57:45 AM UTC 24 |
| Finished | Aug 29 09:48:17 AM UTC 24 |
| Peak memory | 300512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701725711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2701725711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/40.alert_handler_ping_timeout.3768297135 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 22503797956 ps |
| CPU time | 255.39 seconds |
| Started | Aug 29 08:57:28 AM UTC 24 |
| Finished | Aug 29 09:01:47 AM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768297135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3768297135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_alerts.2633833565 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 527096424 ps |
| CPU time | 53.34 seconds |
| Started | Aug 29 08:56:53 AM UTC 24 |
| Finished | Aug 29 08:57:48 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633833565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2633833565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/40.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_classes.587095820 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 3799875483 ps |
| CPU time | 49.11 seconds |
| Started | Aug 29 08:56:53 AM UTC 24 |
| Finished | Aug 29 08:57:43 AM UTC 24 |
| Peak memory | 263036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587095820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.587095820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/40.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/40.alert_handler_sig_int_fail.2116385720 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 15095166919 ps |
| CPU time | 61.85 seconds |
| Started | Aug 29 08:57:11 AM UTC 24 |
| Finished | Aug 29 08:58:14 AM UTC 24 |
| Peak memory | 269432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116385720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2116385720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/40.alert_handler_smoke.835966845 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 120210920 ps |
| CPU time | 13.8 seconds |
| Started | Aug 29 08:56:40 AM UTC 24 |
| Finished | Aug 29 08:56:55 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835966845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.835966845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/40.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all.2131558656 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 13590972893 ps |
| CPU time | 1480.15 seconds |
| Started | Aug 29 08:57:50 AM UTC 24 |
| Finished | Aug 29 09:22:47 AM UTC 24 |
| Peak memory | 302024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131558656 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all.2131558656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/40.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/41.alert_handler_entropy.1834857728 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 8451920548 ps |
| CPU time | 883.37 seconds |
| Started | Aug 29 08:59:09 AM UTC 24 |
| Finished | Aug 29 09:14:04 AM UTC 24 |
| Peak memory | 279356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834857728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1834857728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/41.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_alert_accum.1787273817 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 7986203397 ps |
| CPU time | 318.19 seconds |
| Started | Aug 29 08:59:03 AM UTC 24 |
| Finished | Aug 29 09:04:26 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787273817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1787273817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/41.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_intr_timeout.3331789921 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 96217821 ps |
| CPU time | 3.9 seconds |
| Started | Aug 29 08:59:03 AM UTC 24 |
| Finished | Aug 29 08:59:08 AM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331789921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3331789921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg.4080550862 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 41495754305 ps |
| CPU time | 1236.65 seconds |
| Started | Aug 29 08:59:16 AM UTC 24 |
| Finished | Aug 29 09:20:08 AM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080550862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.4080550862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/41.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg_stub_clk.3409936643 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 23209947841 ps |
| CPU time | 1578.87 seconds |
| Started | Aug 29 08:59:25 AM UTC 24 |
| Finished | Aug 29 09:26:05 AM UTC 24 |
| Peak memory | 302280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409936643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3409936643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/41.alert_handler_ping_timeout.1069382042 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 11742049601 ps |
| CPU time | 555.53 seconds |
| Started | Aug 29 08:59:09 AM UTC 24 |
| Finished | Aug 29 09:08:31 AM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069382042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1069382042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_alerts.650114566 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 3382349719 ps |
| CPU time | 41.66 seconds |
| Started | Aug 29 08:58:40 AM UTC 24 |
| Finished | Aug 29 08:59:23 AM UTC 24 |
| Peak memory | 269176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650114566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.650114566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/41.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_classes.1856320047 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 890572461 ps |
| CPU time | 18.91 seconds |
| Started | Aug 29 08:58:40 AM UTC 24 |
| Finished | Aug 29 08:59:00 AM UTC 24 |
| Peak memory | 269404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856320047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1856320047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/41.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/41.alert_handler_sig_int_fail.1453311226 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 284010708 ps |
| CPU time | 23.33 seconds |
| Started | Aug 29 08:59:05 AM UTC 24 |
| Finished | Aug 29 08:59:29 AM UTC 24 |
| Peak memory | 262896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453311226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1453311226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/41.alert_handler_smoke.1998478050 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 91619372 ps |
| CPU time | 6.14 seconds |
| Started | Aug 29 08:58:32 AM UTC 24 |
| Finished | Aug 29 08:58:40 AM UTC 24 |
| Peak memory | 265024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998478050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1998478050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/41.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all.51663899 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 186787478067 ps |
| CPU time | 3247.63 seconds |
| Started | Aug 29 08:59:31 AM UTC 24 |
| Finished | Aug 29 09:54:16 AM UTC 24 |
| Peak memory | 304936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51663899 -assert nopostproc +UVM_TES TNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all.51663899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/41.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_alert_accum.2561783329 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 6766940904 ps |
| CPU time | 297.17 seconds |
| Started | Aug 29 09:00:52 AM UTC 24 |
| Finished | Aug 29 09:05:53 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561783329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2561783329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/42.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_intr_timeout.2525600516 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1981265729 ps |
| CPU time | 82.03 seconds |
| Started | Aug 29 09:00:41 AM UTC 24 |
| Finished | Aug 29 09:02:05 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525600516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2525600516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg.1052398377 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 97459767649 ps |
| CPU time | 1635.23 seconds |
| Started | Aug 29 09:01:49 AM UTC 24 |
| Finished | Aug 29 09:29:23 AM UTC 24 |
| Peak memory | 279356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052398377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1052398377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/42.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg_stub_clk.3200582986 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 99798192104 ps |
| CPU time | 1618.3 seconds |
| Started | Aug 29 09:02:07 AM UTC 24 |
| Finished | Aug 29 09:29:23 AM UTC 24 |
| Peak memory | 281408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200582986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3200582986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/42.alert_handler_ping_timeout.2513955909 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 23750479134 ps |
| CPU time | 496.31 seconds |
| Started | Aug 29 09:01:43 AM UTC 24 |
| Finished | Aug 29 09:10:06 AM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513955909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2513955909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_alerts.1855894779 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 28113374 ps |
| CPU time | 7.32 seconds |
| Started | Aug 29 09:00:11 AM UTC 24 |
| Finished | Aug 29 09:00:19 AM UTC 24 |
| Peak memory | 264948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855894779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1855894779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/42.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_classes.1253437675 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 758740876 ps |
| CPU time | 28.57 seconds |
| Started | Aug 29 09:00:21 AM UTC 24 |
| Finished | Aug 29 09:00:50 AM UTC 24 |
| Peak memory | 262912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253437675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1253437675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/42.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/42.alert_handler_sig_int_fail.3352070307 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 926151540 ps |
| CPU time | 40.74 seconds |
| Started | Aug 29 09:00:57 AM UTC 24 |
| Finished | Aug 29 09:01:39 AM UTC 24 |
| Peak memory | 262968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352070307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3352070307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/42.alert_handler_smoke.3126399756 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 2526951982 ps |
| CPU time | 39.16 seconds |
| Started | Aug 29 08:59:58 AM UTC 24 |
| Finished | Aug 29 09:00:38 AM UTC 24 |
| Peak memory | 262968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126399756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3126399756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/42.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all.4174057882 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 8331341105 ps |
| CPU time | 221.71 seconds |
| Started | Aug 29 09:02:17 AM UTC 24 |
| Finished | Aug 29 09:06:02 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174057882 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all.4174057882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/42.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all_with_rand_reset.3356398751 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 15155079122 ps |
| CPU time | 472.79 seconds |
| Started | Aug 29 09:02:57 AM UTC 24 |
| Finished | Aug 29 09:10:56 AM UTC 24 |
| Peak memory | 283572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3356398751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.a lert_handler_stress_all_with_rand_reset.3356398751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/42.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/43.alert_handler_entropy.3653714304 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 12159492172 ps |
| CPU time | 1240.19 seconds |
| Started | Aug 29 09:04:21 AM UTC 24 |
| Finished | Aug 29 09:25:17 AM UTC 24 |
| Peak memory | 298116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653714304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3653714304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/43.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_alert_accum.2472717084 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 3984278280 ps |
| CPU time | 163.3 seconds |
| Started | Aug 29 09:03:47 AM UTC 24 |
| Finished | Aug 29 09:06:33 AM UTC 24 |
| Peak memory | 269436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472717084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2472717084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/43.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_intr_timeout.2295872674 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 1999179393 ps |
| CPU time | 21.18 seconds |
| Started | Aug 29 09:03:46 AM UTC 24 |
| Finished | Aug 29 09:04:09 AM UTC 24 |
| Peak memory | 269308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295872674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2295872674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg.1783590421 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 85672573293 ps |
| CPU time | 1436.9 seconds |
| Started | Aug 29 09:04:35 AM UTC 24 |
| Finished | Aug 29 09:28:49 AM UTC 24 |
| Peak memory | 285576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783590421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1783590421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/43.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg_stub_clk.3259177060 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 231655125226 ps |
| CPU time | 2230.73 seconds |
| Started | Aug 29 09:04:42 AM UTC 24 |
| Finished | Aug 29 09:42:18 AM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259177060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3259177060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/43.alert_handler_ping_timeout.1172687514 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 5096542089 ps |
| CPU time | 303.76 seconds |
| Started | Aug 29 09:04:27 AM UTC 24 |
| Finished | Aug 29 09:09:36 AM UTC 24 |
| Peak memory | 269448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172687514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1172687514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_alerts.2527668714 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 240495663 ps |
| CPU time | 19.21 seconds |
| Started | Aug 29 09:03:24 AM UTC 24 |
| Finished | Aug 29 09:03:44 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527668714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2527668714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/43.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_classes.3636618737 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 993237143 ps |
| CPU time | 84.67 seconds |
| Started | Aug 29 09:03:30 AM UTC 24 |
| Finished | Aug 29 09:04:56 AM UTC 24 |
| Peak memory | 262916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636618737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3636618737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/43.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/43.alert_handler_sig_int_fail.1909801302 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 1832467133 ps |
| CPU time | 72.85 seconds |
| Started | Aug 29 09:04:11 AM UTC 24 |
| Finished | Aug 29 09:05:26 AM UTC 24 |
| Peak memory | 269036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909801302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1909801302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/43.alert_handler_smoke.4046423224 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 121553283 ps |
| CPU time | 11.29 seconds |
| Started | Aug 29 09:03:11 AM UTC 24 |
| Finished | Aug 29 09:03:23 AM UTC 24 |
| Peak memory | 269376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046423224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.4046423224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/43.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all.1074930108 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 4171093662 ps |
| CPU time | 127.51 seconds |
| Started | Aug 29 09:04:42 AM UTC 24 |
| Finished | Aug 29 09:06:52 AM UTC 24 |
| Peak memory | 269192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074930108 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all.1074930108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/43.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all_with_rand_reset.864230318 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 5299074047 ps |
| CPU time | 107.52 seconds |
| Started | Aug 29 09:04:58 AM UTC 24 |
| Finished | Aug 29 09:06:48 AM UTC 24 |
| Peak memory | 279476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=864230318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.al ert_handler_stress_all_with_rand_reset.864230318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/44.alert_handler_entropy.3243475527 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 14845714637 ps |
| CPU time | 1529.62 seconds |
| Started | Aug 29 09:06:04 AM UTC 24 |
| Finished | Aug 29 09:31:52 AM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243475527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3243475527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/44.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_alert_accum.1094078638 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 10040064920 ps |
| CPU time | 198.21 seconds |
| Started | Aug 29 09:05:57 AM UTC 24 |
| Finished | Aug 29 09:09:18 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094078638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1094078638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/44.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_intr_timeout.1698229636 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2072401468 ps |
| CPU time | 42.97 seconds |
| Started | Aug 29 09:05:49 AM UTC 24 |
| Finished | Aug 29 09:06:33 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698229636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1698229636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg.1935143717 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 149856225665 ps |
| CPU time | 1571.35 seconds |
| Started | Aug 29 09:06:22 AM UTC 24 |
| Finished | Aug 29 09:32:52 AM UTC 24 |
| Peak memory | 285832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935143717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1935143717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/44.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg_stub_clk.2509649892 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 9089298565 ps |
| CPU time | 944.93 seconds |
| Started | Aug 29 09:06:27 AM UTC 24 |
| Finished | Aug 29 09:22:23 AM UTC 24 |
| Peak memory | 285832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509649892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2509649892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/44.alert_handler_ping_timeout.1850434115 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 23170214647 ps |
| CPU time | 254.35 seconds |
| Started | Aug 29 09:06:16 AM UTC 24 |
| Finished | Aug 29 09:10:34 AM UTC 24 |
| Peak memory | 269448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850434115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1850434115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_alerts.3445546665 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 218067560 ps |
| CPU time | 17.32 seconds |
| Started | Aug 29 09:05:28 AM UTC 24 |
| Finished | Aug 29 09:05:47 AM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445546665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3445546665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/44.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_classes.1826008486 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 1078383703 ps |
| CPU time | 24.69 seconds |
| Started | Aug 29 09:05:49 AM UTC 24 |
| Finished | Aug 29 09:06:15 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826008486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1826008486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/44.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/44.alert_handler_sig_int_fail.2962054296 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 774149862 ps |
| CPU time | 67.16 seconds |
| Started | Aug 29 09:05:57 AM UTC 24 |
| Finished | Aug 29 09:07:06 AM UTC 24 |
| Peak memory | 269036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962054296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2962054296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/44.alert_handler_smoke.503939697 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 3368156982 ps |
| CPU time | 81.24 seconds |
| Started | Aug 29 09:05:14 AM UTC 24 |
| Finished | Aug 29 09:06:37 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503939697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.503939697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/44.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all.3905031267 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 227057329811 ps |
| CPU time | 3049.44 seconds |
| Started | Aug 29 09:06:34 AM UTC 24 |
| Finished | Aug 29 09:58:00 AM UTC 24 |
| Peak memory | 317288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905031267 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all.3905031267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/44.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all_with_rand_reset.2110406171 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 38230029242 ps |
| CPU time | 410.44 seconds |
| Started | Aug 29 09:06:34 AM UTC 24 |
| Finished | Aug 29 09:13:30 AM UTC 24 |
| Peak memory | 285616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2110406171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.a lert_handler_stress_all_with_rand_reset.2110406171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/45.alert_handler_entropy.2054120242 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 123797443954 ps |
| CPU time | 2115.4 seconds |
| Started | Aug 29 09:07:08 AM UTC 24 |
| Finished | Aug 29 09:42:50 AM UTC 24 |
| Peak memory | 305000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054120242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2054120242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/45.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_alert_accum.862134668 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 3602799523 ps |
| CPU time | 217.97 seconds |
| Started | Aug 29 09:06:56 AM UTC 24 |
| Finished | Aug 29 09:10:37 AM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862134668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.862134668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/45.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_intr_timeout.3004755328 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 641558100 ps |
| CPU time | 57.11 seconds |
| Started | Aug 29 09:06:56 AM UTC 24 |
| Finished | Aug 29 09:07:55 AM UTC 24 |
| Peak memory | 269040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004755328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3004755328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg_stub_clk.817900805 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 90904532248 ps |
| CPU time | 2266.85 seconds |
| Started | Aug 29 09:07:45 AM UTC 24 |
| Finished | Aug 29 09:45:57 AM UTC 24 |
| Peak memory | 302560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817900805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.817900805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/45.alert_handler_ping_timeout.3603419910 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 20808769716 ps |
| CPU time | 264.07 seconds |
| Started | Aug 29 09:07:19 AM UTC 24 |
| Finished | Aug 29 09:11:47 AM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603419910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3603419910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_alerts.1976274638 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 101140234 ps |
| CPU time | 15.88 seconds |
| Started | Aug 29 09:06:47 AM UTC 24 |
| Finished | Aug 29 09:07:04 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976274638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1976274638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/45.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_classes.200681631 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 7800177228 ps |
| CPU time | 75.03 seconds |
| Started | Aug 29 09:06:49 AM UTC 24 |
| Finished | Aug 29 09:08:06 AM UTC 24 |
| Peak memory | 262968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200681631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.200681631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/45.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/45.alert_handler_sig_int_fail.1088759313 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 324380073 ps |
| CPU time | 11.13 seconds |
| Started | Aug 29 09:07:05 AM UTC 24 |
| Finished | Aug 29 09:07:17 AM UTC 24 |
| Peak memory | 264944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088759313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1088759313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/45.alert_handler_smoke.1694687946 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 541399565 ps |
| CPU time | 38.98 seconds |
| Started | Aug 29 09:06:38 AM UTC 24 |
| Finished | Aug 29 09:07:19 AM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694687946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1694687946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/45.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/46.alert_handler_entropy.1224419452 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 13711838831 ps |
| CPU time | 1427.39 seconds |
| Started | Aug 29 09:09:20 AM UTC 24 |
| Finished | Aug 29 09:33:25 AM UTC 24 |
| Peak memory | 300164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224419452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1224419452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/46.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_alert_accum.1346919481 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 9964295311 ps |
| CPU time | 92.96 seconds |
| Started | Aug 29 09:09:11 AM UTC 24 |
| Finished | Aug 29 09:10:46 AM UTC 24 |
| Peak memory | 269212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346919481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1346919481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/46.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_intr_timeout.3742200179 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 86940953 ps |
| CPU time | 11.08 seconds |
| Started | Aug 29 09:08:57 AM UTC 24 |
| Finished | Aug 29 09:09:09 AM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742200179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3742200179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg.1036042488 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 73335321931 ps |
| CPU time | 1370.52 seconds |
| Started | Aug 29 09:09:35 AM UTC 24 |
| Finished | Aug 29 09:32:42 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036042488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1036042488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/46.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg_stub_clk.2876992461 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 12820061091 ps |
| CPU time | 934.32 seconds |
| Started | Aug 29 09:09:37 AM UTC 24 |
| Finished | Aug 29 09:25:23 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876992461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2876992461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/46.alert_handler_ping_timeout.1785241339 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 37051170181 ps |
| CPU time | 451.49 seconds |
| Started | Aug 29 09:09:30 AM UTC 24 |
| Finished | Aug 29 09:17:07 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785241339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1785241339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_alerts.1451951910 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 277877868 ps |
| CPU time | 19.65 seconds |
| Started | Aug 29 09:08:33 AM UTC 24 |
| Finished | Aug 29 09:08:54 AM UTC 24 |
| Peak memory | 269436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451951910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1451951910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/46.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_classes.442875935 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 172909706 ps |
| CPU time | 18.82 seconds |
| Started | Aug 29 09:08:54 AM UTC 24 |
| Finished | Aug 29 09:09:14 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442875935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.442875935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/46.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/46.alert_handler_sig_int_fail.2628653082 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1926767146 ps |
| CPU time | 22.54 seconds |
| Started | Aug 29 09:09:16 AM UTC 24 |
| Finished | Aug 29 09:09:40 AM UTC 24 |
| Peak memory | 263224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628653082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2628653082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/46.alert_handler_smoke.2252390621 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 734097978 ps |
| CPU time | 63.62 seconds |
| Started | Aug 29 09:08:22 AM UTC 24 |
| Finished | Aug 29 09:09:27 AM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252390621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2252390621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/46.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all.4255187213 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 34023269275 ps |
| CPU time | 2210.24 seconds |
| Started | Aug 29 09:09:43 AM UTC 24 |
| Finished | Aug 29 09:46:59 AM UTC 24 |
| Peak memory | 288300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255187213 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all.4255187213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/46.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/47.alert_handler_entropy.896787212 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 296480321223 ps |
| CPU time | 2216.79 seconds |
| Started | Aug 29 09:10:45 AM UTC 24 |
| Finished | Aug 29 09:48:09 AM UTC 24 |
| Peak memory | 304876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896787212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.896787212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/47.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_alert_accum.2265928267 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 8116671930 ps |
| CPU time | 55.87 seconds |
| Started | Aug 29 09:10:37 AM UTC 24 |
| Finished | Aug 29 09:11:34 AM UTC 24 |
| Peak memory | 269108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265928267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2265928267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/47.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_intr_timeout.2034960112 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 804060145 ps |
| CPU time | 26.92 seconds |
| Started | Aug 29 09:10:26 AM UTC 24 |
| Finished | Aug 29 09:10:54 AM UTC 24 |
| Peak memory | 262896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034960112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2034960112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg.2786113735 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 37186284281 ps |
| CPU time | 1643.89 seconds |
| Started | Aug 29 09:10:55 AM UTC 24 |
| Finished | Aug 29 09:38:39 AM UTC 24 |
| Peak memory | 301960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786113735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2786113735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/47.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg_stub_clk.871902357 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 21905280946 ps |
| CPU time | 1510.01 seconds |
| Started | Aug 29 09:10:57 AM UTC 24 |
| Finished | Aug 29 09:36:27 AM UTC 24 |
| Peak memory | 279688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871902357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.871902357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/47.alert_handler_ping_timeout.2701891245 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 8381443587 ps |
| CPU time | 471.07 seconds |
| Started | Aug 29 09:10:48 AM UTC 24 |
| Finished | Aug 29 09:18:46 AM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701891245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2701891245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_alerts.3136353470 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 85225615 ps |
| CPU time | 14.46 seconds |
| Started | Aug 29 09:10:08 AM UTC 24 |
| Finished | Aug 29 09:10:24 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136353470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3136353470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/47.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_classes.3186252104 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 373313748 ps |
| CPU time | 21.41 seconds |
| Started | Aug 29 09:10:20 AM UTC 24 |
| Finished | Aug 29 09:10:43 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186252104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3186252104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/47.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/47.alert_handler_sig_int_fail.1469663560 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 86301022 ps |
| CPU time | 10.86 seconds |
| Started | Aug 29 09:10:41 AM UTC 24 |
| Finished | Aug 29 09:10:53 AM UTC 24 |
| Peak memory | 262892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469663560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1469663560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/47.alert_handler_smoke.2277164504 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 313787262 ps |
| CPU time | 10.35 seconds |
| Started | Aug 29 09:10:06 AM UTC 24 |
| Finished | Aug 29 09:10:18 AM UTC 24 |
| Peak memory | 262976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277164504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2277164504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/47.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all.2899076293 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 112438366372 ps |
| CPU time | 1028.21 seconds |
| Started | Aug 29 09:11:00 AM UTC 24 |
| Finished | Aug 29 09:28:21 AM UTC 24 |
| Peak memory | 285572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899076293 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all.2899076293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/47.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/48.alert_handler_entropy.2076738640 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 49758906214 ps |
| CPU time | 1404.99 seconds |
| Started | Aug 29 09:12:01 AM UTC 24 |
| Finished | Aug 29 09:35:43 AM UTC 24 |
| Peak memory | 302212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076738640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2076738640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/48.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_alert_accum.1707112780 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 6675052958 ps |
| CPU time | 291.92 seconds |
| Started | Aug 29 09:11:40 AM UTC 24 |
| Finished | Aug 29 09:16:36 AM UTC 24 |
| Peak memory | 269212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707112780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1707112780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/48.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_intr_timeout.3893516389 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 736121000 ps |
| CPU time | 71.82 seconds |
| Started | Aug 29 09:11:40 AM UTC 24 |
| Finished | Aug 29 09:12:53 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893516389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3893516389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg.1076682788 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 559054701838 ps |
| CPU time | 2528.75 seconds |
| Started | Aug 29 09:12:45 AM UTC 24 |
| Finished | Aug 29 09:55:24 AM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076682788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1076682788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/48.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg_stub_clk.1587781532 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 125808622349 ps |
| CPU time | 1999.42 seconds |
| Started | Aug 29 09:12:53 AM UTC 24 |
| Finished | Aug 29 09:46:35 AM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587781532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1587781532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/48.alert_handler_ping_timeout.2598848832 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 19168025710 ps |
| CPU time | 463 seconds |
| Started | Aug 29 09:12:19 AM UTC 24 |
| Finished | Aug 29 09:20:08 AM UTC 24 |
| Peak memory | 269192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598848832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2598848832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_alerts.4292498086 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 1674506667 ps |
| CPU time | 77.28 seconds |
| Started | Aug 29 09:11:33 AM UTC 24 |
| Finished | Aug 29 09:12:52 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292498086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.4292498086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/48.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_classes.4142862607 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 3218300074 ps |
| CPU time | 66.18 seconds |
| Started | Aug 29 09:11:35 AM UTC 24 |
| Finished | Aug 29 09:12:43 AM UTC 24 |
| Peak memory | 269180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142862607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.4142862607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/48.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/48.alert_handler_sig_int_fail.2208890069 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 156985740 ps |
| CPU time | 27.32 seconds |
| Started | Aug 29 09:11:49 AM UTC 24 |
| Finished | Aug 29 09:12:18 AM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208890069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2208890069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/48.alert_handler_smoke.882396606 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 236433357 ps |
| CPU time | 13.97 seconds |
| Started | Aug 29 09:11:18 AM UTC 24 |
| Finished | Aug 29 09:11:33 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882396606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.882396606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/48.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all_with_rand_reset.3883990646 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1968435682 ps |
| CPU time | 206.51 seconds |
| Started | Aug 29 09:13:33 AM UTC 24 |
| Finished | Aug 29 09:17:03 AM UTC 24 |
| Peak memory | 279484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3883990646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.a lert_handler_stress_all_with_rand_reset.3883990646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/49.alert_handler_entropy.1321991869 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 186334337130 ps |
| CPU time | 1184.97 seconds |
| Started | Aug 29 09:15:32 AM UTC 24 |
| Finished | Aug 29 09:35:32 AM UTC 24 |
| Peak memory | 283452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321991869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1321991869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/49.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_alert_accum.972583348 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 138378368 ps |
| CPU time | 8.86 seconds |
| Started | Aug 29 09:15:20 AM UTC 24 |
| Finished | Aug 29 09:15:30 AM UTC 24 |
| Peak memory | 265280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972583348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.972583348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/49.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_intr_timeout.2811842947 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 267018202 ps |
| CPU time | 43.41 seconds |
| Started | Aug 29 09:14:39 AM UTC 24 |
| Finished | Aug 29 09:15:24 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811842947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2811842947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg_stub_clk.2112672318 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 50438367737 ps |
| CPU time | 2786.55 seconds |
| Started | Aug 29 09:15:50 AM UTC 24 |
| Finished | Aug 29 10:02:47 AM UTC 24 |
| Peak memory | 304608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112672318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2112672318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/49.alert_handler_ping_timeout.1945897 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 36574127479 ps |
| CPU time | 483.94 seconds |
| Started | Aug 29 09:15:35 AM UTC 24 |
| Finished | Aug 29 09:23:46 AM UTC 24 |
| Peak memory | 269116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test + UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1945897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_alerts.936412595 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 58479693 ps |
| CPU time | 4.6 seconds |
| Started | Aug 29 09:14:06 AM UTC 24 |
| Finished | Aug 29 09:14:12 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=936412595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.936412595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/49.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_classes.296079856 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 1002738165 ps |
| CPU time | 21.81 seconds |
| Started | Aug 29 09:14:13 AM UTC 24 |
| Finished | Aug 29 09:14:36 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296079856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.296079856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/49.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/49.alert_handler_sig_int_fail.2273849033 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 198567070 ps |
| CPU time | 18.62 seconds |
| Started | Aug 29 09:15:26 AM UTC 24 |
| Finished | Aug 29 09:15:45 AM UTC 24 |
| Peak memory | 262896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273849033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2273849033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/49.alert_handler_smoke.3950821790 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 1289919958 ps |
| CPU time | 105.52 seconds |
| Started | Aug 29 09:13:45 AM UTC 24 |
| Finished | Aug 29 09:15:33 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950821790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3950821790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/49.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/5.alert_handler_alert_accum_saturation.3910957015 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 14608484 ps |
| CPU time | 2.81 seconds |
| Started | Aug 29 07:45:54 AM UTC 24 |
| Finished | Aug 29 07:45:58 AM UTC 24 |
| Peak memory | 263500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910957015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3910957015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy_stress.2698510109 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3706030495 ps |
| CPU time | 11.88 seconds |
| Started | Aug 29 07:45:43 AM UTC 24 |
| Finished | Aug 29 07:45:56 AM UTC 24 |
| Peak memory | 263176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698510109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2698510109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_alert_accum.987078097 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1663357207 ps |
| CPU time | 136.65 seconds |
| Started | Aug 29 07:44:58 AM UTC 24 |
| Finished | Aug 29 07:47:17 AM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987078097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.987078097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_intr_timeout.730231062 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 792897428 ps |
| CPU time | 62.5 seconds |
| Started | Aug 29 07:44:38 AM UTC 24 |
| Finished | Aug 29 07:45:42 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730231062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.730231062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg.2045697316 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 36995567592 ps |
| CPU time | 1030.16 seconds |
| Started | Aug 29 07:45:18 AM UTC 24 |
| Finished | Aug 29 08:02:41 AM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045697316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2045697316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_alerts.3218815729 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 342996245 ps |
| CPU time | 36.46 seconds |
| Started | Aug 29 07:44:19 AM UTC 24 |
| Finished | Aug 29 07:44:57 AM UTC 24 |
| Peak memory | 269372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218815729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3218815729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_classes.2613607521 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 422139169 ps |
| CPU time | 32.82 seconds |
| Started | Aug 29 07:44:32 AM UTC 24 |
| Finished | Aug 29 07:45:07 AM UTC 24 |
| Peak memory | 269148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613607521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2613607521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/5.alert_handler_sig_int_fail.3290642645 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 295736485 ps |
| CPU time | 45.59 seconds |
| Started | Aug 29 07:45:06 AM UTC 24 |
| Finished | Aug 29 07:45:53 AM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290642645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3290642645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/5.alert_handler_smoke.357191581 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 668069028 ps |
| CPU time | 59.94 seconds |
| Started | Aug 29 07:44:10 AM UTC 24 |
| Finished | Aug 29 07:45:12 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357191581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.357191581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/5.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/6.alert_handler_alert_accum_saturation.2571767725 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 40882324 ps |
| CPU time | 5.83 seconds |
| Started | Aug 29 07:48:03 AM UTC 24 |
| Finished | Aug 29 07:48:10 AM UTC 24 |
| Peak memory | 263180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571767725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2571767725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy.661823831 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 40517652035 ps |
| CPU time | 2558.73 seconds |
| Started | Aug 29 07:46:28 AM UTC 24 |
| Finished | Aug 29 08:29:39 AM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661823831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.661823831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy_stress.2686613702 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 9524549597 ps |
| CPU time | 94.82 seconds |
| Started | Aug 29 07:47:20 AM UTC 24 |
| Finished | Aug 29 07:48:57 AM UTC 24 |
| Peak memory | 263048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686613702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2686613702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_alert_accum.2293701044 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1876869196 ps |
| CPU time | 165.8 seconds |
| Started | Aug 29 07:46:15 AM UTC 24 |
| Finished | Aug 29 07:49:04 AM UTC 24 |
| Peak memory | 269468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293701044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2293701044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_intr_timeout.820390051 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 3636150832 ps |
| CPU time | 79.57 seconds |
| Started | Aug 29 07:46:15 AM UTC 24 |
| Finished | Aug 29 07:47:37 AM UTC 24 |
| Peak memory | 269212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820390051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.820390051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg_stub_clk.2418489188 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 135754444102 ps |
| CPU time | 976.49 seconds |
| Started | Aug 29 07:47:18 AM UTC 24 |
| Finished | Aug 29 08:03:47 AM UTC 24 |
| Peak memory | 295812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418489188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2418489188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/6.alert_handler_ping_timeout.3248826944 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 27053236400 ps |
| CPU time | 698.19 seconds |
| Started | Aug 29 07:47:03 AM UTC 24 |
| Finished | Aug 29 07:58:50 AM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248826944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3248826944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_alerts.2105586848 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2714832186 ps |
| CPU time | 62.67 seconds |
| Started | Aug 29 07:45:57 AM UTC 24 |
| Finished | Aug 29 07:47:01 AM UTC 24 |
| Peak memory | 262956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105586848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2105586848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_classes.2389357655 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 370901346 ps |
| CPU time | 26.94 seconds |
| Started | Aug 29 07:45:58 AM UTC 24 |
| Finished | Aug 29 07:46:27 AM UTC 24 |
| Peak memory | 269276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389357655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2389357655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/6.alert_handler_sig_int_fail.823697939 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 469976858 ps |
| CPU time | 46.19 seconds |
| Started | Aug 29 07:46:27 AM UTC 24 |
| Finished | Aug 29 07:47:15 AM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823697939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.823697939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/6.alert_handler_smoke.1222906058 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1555276004 ps |
| CPU time | 17.01 seconds |
| Started | Aug 29 07:45:56 AM UTC 24 |
| Finished | Aug 29 07:46:14 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222906058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1222906058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all.3819029845 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 50060080470 ps |
| CPU time | 3081.34 seconds |
| Started | Aug 29 07:47:37 AM UTC 24 |
| Finished | Aug 29 08:39:35 AM UTC 24 |
| Peak memory | 312124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819029845 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all.3819029845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/6.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/7.alert_handler_alert_accum_saturation.2318867178 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 26726033 ps |
| CPU time | 4.5 seconds |
| Started | Aug 29 07:49:14 AM UTC 24 |
| Finished | Aug 29 07:49:20 AM UTC 24 |
| Peak memory | 263248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318867178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2318867178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy.973726106 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 153686238392 ps |
| CPU time | 3115.61 seconds |
| Started | Aug 29 07:48:58 AM UTC 24 |
| Finished | Aug 29 08:41:31 AM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973726106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.973726106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy_stress.3298606461 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 3008377751 ps |
| CPU time | 56.93 seconds |
| Started | Aug 29 07:49:12 AM UTC 24 |
| Finished | Aug 29 07:50:11 AM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298606461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3298606461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_alert_accum.734610128 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 13577481706 ps |
| CPU time | 289.49 seconds |
| Started | Aug 29 07:48:44 AM UTC 24 |
| Finished | Aug 29 07:53:38 AM UTC 24 |
| Peak memory | 265372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734610128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.734610128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_intr_timeout.1408161708 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 817499187 ps |
| CPU time | 32.62 seconds |
| Started | Aug 29 07:48:39 AM UTC 24 |
| Finished | Aug 29 07:49:13 AM UTC 24 |
| Peak memory | 262900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408161708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1408161708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg.3304219314 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 18261906057 ps |
| CPU time | 1501.48 seconds |
| Started | Aug 29 07:49:06 AM UTC 24 |
| Finished | Aug 29 08:14:25 AM UTC 24 |
| Peak memory | 301880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304219314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3304219314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg_stub_clk.3463715498 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 337597438478 ps |
| CPU time | 1388.66 seconds |
| Started | Aug 29 07:49:10 AM UTC 24 |
| Finished | Aug 29 08:12:35 AM UTC 24 |
| Peak memory | 285496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463715498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3463715498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/7.alert_handler_ping_timeout.3061579867 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 9038930706 ps |
| CPU time | 505.01 seconds |
| Started | Aug 29 07:49:05 AM UTC 24 |
| Finished | Aug 29 07:57:37 AM UTC 24 |
| Peak memory | 262972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061579867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3061579867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_alerts.3069050395 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 624992178 ps |
| CPU time | 24.53 seconds |
| Started | Aug 29 07:48:27 AM UTC 24 |
| Finished | Aug 29 07:48:53 AM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069050395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3069050395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_classes.2455657639 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 255279579 ps |
| CPU time | 24.73 seconds |
| Started | Aug 29 07:48:39 AM UTC 24 |
| Finished | Aug 29 07:49:05 AM UTC 24 |
| Peak memory | 267292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455657639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2455657639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/7.alert_handler_sig_int_fail.291566840 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 91619568 ps |
| CPU time | 16.97 seconds |
| Started | Aug 29 07:48:54 AM UTC 24 |
| Finished | Aug 29 07:49:12 AM UTC 24 |
| Peak memory | 269120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291566840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.291566840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/7.alert_handler_smoke.1934727356 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 168101527 ps |
| CPU time | 22.52 seconds |
| Started | Aug 29 07:48:20 AM UTC 24 |
| Finished | Aug 29 07:48:44 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934727356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1934727356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all.319937285 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 11112294368 ps |
| CPU time | 1301.83 seconds |
| Started | Aug 29 07:49:14 AM UTC 24 |
| Finished | Aug 29 08:11:12 AM UTC 24 |
| Peak memory | 297860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319937285 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all.319937285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/7.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/8.alert_handler_alert_accum_saturation.3516999869 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 53890009 ps |
| CPU time | 3.67 seconds |
| Started | Aug 29 07:52:06 AM UTC 24 |
| Finished | Aug 29 07:52:11 AM UTC 24 |
| Peak memory | 263504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516999869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3516999869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy.969179019 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 25009405915 ps |
| CPU time | 1604.18 seconds |
| Started | Aug 29 07:50:47 AM UTC 24 |
| Finished | Aug 29 08:17:49 AM UTC 24 |
| Peak memory | 302148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969179019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.969179019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy_stress.1959598753 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 323889329 ps |
| CPU time | 14.74 seconds |
| Started | Aug 29 07:51:45 AM UTC 24 |
| Finished | Aug 29 07:52:01 AM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959598753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1959598753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_alert_accum.2589687415 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 13532872306 ps |
| CPU time | 169.67 seconds |
| Started | Aug 29 07:50:29 AM UTC 24 |
| Finished | Aug 29 07:53:21 AM UTC 24 |
| Peak memory | 269112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589687415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2589687415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_intr_timeout.1679321439 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 920328837 ps |
| CPU time | 25.32 seconds |
| Started | Aug 29 07:50:20 AM UTC 24 |
| Finished | Aug 29 07:50:47 AM UTC 24 |
| Peak memory | 263228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679321439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1679321439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg.3483743246 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 34502489581 ps |
| CPU time | 2350.64 seconds |
| Started | Aug 29 07:51:21 AM UTC 24 |
| Finished | Aug 29 08:30:59 AM UTC 24 |
| Peak memory | 301948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483743246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3483743246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg_stub_clk.6083245 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 19667823497 ps |
| CPU time | 1247.52 seconds |
| Started | Aug 29 07:51:34 AM UTC 24 |
| Finished | Aug 29 08:12:37 AM UTC 24 |
| Peak memory | 297788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6083245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test + UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.6083245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_alerts.1235505504 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 55093380 ps |
| CPU time | 6.47 seconds |
| Started | Aug 29 07:50:12 AM UTC 24 |
| Finished | Aug 29 07:50:20 AM UTC 24 |
| Peak memory | 262892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235505504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1235505504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_classes.606770953 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 653483428 ps |
| CPU time | 27.8 seconds |
| Started | Aug 29 07:50:16 AM UTC 24 |
| Finished | Aug 29 07:50:46 AM UTC 24 |
| Peak memory | 263232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606770953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.606770953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/8.alert_handler_sig_int_fail.1874952044 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1106568920 ps |
| CPU time | 50.92 seconds |
| Started | Aug 29 07:50:40 AM UTC 24 |
| Finished | Aug 29 07:51:33 AM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874952044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1874952044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/8.alert_handler_smoke.2853689074 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1297782355 ps |
| CPU time | 65.18 seconds |
| Started | Aug 29 07:49:21 AM UTC 24 |
| Finished | Aug 29 07:50:28 AM UTC 24 |
| Peak memory | 269052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853689074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2853689074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all.2719773118 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 28180706575 ps |
| CPU time | 1125.58 seconds |
| Started | Aug 29 07:52:02 AM UTC 24 |
| Finished | Aug 29 08:11:01 AM UTC 24 |
| Peak memory | 285500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719773118 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all.2719773118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all_with_rand_reset.3632935201 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3600969927 ps |
| CPU time | 166.3 seconds |
| Started | Aug 29 07:52:11 AM UTC 24 |
| Finished | Aug 29 07:55:00 AM UTC 24 |
| Peak memory | 279480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3632935201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.al ert_handler_stress_all_with_rand_reset.3632935201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/9.alert_handler_alert_accum_saturation.2024497776 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 23566845 ps |
| CPU time | 4.69 seconds |
| Started | Aug 29 07:53:38 AM UTC 24 |
| Finished | Aug 29 07:53:44 AM UTC 24 |
| Peak memory | 263172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024497776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2024497776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy.1498525271 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 52370601929 ps |
| CPU time | 1404.52 seconds |
| Started | Aug 29 07:53:08 AM UTC 24 |
| Finished | Aug 29 08:16:49 AM UTC 24 |
| Peak memory | 296068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498525271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1498525271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy_stress.2593051892 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 736262111 ps |
| CPU time | 14.61 seconds |
| Started | Aug 29 07:53:22 AM UTC 24 |
| Finished | Aug 29 07:53:38 AM UTC 24 |
| Peak memory | 262912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593051892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2593051892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_alert_accum.249034126 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1847887701 ps |
| CPU time | 189.36 seconds |
| Started | Aug 29 07:52:54 AM UTC 24 |
| Finished | Aug 29 07:56:07 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249034126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.249034126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_intr_timeout.378937844 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1347089100 ps |
| CPU time | 28.23 seconds |
| Started | Aug 29 07:52:43 AM UTC 24 |
| Finished | Aug 29 07:53:13 AM UTC 24 |
| Peak memory | 269044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378937844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.378937844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg.4112528230 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 42618138832 ps |
| CPU time | 1385.77 seconds |
| Started | Aug 29 07:53:14 AM UTC 24 |
| Finished | Aug 29 08:16:35 AM UTC 24 |
| Peak memory | 285692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112528230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.4112528230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg_stub_clk.2458630126 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 31615585073 ps |
| CPU time | 2063.77 seconds |
| Started | Aug 29 07:53:16 AM UTC 24 |
| Finished | Aug 29 08:28:03 AM UTC 24 |
| Peak memory | 301884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458630126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2458630126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/9.alert_handler_ping_timeout.237087114 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 20235776086 ps |
| CPU time | 491.42 seconds |
| Started | Aug 29 07:53:11 AM UTC 24 |
| Finished | Aug 29 08:01:29 AM UTC 24 |
| Peak memory | 263304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237087114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.237087114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_alerts.1404294513 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 359223480 ps |
| CPU time | 17.93 seconds |
| Started | Aug 29 07:52:34 AM UTC 24 |
| Finished | Aug 29 07:52:54 AM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404294513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1404294513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_classes.183705631 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3350046677 ps |
| CPU time | 79.51 seconds |
| Started | Aug 29 07:52:39 AM UTC 24 |
| Finished | Aug 29 07:54:00 AM UTC 24 |
| Peak memory | 263040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183705631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.183705631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/9.alert_handler_sig_int_fail.528647815 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1682901896 ps |
| CPU time | 39.85 seconds |
| Started | Aug 29 07:53:06 AM UTC 24 |
| Finished | Aug 29 07:53:48 AM UTC 24 |
| Peak memory | 269048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528647815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.528647815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/9.alert_handler_smoke.1063207726 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 3474622832 ps |
| CPU time | 47.75 seconds |
| Started | Aug 29 07:52:16 AM UTC 24 |
| Finished | Aug 29 07:53:06 AM UTC 24 |
| Peak memory | 263356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063207726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1063207726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all.4115165310 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 33594955906 ps |
| CPU time | 1502.57 seconds |
| Started | Aug 29 07:53:22 AM UTC 24 |
| Finished | Aug 29 08:18:42 AM UTC 24 |
| Peak memory | 301956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115165310 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all.4115165310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all_with_rand_reset.2523071722 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 12420234616 ps |
| CPU time | 224.42 seconds |
| Started | Aug 29 07:53:39 AM UTC 24 |
| Finished | Aug 29 07:57:27 AM UTC 24 |
| Peak memory | 285624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2523071722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.al ert_handler_stress_all_with_rand_reset.2523071722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest |
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