Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	43059	1			T35	76		T27	169		T15	5
class_i[0x1]	45964	1			T11	98		T15	10		T67	2
class_i[0x2]	48701	1			T7	1		T27	416		T136	90
class_i[0x3]	62780	1			T7	1		T27	8		T67	621

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	50529	1			T11	22		T27	7		T67	2
alert[0x1]	49285	1			T11	22		T27	331		T15	2
alert[0x2]	49634	1			T11	18		T35	76		T7	1
alert[0x3]	51056	1			T11	36		T7	1		T15	7

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

200206

1

T11

98

T35

76

T7

1

esc_ping_fail

298

1

T7

1

T15

6

T16

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	50442	1			T11	22		T27	7		T67	2
esc_integrity_fail	alert[0x1]	49207	1			T11	22		T27	331		T15	1
esc_integrity_fail	alert[0x2]	49565	1			T11	18		T35	76		T27	255
esc_integrity_fail	alert[0x3]	50992	1			T11	36		T7	1		T15	5
esc_ping_fail	alert[0x0]	87	1			T16	2		T338	4		T158	2
esc_ping_fail	alert[0x1]	78	1			T15	1		T16	2		T338	1
esc_ping_fail	alert[0x2]	69	1			T7	1		T15	3		T16	1
esc_ping_fail	alert[0x3]	64	1			T15	2		T16	1		T338	3

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	43009	1			T35	76		T27	169		T50	344
esc_integrity_fail	class_i[0x1]	45877	1			T11	98		T15	9		T67	2
esc_integrity_fail	class_i[0x2]	48614	1			T7	1		T27	416		T136	90
esc_integrity_fail	class_i[0x3]	62706	1			T27	8		T67	621		T16	8
esc_ping_fail	class_i[0x0]	50	1			T15	5		T338	6		T158	1
esc_ping_fail	class_i[0x1]	87	1			T15	1		T158	1		T314	1
esc_ping_fail	class_i[0x2]	87	1			T338	1		T158	9		T339	5
esc_ping_fail	class_i[0x3]	74	1			T7	1		T16	6		T338	1