Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	154	1			T26	2		T221	1		T34	1
index[0x1]	171	1			T23	1		T25	2		T28	1
index[0x2]	181	1			T11	1		T27	2		T28	1
index[0x3]	163	1			T11	1		T26	2		T27	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	229	1			T11	1		T23	1		T27	1
lens_less_than_1000[1]	106	1			T27	2		T48	1		T80	1
lens_less_than_1000[2]	98	1			T28	1		T47	1		T272	1
lens_less_than_1000[3]	77	1			T295	1		T296	1		T297	1
lens_less_than_1000[4]	47	1			T26	1		T28	1		T107	1
lens_less_than_1000[5]	40	1			T11	1		T26	2		T28	2
lens_less_than_1000[6]	28	1			T25	2		T221	1		T53	1
lens_less_than_1000[7]	22	1			T26	1		T82	2		T53	1
lens_less_than_1000[8]	9	1			T75	1		T124	2		T298	1
lens_less_than_1000[9]	3	1			T299	1		T39	1		T283	1
len_2	10	1			T300	1		T301	1		T302	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[len_2]	0	1	1
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	56	1			T136	1		T303	1		T304	1
index[0x0]	lens_less_than_1000[1]	38	1			T34	1		T51	2		T305	1
index[0x0]	lens_less_than_1000[2]	26	1			T52	1		T258	1		T306	1
index[0x0]	lens_less_than_1000[3]	8	1			T295	1		T307	1		T55	1
index[0x0]	lens_less_than_1000[4]	10	1			T26	1		T308	1		T309	1
index[0x0]	lens_less_than_1000[5]	7	1			T310	1		T311	1		T38	1
index[0x0]	lens_less_than_1000[6]	4	1			T221	1		T114	1		T312	2
index[0x0]	lens_less_than_1000[7]	3	1			T26	1		T53	1		T313	1
index[0x0]	lens_less_than_1000[8]	1	1			T75	1		-	-		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T39	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	45	1			T23	1		T15	1		T220	1
index[0x1]	lens_less_than_1000[1]	24	1			T80	1		T314	1		T311	1
index[0x1]	lens_less_than_1000[2]	34	1			T47	1		T81	1		T54	1
index[0x1]	lens_less_than_1000[3]	23	1			T296	1		T297	1		T315	1
index[0x1]	lens_less_than_1000[4]	11	1			T28	1		T259	1		T316	1
index[0x1]	lens_less_than_1000[5]	14	1			T317	1		T118	1		T30	1
index[0x1]	lens_less_than_1000[6]	8	1			T25	2		T217	1		T57	1
index[0x1]	lens_less_than_1000[7]	6	1			T30	1		T148	1		T291	4
index[0x1]	lens_less_than_1000[8]	1	1			T124	1		-	-		-	-
index[0x1]	lens_less_than_1000[9]	1	1			T299	1		-	-		-	-
index[0x1]	len_2	4	1			T301	1		T318	1		T319	1
index[0x2]	lens_less_than_1000[0]	67	1			T11	1		T87	1		T50	2
index[0x2]	lens_less_than_1000[1]	22	1			T27	2		T48	1		T94	1
index[0x2]	lens_less_than_1000[2]	17	1			T28	1		T272	1		T94	1
index[0x2]	lens_less_than_1000[3]	26	1			T53	2		T320	1		T99	1
index[0x2]	lens_less_than_1000[4]	14	1			T119	1		T321	1		T309	1
index[0x2]	lens_less_than_1000[5]	10	1			T77	3		T322	1		T274	4
index[0x2]	lens_less_than_1000[6]	10	1			T57	1		T121	1		T323	1
index[0x2]	lens_less_than_1000[7]	8	1			T82	1		T298	1		T274	1
index[0x2]	lens_less_than_1000[8]	3	1			T124	1		T324	1		T325	1
index[0x2]	lens_less_than_1000[9]	1	1			T283	1		-	-		-	-
index[0x2]	len_2	3	1			T302	1		T153	1		T293	1
index[0x3]	lens_less_than_1000[0]	61	1			T27	1		T221	1		T34	1
index[0x3]	lens_less_than_1000[1]	22	1			T91	1		T326	1		T327	1
index[0x3]	lens_less_than_1000[2]	21	1			T258	1		T307	1		T217	1
index[0x3]	lens_less_than_1000[3]	20	1			T83	2		T95	1		T58	1
index[0x3]	lens_less_than_1000[4]	12	1			T107	1		T100	1		T75	1
index[0x3]	lens_less_than_1000[5]	9	1			T11	1		T26	2		T28	2
index[0x3]	lens_less_than_1000[6]	6	1			T53	1		T258	1		T147	1
index[0x3]	lens_less_than_1000[7]	5	1			T82	1		T129	1		T319	1
index[0x3]	lens_less_than_1000[8]	4	1			T298	1		T129	1		T280	1
index[0x3]	len_2	3	1			T300	1		T110	1		T328	1