Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	6	34	85.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	6	34	85.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	51	1			T36	1		T87	1		T50	2
class_index[0x1]	48	1			T26	1		T50	4		T80	2
class_index[0x2]	60	1			T27	2		T36	1		T87	1
class_index[0x3]	55	1			T86	1		T27	1		T49	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	102	1			T87	1		T50	2		T80	2
intr_timeout_cnt[1]	48	1			T26	1		T86	1		T36	1
intr_timeout_cnt[2]	22	1			T27	1		T50	4		T53	1
intr_timeout_cnt[3]	12	1			T27	1		T36	1		T49	1
intr_timeout_cnt[4]	9	1			T98	1		T57	3		T273	1
intr_timeout_cnt[5]	5	1			T27	1		T274	1		T275	1
intr_timeout_cnt[6]	3	1			T112	1		T276	1		T110	1
intr_timeout_cnt[7]	5	1			T58	1		T277	2		T278	1
intr_timeout_cnt[8]	3	1			T279	1		T261	1		T280	1
intr_timeout_cnt[9]	5	1			T281	1		T151	1		T261	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	6	34	85.00	6

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[7] , intr_timeout_cnt[8]]	--	--	2
[class_index[0x1]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	27	1			T87	1		T50	1		T89	1
class_index[0x0]	intr_timeout_cnt[1]	13	1			T36	1		T50	1		T100	2
class_index[0x0]	intr_timeout_cnt[2]	4	1			T114	1		T282	1		T279	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T54	1		T283	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	1	1			T98	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	1	1			T112	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	3	1			T281	1		T261	1		T280	1
class_index[0x1]	intr_timeout_cnt[0]	17	1			T50	1		T80	2		T54	1
class_index[0x1]	intr_timeout_cnt[1]	12	1			T26	1		T54	1		T101	1
class_index[0x1]	intr_timeout_cnt[2]	7	1			T50	3		T53	1		T104	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T284	1		T285	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	3	1			T57	2		T286	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	3	1			T274	1		T275	1		T280	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T276	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T277	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T287	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	35	1			T89	1		T53	1		T54	1
class_index[0x2]	intr_timeout_cnt[1]	11	1			T87	1		T288	1		T289	1
class_index[0x2]	intr_timeout_cnt[2]	5	1			T27	1		T114	1		T281	1
class_index[0x2]	intr_timeout_cnt[3]	3	1			T36	1		T285	1		T290	1
class_index[0x2]	intr_timeout_cnt[4]	1	1			T273	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	1	1			T27	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	1	1			T58	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T279	1		T280	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T151	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	23	1			T139	1		T99	1		T101	1
class_index[0x3]	intr_timeout_cnt[1]	12	1			T86	1		T136	3		T138	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T50	1		T275	1		T291	4
class_index[0x3]	intr_timeout_cnt[3]	5	1			T27	1		T49	1		T288	1
class_index[0x3]	intr_timeout_cnt[4]	4	1			T57	1		T280	2		T291	1
class_index[0x3]	intr_timeout_cnt[5]	1	1			T292	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T110	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T278	1		T293	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T261	1		-	-		-	-