Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	297332	1			T1	5		T3	15		T10	19
all_values[1]	297332	1			T1	5		T3	15		T10	19
all_values[2]	297332	1			T1	5		T3	15		T10	19
all_values[3]	297332	1			T1	5		T3	15		T10	19

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

592246

1

T1

9

T3

23

T10

46

auto[1]

597082

1

T1

11

T3

37

T10

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

694049

1

T1

12

T3

58

T10

43

auto[1]

495279

1

T1

8

T3

2

T10

33

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	86089	1			T3	6		T10	6		T12	12
all_values[0]	auto[0]	auto[1]	62567	1			T10	4		T12	11		T14	7
all_values[0]	auto[1]	auto[0]	86848	1			T1	3		T3	7		T10	6
all_values[0]	auto[1]	auto[1]	61828	1			T1	2		T3	2		T10	3
all_values[1]	auto[0]	auto[0]	85417	1			T1	2		T3	4		T10	9
all_values[1]	auto[0]	auto[1]	62262	1			T1	1		T10	6		T12	6
all_values[1]	auto[1]	auto[0]	87193	1			T1	1		T3	11		T10	2
all_values[1]	auto[1]	auto[1]	62460	1			T1	1		T10	2		T12	11
all_values[2]	auto[0]	auto[0]	85712	1			T1	2		T3	8		T10	4
all_values[2]	auto[0]	auto[1]	62208	1			T1	1		T10	4		T12	9
all_values[2]	auto[1]	auto[0]	87011	1			T1	1		T3	7		T10	6
all_values[2]	auto[1]	auto[1]	62401	1			T1	1		T10	5		T12	8
all_values[3]	auto[0]	auto[0]	87146	1			T1	2		T3	5		T10	7
all_values[3]	auto[0]	auto[1]	60845	1			T1	1		T10	6		T12	10
all_values[3]	auto[1]	auto[0]	88633	1			T1	1		T3	10		T10	3
all_values[3]	auto[1]	auto[1]	60708	1			T1	1		T10	3		T12	7