Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	297332	1			T1	5		T3	15		T10	19
all_pins[1]	297332	1			T1	5		T3	15		T10	19
all_pins[2]	297332	1			T1	5		T3	15		T10	19
all_pins[3]	297332	1			T1	5		T3	15		T10	19

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	941931	1			T1	15		T3	58		T10	63
values[0x1]	247397	1			T1	5		T3	2		T10	13
transitions[0x0=>0x1]	162907	1			T1	1		T3	1		T10	10
transitions[0x1=>0x0]	163139	1			T1	2		T3	2		T10	11

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	235504	1			T1	3		T3	13		T10	16
all_pins[0]	values[0x1]	61828	1			T1	2		T3	2		T10	3
all_pins[0]	transitions[0x0=>0x1]	61310	1			T1	1		T3	1		T10	2
all_pins[0]	transitions[0x1=>0x0]	60422	1			T1	1		T10	3		T12	7
all_pins[1]	values[0x0]	234872	1			T1	4		T3	15		T10	17
all_pins[1]	values[0x1]	62460	1			T1	1		T10	2		T12	11
all_pins[1]	transitions[0x0=>0x1]	34464	1			T10	2		T12	8		T14	3
all_pins[1]	transitions[0x1=>0x0]	33832	1			T1	1		T3	2		T10	3
all_pins[2]	values[0x0]	234931	1			T1	4		T3	15		T10	14
all_pins[2]	values[0x1]	62401	1			T1	1		T10	5		T12	8
all_pins[2]	transitions[0x0=>0x1]	34253	1			T10	4		T12	2		T14	4
all_pins[2]	transitions[0x1=>0x0]	34312	1			T10	1		T12	5		T14	2
all_pins[3]	values[0x0]	236624	1			T1	4		T3	15		T10	16
all_pins[3]	values[0x1]	60708	1			T1	1		T10	3		T12	7
all_pins[3]	transitions[0x0=>0x1]	32880	1			T10	2		T12	3		T14	5
all_pins[3]	transitions[0x1=>0x0]	34573	1			T10	4		T12	4		T14	3