Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1			T198	7		T200	4		T271	7
all_values[1]	266	1			T198	7		T200	4		T271	7
all_values[2]	266	1			T198	7		T200	4		T271	7
all_values[3]	266	1			T198	7		T200	4		T271	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

606

1

T198

21

T200

12

T271

17

auto[1]

458

1

T198

7

T200

4

T271

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

416

1

T198

9

T200

7

T271

8

auto[1]

648

1

T198

19

T200

9

T271

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

621

1

T198

14

T200

11

T271

17

auto[1]

443

1

T198

14

T200

5

T271

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

63

1

T198

2

T200

2

T271

2

all_values[0]

auto[0]

auto[0]

auto[1]

25

1

T386

1

T387

1

T388

1

all_values[0]

auto[0]

auto[1]

auto[0]

36

1

T200

1

T386

1

T389

2

all_values[0]

auto[0]

auto[1]

auto[1]

24

1

T271

3

T390

1

T389

1

all_values[0]

auto[1]

auto[0]

auto[1]

60

1

T198

4

T271

1

T386

2

all_values[0]

auto[1]

auto[1]

auto[1]

58

1

T198

1

T200

1

T271

1

all_values[1]

auto[0]

auto[0]

auto[0]

69

1

T198

3

T271

2

T386

2

all_values[1]

auto[0]

auto[0]

auto[1]

30

1

T200

2

T271

2

T386

1

all_values[1]

auto[0]

auto[1]

auto[0]

44

1

T198

1

T390

2

T389

3

all_values[1]

auto[0]

auto[1]

auto[1]

20

1

T198

1

T200

1

T386

1

all_values[1]

auto[1]

auto[0]

auto[1]

56

1

T198

1

T200

1

T271

1

all_values[1]

auto[1]

auto[1]

auto[1]

47

1

T198

1

T271

2

T389

2

all_values[2]

auto[0]

auto[0]

auto[0]

49

1

T198

2

T200

3

T271

1

all_values[2]

auto[0]

auto[0]

auto[1]

35

1

T271

2

T390

1

T389

1

all_values[2]

auto[0]

auto[1]

auto[0]

37

1

T271

1

T386

1

T387

2

all_values[2]

auto[0]

auto[1]

auto[1]

29

1

T198

1

T271

1

T390

1

all_values[2]

auto[1]

auto[0]

auto[1]

73

1

T198

4

T200

1

T271

1

all_values[2]

auto[1]

auto[1]

auto[1]

43

1

T271

1

T386

1

T390

1

all_values[3]

auto[0]

auto[0]

auto[0]

63

1

T198

1

T200

1

T271

2

all_values[3]

auto[0]

auto[0]

auto[1]

28

1

T198

3

T200

1

T386

1

all_values[3]

auto[0]

auto[1]

auto[0]

55

1

T386

1

T390

4

T388

1

all_values[3]

auto[0]

auto[1]

auto[1]

14

1

T271

1

T388

2

T391

1

all_values[3]

auto[1]

auto[0]

auto[1]

55

1

T198

1

T200

1

T271

3

all_values[3]

auto[1]

auto[1]

auto[1]

51

1

T198

2

T200

1

T271

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal