Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	83999	1			T335	331		T84	197		T146	1473
accum_cnt_1000	187862	1			T23	2		T27	2		T47	106
accum_cnt_100	21514	1			T11	13		T22	10		T23	13
accum_cnt_50	64393	1			T14	20		T11	38		T22	10
accum_cnt_10	157957	1			T1	1		T3	10		T10	20
accum_cnt_0	324844	1			T1	11		T3	30		T10	36

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	220290	1			T1	3		T3	10		T10	14
class_index[0x1]	220290	1			T1	3		T3	10		T10	14
class_index[0x2]	220290	1			T1	3		T3	10		T10	14
class_index[0x3]	220290	1			T1	3		T3	10		T10	14

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	19674	1			T146	208		T255	194		T311	329
class_index[0x0]	accum_cnt_1000	44767	1			T23	2		T27	1		T47	28
class_index[0x0]	accum_cnt_100	5602	1			T22	10		T23	13		T35	1
class_index[0x0]	accum_cnt_50	18543	1			T11	7		T22	10		T23	10
class_index[0x0]	accum_cnt_10	39256	1			T3	10		T12	1		T11	19
class_index[0x0]	accum_cnt_0	82465	1			T1	3		T10	14		T12	33
class_index[0x1]	accum_cnt_2000	19276	1			T146	397		T255	231		T315	479
class_index[0x1]	accum_cnt_1000	45292	1			T47	43		T36	29		T48	9
class_index[0x1]	accum_cnt_100	6080	1			T11	13		T76	4		T47	17
class_index[0x1]	accum_cnt_50	18407	1			T14	20		T11	12		T76	17
class_index[0x1]	accum_cnt_10	37793	1			T10	8		T12	1		T14	11
class_index[0x1]	accum_cnt_0	86223	1			T1	3		T3	10		T10	6
class_index[0x2]	accum_cnt_2000	23768	1			T335	331		T146	438		T55	507
class_index[0x2]	accum_cnt_1000	50385	1			T27	1		T68	8		T48	11
class_index[0x2]	accum_cnt_100	5092	1			T85	4		T76	4		T68	39
class_index[0x2]	accum_cnt_50	13758	1			T11	19		T25	2		T35	1
class_index[0x2]	accum_cnt_10	34595	1			T1	1		T10	12		T11	10
class_index[0x2]	accum_cnt_0	80632	1			T1	2		T3	10		T10	2
class_index[0x3]	accum_cnt_2000	21281	1			T84	197		T146	430		T315	457
class_index[0x3]	accum_cnt_1000	47418	1			T47	35		T67	1		T68	49
class_index[0x3]	accum_cnt_100	4740	1			T85	6		T76	3		T47	22
class_index[0x3]	accum_cnt_50	13685	1			T85	26		T86	6		T76	18
class_index[0x3]	accum_cnt_10	46313	1			T12	1		T14	18		T11	29
class_index[0x3]	accum_cnt_0	75524	1			T1	3		T3	10		T10	14