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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.24 99.99 98.71 97.09 100.00 100.00 99.38 99.48


Total test records in report: 825
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T182 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.963920320 Sep 04 03:26:08 PM UTC 24 Sep 04 03:29:01 PM UTC 24 3227034452 ps
T783 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3325379114 Sep 04 03:28:38 PM UTC 24 Sep 04 03:29:10 PM UTC 24 262750062 ps
T784 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.4282547071 Sep 04 03:28:56 PM UTC 24 Sep 04 03:29:15 PM UTC 24 566352816 ps
T785 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.253132809 Sep 04 03:28:53 PM UTC 24 Sep 04 03:29:17 PM UTC 24 371718979 ps
T786 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.3204834485 Sep 04 03:29:16 PM UTC 24 Sep 04 03:29:19 PM UTC 24 12791708 ps
T787 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.3289810605 Sep 04 03:29:02 PM UTC 24 Sep 04 03:29:22 PM UTC 24 719154813 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3530488480 Sep 04 03:28:48 PM UTC 24 Sep 04 03:29:24 PM UTC 24 954057241 ps
T788 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.1810316261 Sep 04 03:29:18 PM UTC 24 Sep 04 03:29:25 PM UTC 24 256505579 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2386465358 Sep 04 03:29:12 PM UTC 24 Sep 04 03:29:25 PM UTC 24 152391308 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.184028411 Sep 04 03:29:25 PM UTC 24 Sep 04 03:29:31 PM UTC 24 60676073 ps
T789 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2059324419 Sep 04 03:29:22 PM UTC 24 Sep 04 03:29:34 PM UTC 24 349136768 ps
T790 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.1673778377 Sep 04 03:29:33 PM UTC 24 Sep 04 03:29:36 PM UTC 24 61238951 ps
T791 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3168526907 Sep 04 03:23:35 PM UTC 24 Sep 04 03:29:37 PM UTC 24 4868310916 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2696324190 Sep 04 03:19:43 PM UTC 24 Sep 04 03:29:40 PM UTC 24 16332143860 ps
T792 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.3578787117 Sep 04 03:29:25 PM UTC 24 Sep 04 03:29:40 PM UTC 24 156874866 ps
T793 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.3227629597 Sep 04 03:29:38 PM UTC 24 Sep 04 03:29:41 PM UTC 24 28411319 ps
T794 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.1019440183 Sep 04 03:29:41 PM UTC 24 Sep 04 03:29:44 PM UTC 24 16869350 ps
T795 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.828447846 Sep 04 03:29:42 PM UTC 24 Sep 04 03:29:46 PM UTC 24 6504727 ps
T796 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.1230102546 Sep 04 03:29:43 PM UTC 24 Sep 04 03:29:46 PM UTC 24 26151280 ps
T797 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1637415482 Sep 04 03:29:37 PM UTC 24 Sep 04 03:29:47 PM UTC 24 345493787 ps
T798 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.2562115477 Sep 04 03:29:45 PM UTC 24 Sep 04 03:29:48 PM UTC 24 11326134 ps
T799 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.2909086297 Sep 04 03:29:45 PM UTC 24 Sep 04 03:29:48 PM UTC 24 7980023 ps
T800 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.911308076 Sep 04 03:29:22 PM UTC 24 Sep 04 03:29:50 PM UTC 24 308362925 ps
T801 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.1015249248 Sep 04 03:29:48 PM UTC 24 Sep 04 03:29:51 PM UTC 24 18878145 ps
T802 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.1265834044 Sep 04 03:29:48 PM UTC 24 Sep 04 03:29:51 PM UTC 24 11276666 ps
T803 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.4004187481 Sep 04 03:29:49 PM UTC 24 Sep 04 03:29:53 PM UTC 24 7770694 ps
T804 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.1618325133 Sep 04 03:29:49 PM UTC 24 Sep 04 03:29:53 PM UTC 24 8261076 ps
T805 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.3077877159 Sep 04 03:29:49 PM UTC 24 Sep 04 03:29:53 PM UTC 24 8344191 ps
T806 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.2461089461 Sep 04 03:29:51 PM UTC 24 Sep 04 03:29:54 PM UTC 24 14657825 ps
T807 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.3507137529 Sep 04 03:29:52 PM UTC 24 Sep 04 03:29:56 PM UTC 24 6269868 ps
T808 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.2572918950 Sep 04 03:29:52 PM UTC 24 Sep 04 03:29:56 PM UTC 24 7717234 ps
T809 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.2129752967 Sep 04 03:29:54 PM UTC 24 Sep 04 03:29:57 PM UTC 24 12183268 ps
T810 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.338443667 Sep 04 03:29:56 PM UTC 24 Sep 04 03:29:59 PM UTC 24 10303590 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.413836381 Sep 04 03:29:55 PM UTC 24 Sep 04 03:29:59 PM UTC 24 8556600 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.2986397091 Sep 04 03:29:55 PM UTC 24 Sep 04 03:29:59 PM UTC 24 38201651 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.4085595662 Sep 04 03:29:57 PM UTC 24 Sep 04 03:30:00 PM UTC 24 10346214 ps
T814 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.1846383208 Sep 04 03:29:57 PM UTC 24 Sep 04 03:30:00 PM UTC 24 8692998 ps
T815 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.2553217494 Sep 04 03:29:58 PM UTC 24 Sep 04 03:30:01 PM UTC 24 19080402 ps
T816 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.1922149914 Sep 04 03:30:01 PM UTC 24 Sep 04 03:30:04 PM UTC 24 11040965 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.3053347486 Sep 04 03:30:01 PM UTC 24 Sep 04 03:30:04 PM UTC 24 7347086 ps
T818 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.999759940 Sep 04 03:30:01 PM UTC 24 Sep 04 03:30:04 PM UTC 24 7803841 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.620365273 Sep 04 03:30:01 PM UTC 24 Sep 04 03:30:04 PM UTC 24 19566547 ps
T820 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.3883885943 Sep 04 03:30:01 PM UTC 24 Sep 04 03:30:04 PM UTC 24 10243932 ps
T821 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.1924038926 Sep 04 03:30:03 PM UTC 24 Sep 04 03:30:06 PM UTC 24 9588563 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.3738144354 Sep 04 03:30:05 PM UTC 24 Sep 04 03:30:08 PM UTC 24 18086026 ps
T823 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.446610254 Sep 04 03:30:05 PM UTC 24 Sep 04 03:30:09 PM UTC 24 13088582 ps
T824 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.3584739864 Sep 04 03:30:05 PM UTC 24 Sep 04 03:30:09 PM UTC 24 10403473 ps
T825 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2330354677 Sep 04 03:29:36 PM UTC 24 Sep 04 03:30:19 PM UTC 24 7410860197 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.579466081 Sep 04 03:26:21 PM UTC 24 Sep 04 03:30:21 PM UTC 24 2069762634 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3782851155 Sep 04 03:26:42 PM UTC 24 Sep 04 03:30:42 PM UTC 24 10577671830 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1475216567 Sep 04 03:28:21 PM UTC 24 Sep 04 03:30:56 PM UTC 24 787239444 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4242818943 Sep 04 03:24:26 PM UTC 24 Sep 04 03:31:14 PM UTC 24 19916419586 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.315729121 Sep 04 03:28:42 PM UTC 24 Sep 04 03:31:18 PM UTC 24 4203336617 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2001621328 Sep 04 03:27:00 PM UTC 24 Sep 04 03:31:43 PM UTC 24 3777764509 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.767807220 Sep 04 03:28:06 PM UTC 24 Sep 04 03:31:57 PM UTC 24 10184367371 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1427865387 Sep 04 03:26:59 PM UTC 24 Sep 04 03:32:47 PM UTC 24 2227837153 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1186389349 Sep 04 03:25:26 PM UTC 24 Sep 04 03:33:00 PM UTC 24 24763653163 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.864971821 Sep 04 03:29:25 PM UTC 24 Sep 04 03:33:05 PM UTC 24 5157318322 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2352649619 Sep 04 03:21:58 PM UTC 24 Sep 04 03:33:52 PM UTC 24 36100238542 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.724483298 Sep 04 03:28:06 PM UTC 24 Sep 04 03:33:53 PM UTC 24 2931679488 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2700043863 Sep 04 03:27:49 PM UTC 24 Sep 04 03:34:27 PM UTC 24 21334953398 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.903431772 Sep 04 03:22:43 PM UTC 24 Sep 04 03:34:39 PM UTC 24 19031515658 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3369583174 Sep 04 03:25:00 PM UTC 24 Sep 04 03:35:25 PM UTC 24 7650617263 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2050261455 Sep 04 03:26:07 PM UTC 24 Sep 04 03:36:14 PM UTC 24 6324618236 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1580328611 Sep 04 03:25:48 PM UTC 24 Sep 04 03:36:29 PM UTC 24 13463284477 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2516400411 Sep 04 03:26:40 PM UTC 24 Sep 04 03:36:36 PM UTC 24 18067540879 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3214400742 Sep 04 03:28:58 PM UTC 24 Sep 04 03:36:40 PM UTC 24 5842972448 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.171395357 Sep 04 03:23:38 PM UTC 24 Sep 04 03:36:42 PM UTC 24 12563098249 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3624597032 Sep 04 03:28:41 PM UTC 24 Sep 04 03:36:47 PM UTC 24 25942723733 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1886707203 Sep 04 03:28:18 PM UTC 24 Sep 04 03:37:31 PM UTC 24 154939574577 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3083317911 Sep 04 03:29:23 PM UTC 24 Sep 04 03:37:34 PM UTC 24 2396887003 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1820473061 Sep 04 03:26:20 PM UTC 24 Sep 04 03:42:27 PM UTC 24 48819017609 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3081142223 Sep 04 03:24:18 PM UTC 24 Sep 04 03:44:38 PM UTC 24 14894907318 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3165616207 Sep 04 03:27:49 PM UTC 24 Sep 04 03:46:15 PM UTC 24 56095135138 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.116387925 Sep 04 03:28:57 PM UTC 24 Sep 04 03:47:41 PM UTC 24 24787310470 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/1.alert_handler_sig_int_fail.1218300717
Short name T11
Test name
Test status
Simulation time 364605815 ps
CPU time 36.71 seconds
Started Sep 04 01:39:13 PM UTC 24
Finished Sep 04 01:39:51 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218300717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1218300717
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/0.alert_handler_sec_cm.3488756866
Short name T6
Test name
Test status
Simulation time 1377102083 ps
CPU time 49.52 seconds
Started Sep 04 01:39:11 PM UTC 24
Finished Sep 04 01:40:02 PM UTC 24
Peak memory 297296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488756866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3488756866
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all_with_rand_reset.3412939188
Short name T50
Test name
Test status
Simulation time 22994406022 ps
CPU time 270.91 seconds
Started Sep 04 01:39:41 PM UTC 24
Finished Sep 04 01:44:16 PM UTC 24
Peak memory 279476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3412939188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.al
ert_handler_stress_all_with_rand_reset.3412939188
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy_stress.109621500
Short name T4
Test name
Test status
Simulation time 191402721 ps
CPU time 9.64 seconds
Started Sep 04 01:39:30 PM UTC 24
Finished Sep 04 01:39:41 PM UTC 24
Peak memory 263044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109621500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.109621500
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1723484048
Short name T196
Test name
Test status
Simulation time 1308503275 ps
CPU time 138.19 seconds
Started Sep 04 03:17:59 PM UTC 24
Finished Sep 04 03:20:20 PM UTC 24
Peak memory 252520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723484048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1723484048
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_classes.2206837075
Short name T26
Test name
Test status
Simulation time 1329855420 ps
CPU time 58.4 seconds
Started Sep 04 01:39:11 PM UTC 24
Finished Sep 04 01:40:12 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206837075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2206837075
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all_with_rand_reset.2790528352
Short name T30
Test name
Test status
Simulation time 4453511165 ps
CPU time 383.08 seconds
Started Sep 04 01:58:44 PM UTC 24
Finished Sep 04 02:05:12 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2790528352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.a
lert_handler_stress_all_with_rand_reset.2790528352
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/3.alert_handler_sig_int_fail.1884907310
Short name T27
Test name
Test status
Simulation time 2117487896 ps
CPU time 55.12 seconds
Started Sep 04 01:40:24 PM UTC 24
Finished Sep 04 01:41:22 PM UTC 24
Peak memory 262936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884907310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1884907310
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy.1083268243
Short name T128
Test name
Test status
Simulation time 106672481468 ps
CPU time 3033.37 seconds
Started Sep 04 02:05:10 PM UTC 24
Finished Sep 04 02:56:17 PM UTC 24
Peak memory 300504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083268243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1083268243
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.246628406
Short name T160
Test name
Test status
Simulation time 3080183520 ps
CPU time 312.25 seconds
Started Sep 04 03:17:22 PM UTC 24
Finished Sep 04 03:22:39 PM UTC 24
Peak memory 279528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246628406 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.246628406
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg.1903873403
Short name T75
Test name
Test status
Simulation time 50594724796 ps
CPU time 1950.83 seconds
Started Sep 04 01:40:40 PM UTC 24
Finished Sep 04 02:13:32 PM UTC 24
Peak memory 281480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903873403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1903873403
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy.3328336293
Short name T135
Test name
Test status
Simulation time 34731432912 ps
CPU time 1840.79 seconds
Started Sep 04 01:43:14 PM UTC 24
Finished Sep 04 02:14:15 PM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328336293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3328336293
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/25.alert_handler_ping_timeout.3842885146
Short name T143
Test name
Test status
Simulation time 10334985105 ps
CPU time 232.44 seconds
Started Sep 04 02:24:38 PM UTC 24
Finished Sep 04 02:28:34 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842885146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3842885146
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg.2219058009
Short name T113
Test name
Test status
Simulation time 51259416758 ps
CPU time 2730.2 seconds
Started Sep 04 01:39:17 PM UTC 24
Finished Sep 04 02:25:17 PM UTC 24
Peak memory 302212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219058009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2219058009
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.903431772
Short name T187
Test name
Test status
Simulation time 19031515658 ps
CPU time 707.24 seconds
Started Sep 04 03:22:43 PM UTC 24
Finished Sep 04 03:34:39 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903431772 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow
_reg_errors_with_csr_rw.903431772
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.4248387531
Short name T165
Test name
Test status
Simulation time 7987971130 ps
CPU time 174.7 seconds
Started Sep 04 03:25:06 PM UTC 24
Finished Sep 04 03:28:04 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248387531 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.4248387531
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_alerts.2427581888
Short name T22
Test name
Test status
Simulation time 2480439661 ps
CPU time 43.05 seconds
Started Sep 04 01:39:11 PM UTC 24
Finished Sep 04 01:39:56 PM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427581888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2427581888
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg_stub_clk.1168932748
Short name T146
Test name
Test status
Simulation time 49043448302 ps
CPU time 1177.23 seconds
Started Sep 04 01:39:30 PM UTC 24
Finished Sep 04 01:59:21 PM UTC 24
Peak memory 297860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168932748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1168932748
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/4.alert_handler_ping_timeout.4123621188
Short name T337
Test name
Test status
Simulation time 13651177503 ps
CPU time 543.09 seconds
Started Sep 04 01:41:20 PM UTC 24
Finished Sep 04 01:50:30 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123621188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.4123621188
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3214400742
Short name T172
Test name
Test status
Simulation time 5842972448 ps
CPU time 455.57 seconds
Started Sep 04 03:28:58 PM UTC 24
Finished Sep 04 03:36:40 PM UTC 24
Peak memory 285668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214400742 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.3214400742
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all_with_rand_reset.4122878564
Short name T34
Test name
Test status
Simulation time 5539606238 ps
CPU time 254.62 seconds
Started Sep 04 01:40:58 PM UTC 24
Finished Sep 04 01:45:17 PM UTC 24
Peak memory 279548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4122878564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.al
ert_handler_stress_all_with_rand_reset.4122878564
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_intr_test.3725051184
Short name T271
Test name
Test status
Simulation time 24554770 ps
CPU time 2.3 seconds
Started Sep 04 03:20:51 PM UTC 24
Finished Sep 04 03:20:54 PM UTC 24
Peak memory 250540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725051184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3725051184
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3081142223
Short name T192
Test name
Test status
Simulation time 14894907318 ps
CPU time 1204.07 seconds
Started Sep 04 03:24:18 PM UTC 24
Finished Sep 04 03:44:38 PM UTC 24
Peak memory 285608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081142223 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shado
w_reg_errors_with_csr_rw.3081142223
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all.1440806469
Short name T57
Test name
Test status
Simulation time 97916119884 ps
CPU time 2027.68 seconds
Started Sep 04 01:40:03 PM UTC 24
Finished Sep 04 02:14:17 PM UTC 24
Peak memory 318424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440806469 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all.1440806469
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg.3177173775
Short name T369
Test name
Test status
Simulation time 411157058015 ps
CPU time 2394.33 seconds
Started Sep 04 02:15:53 PM UTC 24
Finished Sep 04 02:56:14 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177173775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3177173775
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/22.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy.1183473378
Short name T259
Test name
Test status
Simulation time 28907846941 ps
CPU time 952.91 seconds
Started Sep 04 01:49:04 PM UTC 24
Finished Sep 04 02:05:08 PM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183473378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1183473378
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.864971821
Short name T175
Test name
Test status
Simulation time 5157318322 ps
CPU time 215.83 seconds
Started Sep 04 03:29:25 PM UTC 24
Finished Sep 04 03:33:05 PM UTC 24
Peak memory 279464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864971821 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.864971821
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/10.alert_handler_ping_timeout.2127703673
Short name T341
Test name
Test status
Simulation time 20257770909 ps
CPU time 621.15 seconds
Started Sep 04 01:49:05 PM UTC 24
Finished Sep 04 01:59:34 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127703673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2127703673
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.171395357
Short name T185
Test name
Test status
Simulation time 12563098249 ps
CPU time 772.99 seconds
Started Sep 04 03:23:38 PM UTC 24
Finished Sep 04 03:36:42 PM UTC 24
Peak memory 279460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171395357 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow
_reg_errors_with_csr_rw.171395357
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/39.alert_handler_ping_timeout.3517536295
Short name T360
Test name
Test status
Simulation time 14186721148 ps
CPU time 557.92 seconds
Started Sep 04 02:54:27 PM UTC 24
Finished Sep 04 03:03:51 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517536295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3517536295
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg.1526524797
Short name T332
Test name
Test status
Simulation time 22288651419 ps
CPU time 1561.83 seconds
Started Sep 04 01:57:42 PM UTC 24
Finished Sep 04 02:24:02 PM UTC 24
Peak memory 301956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526524797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1526524797
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2700043863
Short name T176
Test name
Test status
Simulation time 21334953398 ps
CPU time 391.53 seconds
Started Sep 04 03:27:49 PM UTC 24
Finished Sep 04 03:34:27 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700043863 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.2700043863
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_classes.2546136562
Short name T25
Test name
Test status
Simulation time 85453006 ps
CPU time 13.82 seconds
Started Sep 04 01:39:48 PM UTC 24
Finished Sep 04 01:40:03 PM UTC 24
Peak memory 269356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546136562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2546136562
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy.2652110936
Short name T55
Test name
Test status
Simulation time 15623738346 ps
CPU time 1163.94 seconds
Started Sep 04 01:42:26 PM UTC 24
Finished Sep 04 02:02:03 PM UTC 24
Peak memory 299840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652110936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2652110936
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg.2679458459
Short name T371
Test name
Test status
Simulation time 93666780909 ps
CPU time 2542.97 seconds
Started Sep 04 02:24:41 PM UTC 24
Finished Sep 04 03:07:32 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679458459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2679458459
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/25.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2516400411
Short name T186
Test name
Test status
Simulation time 18067540879 ps
CPU time 589.32 seconds
Started Sep 04 03:26:40 PM UTC 24
Finished Sep 04 03:36:36 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516400411 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shad
ow_reg_errors_with_csr_rw.2516400411
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all.3555854828
Short name T280
Test name
Test status
Simulation time 6744310404 ps
CPU time 715.77 seconds
Started Sep 04 03:07:35 PM UTC 24
Finished Sep 04 03:19:40 PM UTC 24
Peak memory 279676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555854828 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all.3555854828
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/44.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all.1932048212
Short name T81
Test name
Test status
Simulation time 19697642477 ps
CPU time 275.43 seconds
Started Sep 04 01:42:49 PM UTC 24
Finished Sep 04 01:47:28 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932048212 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all.1932048212
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/18.alert_handler_ping_timeout.3869154459
Short name T71
Test name
Test status
Simulation time 9240688849 ps
CPU time 379.4 seconds
Started Sep 04 02:06:25 PM UTC 24
Finished Sep 04 02:12:49 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869154459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3869154459
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.1673778377
Short name T790
Test name
Test status
Simulation time 61238951 ps
CPU time 2.18 seconds
Started Sep 04 03:29:33 PM UTC 24
Finished Sep 04 03:29:36 PM UTC 24
Peak memory 250340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673778377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1673778377
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg.334902566
Short name T373
Test name
Test status
Simulation time 178675496840 ps
CPU time 2995.55 seconds
Started Sep 04 02:02:55 PM UTC 24
Finished Sep 04 02:53:24 PM UTC 24
Peak memory 300508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334902566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.334902566
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg.2135174865
Short name T708
Test name
Test status
Simulation time 59161147892 ps
CPU time 3465.08 seconds
Started Sep 04 02:52:53 PM UTC 24
Finished Sep 04 03:51:17 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135174865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2135174865
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/38.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all.2247698180
Short name T110
Test name
Test status
Simulation time 35806641181 ps
CPU time 2408.5 seconds
Started Sep 04 03:12:13 PM UTC 24
Finished Sep 04 03:52:49 PM UTC 24
Peak memory 304672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247698180 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all.2247698180
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/47.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.4123428850
Short name T159
Test name
Test status
Simulation time 743041385 ps
CPU time 131.98 seconds
Started Sep 04 03:19:43 PM UTC 24
Finished Sep 04 03:21:57 PM UTC 24
Peak memory 279460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123428850 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.4123428850
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/0.alert_handler_ping_timeout.978006536
Short name T15
Test name
Test status
Simulation time 5924845994 ps
CPU time 190.92 seconds
Started Sep 04 01:39:11 PM UTC 24
Finished Sep 04 01:42:25 PM UTC 24
Peak memory 269444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978006536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.978006536
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all.2311835055
Short name T283
Test name
Test status
Simulation time 305186351404 ps
CPU time 3906.03 seconds
Started Sep 04 02:48:49 PM UTC 24
Finished Sep 04 03:54:38 PM UTC 24
Peak memory 319328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311835055 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all.2311835055
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/36.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all.1751737452
Short name T112
Test name
Test status
Simulation time 67976483222 ps
CPU time 2071.58 seconds
Started Sep 04 01:47:44 PM UTC 24
Finished Sep 04 02:22:40 PM UTC 24
Peak memory 301948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751737452 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all.1751737452
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2276471126
Short name T161
Test name
Test status
Simulation time 872132101 ps
CPU time 103.24 seconds
Started Sep 04 03:23:47 PM UTC 24
Finished Sep 04 03:25:33 PM UTC 24
Peak memory 279332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276471126 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.2276471126
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3083317911
Short name T194
Test name
Test status
Simulation time 2396887003 ps
CPU time 484.28 seconds
Started Sep 04 03:29:23 PM UTC 24
Finished Sep 04 03:37:34 PM UTC 24
Peak memory 279656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083317911 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shad
ow_reg_errors_with_csr_rw.3083317911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.184028411
Short name T211
Test name
Test status
Simulation time 60676073 ps
CPU time 4.79 seconds
Started Sep 04 03:29:25 PM UTC 24
Finished Sep 04 03:29:31 PM UTC 24
Peak memory 252580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184028411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.184028411
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_alert_accum.544415120
Short name T76
Test name
Test status
Simulation time 1593747243 ps
CPU time 74.38 seconds
Started Sep 04 01:39:57 PM UTC 24
Finished Sep 04 01:41:13 PM UTC 24
Peak memory 269076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544415120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.544415120
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all.2694962575
Short name T293
Test name
Test status
Simulation time 137875288793 ps
CPU time 4762.87 seconds
Started Sep 04 02:05:25 PM UTC 24
Finished Sep 04 03:25:45 PM UTC 24
Peak memory 321056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694962575 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all.2694962575
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all_with_rand_reset.180266805
Short name T114
Test name
Test status
Simulation time 13704530450 ps
CPU time 474.15 seconds
Started Sep 04 02:07:00 PM UTC 24
Finished Sep 04 02:15:01 PM UTC 24
Peak memory 285696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=180266805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.al
ert_handler_stress_all_with_rand_reset.180266805
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg.1262115492
Short name T380
Test name
Test status
Simulation time 12428337225 ps
CPU time 833.82 seconds
Started Sep 04 03:00:13 PM UTC 24
Finished Sep 04 03:14:17 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262115492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1262115492
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/41.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/41.alert_handler_ping_timeout.2381783349
Short name T357
Test name
Test status
Simulation time 25610909579 ps
CPU time 275.84 seconds
Started Sep 04 02:59:50 PM UTC 24
Finished Sep 04 03:04:29 PM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381783349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2381783349
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_rw.753602949
Short name T209
Test name
Test status
Simulation time 198219382 ps
CPU time 15.37 seconds
Started Sep 04 03:18:22 PM UTC 24
Finished Sep 04 03:18:39 PM UTC 24
Peak memory 250328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753602949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.753602949
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/0.alert_handler_alert_accum_saturation.353885148
Short name T2
Test name
Test status
Simulation time 29872347 ps
CPU time 2.89 seconds
Started Sep 04 01:39:11 PM UTC 24
Finished Sep 04 01:39:15 PM UTC 24
Peak memory 262660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353885148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.353885148
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/1.alert_handler_alert_accum_saturation.973309523
Short name T13
Test name
Test status
Simulation time 42552689 ps
CPU time 5.47 seconds
Started Sep 04 01:39:36 PM UTC 24
Finished Sep 04 01:39:43 PM UTC 24
Peak memory 263172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973309523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.973309523
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/10.alert_handler_alert_accum_saturation.2765461168
Short name T244
Test name
Test status
Simulation time 27660834 ps
CPU time 4.17 seconds
Started Sep 04 01:49:25 PM UTC 24
Finished Sep 04 01:49:30 PM UTC 24
Peak memory 263504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765461168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2765461168
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/11.alert_handler_alert_accum_saturation.2531427822
Short name T245
Test name
Test status
Simulation time 60511576 ps
CPU time 4.96 seconds
Started Sep 04 01:50:56 PM UTC 24
Finished Sep 04 01:51:02 PM UTC 24
Peak memory 263176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531427822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2531427822
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all.134837234
Short name T289
Test name
Test status
Simulation time 37142538849 ps
CPU time 2320.61 seconds
Started Sep 04 01:58:30 PM UTC 24
Finished Sep 04 02:37:36 PM UTC 24
Peak memory 302204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134837234 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all.134837234
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all.4014164373
Short name T124
Test name
Test status
Simulation time 12388607998 ps
CPU time 1383.04 seconds
Started Sep 04 02:00:42 PM UTC 24
Finished Sep 04 02:24:02 PM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014164373 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all.4014164373
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all.2762923911
Short name T319
Test name
Test status
Simulation time 42851564401 ps
CPU time 2450.67 seconds
Started Sep 04 02:19:31 PM UTC 24
Finished Sep 04 03:00:50 PM UTC 24
Peak memory 304600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762923911 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all.2762923911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/23.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/25.alert_handler_sig_int_fail.3268837512
Short name T285
Test name
Test status
Simulation time 3542610464 ps
CPU time 40.81 seconds
Started Sep 04 02:24:06 PM UTC 24
Finished Sep 04 02:24:49 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268837512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3268837512
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.594309453
Short name T166
Test name
Test status
Simulation time 8565760612 ps
CPU time 622.43 seconds
Started Sep 04 03:17:17 PM UTC 24
Finished Sep 04 03:27:47 PM UTC 24
Peak memory 279596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594309453 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow
_reg_errors_with_csr_rw.594309453
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2828339649
Short name T201
Test name
Test status
Simulation time 2468647374 ps
CPU time 124.14 seconds
Started Sep 04 03:23:11 PM UTC 24
Finished Sep 04 03:25:18 PM UTC 24
Peak memory 250664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828339649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2828339649
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.315729121
Short name T183
Test name
Test status
Simulation time 4203336617 ps
CPU time 153.34 seconds
Started Sep 04 03:28:42 PM UTC 24
Finished Sep 04 03:31:18 PM UTC 24
Peak memory 279660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315729121 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.315729121
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/6.alert_handler_sig_int_fail.2214028013
Short name T49
Test name
Test status
Simulation time 172331811 ps
CPU time 20.27 seconds
Started Sep 04 01:43:13 PM UTC 24
Finished Sep 04 01:43:34 PM UTC 24
Peak memory 262944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214028013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2214028013
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all.1081059886
Short name T39
Test name
Test status
Simulation time 57885782242 ps
CPU time 1843.62 seconds
Started Sep 04 03:10:21 PM UTC 24
Finished Sep 04 03:41:28 PM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081059886 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all.1081059886
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/46.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1475216567
Short name T169
Test name
Test status
Simulation time 787239444 ps
CPU time 151.76 seconds
Started Sep 04 03:28:21 PM UTC 24
Finished Sep 04 03:30:56 PM UTC 24
Peak memory 279328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475216567 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.1475216567
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_intr_test.1896603991
Short name T198
Test name
Test status
Simulation time 6666082 ps
CPU time 2.47 seconds
Started Sep 04 03:18:05 PM UTC 24
Finished Sep 04 03:18:08 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896603991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1896603991
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/1.alert_handler_sec_cm.3040523784
Short name T8
Test name
Test status
Simulation time 428312913 ps
CPU time 25.7 seconds
Started Sep 04 01:39:42 PM UTC 24
Finished Sep 04 01:40:09 PM UTC 24
Peak memory 295268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040523784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3040523784
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg.71087820
Short name T334
Test name
Test status
Simulation time 45981824543 ps
CPU time 1641.71 seconds
Started Sep 04 01:49:05 PM UTC 24
Finished Sep 04 02:16:46 PM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71087820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.71087820
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/12.alert_handler_ping_timeout.2644888500
Short name T342
Test name
Test status
Simulation time 49881060745 ps
CPU time 582.04 seconds
Started Sep 04 01:52:38 PM UTC 24
Finished Sep 04 02:02:28 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644888500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2644888500
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/16.alert_handler_sig_int_fail.3557067851
Short name T98
Test name
Test status
Simulation time 74303823 ps
CPU time 13.54 seconds
Started Sep 04 02:02:29 PM UTC 24
Finished Sep 04 02:02:43 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557067851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3557067851
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/19.alert_handler_ping_timeout.29586732
Short name T265
Test name
Test status
Simulation time 7112488518 ps
CPU time 325.45 seconds
Started Sep 04 02:09:33 PM UTC 24
Finished Sep 04 02:15:03 PM UTC 24
Peak memory 263172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29586732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.29586732
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/21.alert_handler_sig_int_fail.1635781528
Short name T58
Test name
Test status
Simulation time 98984085 ps
CPU time 18.1 seconds
Started Sep 04 02:14:03 PM UTC 24
Finished Sep 04 02:14:23 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635781528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1635781528
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg.3407695118
Short name T366
Test name
Test status
Simulation time 116106652593 ps
CPU time 3019.8 seconds
Started Sep 04 02:26:40 PM UTC 24
Finished Sep 04 03:17:33 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407695118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3407695118
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/26.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all.3302376267
Short name T274
Test name
Test status
Simulation time 19427418631 ps
CPU time 1287.7 seconds
Started Sep 04 02:28:22 PM UTC 24
Finished Sep 04 02:50:04 PM UTC 24
Peak memory 281396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302376267 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all.3302376267
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/27.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/28.alert_handler_ping_timeout.1038330403
Short name T299
Test name
Test status
Simulation time 32569495124 ps
CPU time 496.72 seconds
Started Sep 04 02:29:27 PM UTC 24
Finished Sep 04 02:37:51 PM UTC 24
Peak memory 263304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038330403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1038330403
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all_with_rand_reset.2836748856
Short name T273
Test name
Test status
Simulation time 14954141200 ps
CPU time 529.63 seconds
Started Sep 04 02:53:23 PM UTC 24
Finished Sep 04 03:02:20 PM UTC 24
Peak memory 285620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2836748856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.a
lert_handler_stress_all_with_rand_reset.2836748856
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all.2832458165
Short name T277
Test name
Test status
Simulation time 6805028308 ps
CPU time 258.86 seconds
Started Sep 04 02:54:40 PM UTC 24
Finished Sep 04 02:59:03 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832458165 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all.2832458165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/39.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/40.alert_handler_sig_int_fail.329925476
Short name T151
Test name
Test status
Simulation time 296713323 ps
CPU time 38.66 seconds
Started Sep 04 02:56:17 PM UTC 24
Finished Sep 04 02:56:57 PM UTC 24
Peak memory 269408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329925476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.329925476
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/42.alert_handler_ping_timeout.3528689184
Short name T354
Test name
Test status
Simulation time 43546501007 ps
CPU time 545.81 seconds
Started Sep 04 03:01:57 PM UTC 24
Finished Sep 04 03:11:10 PM UTC 24
Peak memory 269448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528689184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3528689184
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all_with_rand_reset.2552693529
Short name T261
Test name
Test status
Simulation time 5851107062 ps
CPU time 274.39 seconds
Started Sep 04 03:05:05 PM UTC 24
Finished Sep 04 03:09:43 PM UTC 24
Peak memory 279476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2552693529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.a
lert_handler_stress_all_with_rand_reset.2552693529
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all.1861482547
Short name T292
Test name
Test status
Simulation time 32016863364 ps
CPU time 1786.25 seconds
Started Sep 04 03:09:05 PM UTC 24
Finished Sep 04 03:39:11 PM UTC 24
Peak memory 295804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861482547 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all.1861482547
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/45.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/46.alert_handler_sig_int_fail.370716080
Short name T276
Test name
Test status
Simulation time 3299907067 ps
CPU time 64.57 seconds
Started Sep 04 03:09:49 PM UTC 24
Finished Sep 04 03:10:55 PM UTC 24
Peak memory 269472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370716080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.370716080
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all.38147552
Short name T287
Test name
Test status
Simulation time 242876391235 ps
CPU time 3577.75 seconds
Started Sep 04 03:15:00 PM UTC 24
Finished Sep 04 04:15:18 PM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38147552 -assert nopostproc +UVM_TES
TNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all.38147552
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/48.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all_with_rand_reset.2860206317
Short name T38
Test name
Test status
Simulation time 43486624206 ps
CPU time 352.6 seconds
Started Sep 04 02:16:39 PM UTC 24
Finished Sep 04 02:22:36 PM UTC 24
Peak memory 281524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2860206317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.a
lert_handler_stress_all_with_rand_reset.2860206317
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2216379971
Short name T205
Test name
Test status
Simulation time 928377624 ps
CPU time 90.05 seconds
Started Sep 04 03:26:24 PM UTC 24
Finished Sep 04 03:27:56 PM UTC 24
Peak memory 252440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216379971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2216379971
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_intg_err.271475137
Short name T204
Test name
Test status
Simulation time 2999674183 ps
CPU time 39.86 seconds
Started Sep 04 03:24:41 PM UTC 24
Finished Sep 04 03:25:23 PM UTC 24
Peak memory 252564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271475137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.271475137
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3369583174
Short name T193
Test name
Test status
Simulation time 7650617263 ps
CPU time 616.59 seconds
Started Sep 04 03:25:00 PM UTC 24
Finished Sep 04 03:35:25 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369583174 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shado
w_reg_errors_with_csr_rw.3369583174
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3869144708
Short name T206
Test name
Test status
Simulation time 116348208 ps
CPU time 6.85 seconds
Started Sep 04 03:28:29 PM UTC 24
Finished Sep 04 03:28:37 PM UTC 24
Peak memory 250388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869144708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3869144708
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2386465358
Short name T207
Test name
Test status
Simulation time 152391308 ps
CPU time 11.92 seconds
Started Sep 04 03:29:12 PM UTC 24
Finished Sep 04 03:29:25 PM UTC 24
Peak memory 250388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386465358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2386465358
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_alerts.3146340126
Short name T33
Test name
Test status
Simulation time 897090102 ps
CPU time 73.58 seconds
Started Sep 04 01:41:04 PM UTC 24
Finished Sep 04 01:42:19 PM UTC 24
Peak memory 269156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146340126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3146340126
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_intg_err.753674485
Short name T195
Test name
Test status
Simulation time 58792976 ps
CPU time 5.88 seconds
Started Sep 04 03:20:09 PM UTC 24
Finished Sep 04 03:20:16 PM UTC 24
Peak memory 250388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753674485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.753674485
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.579466081
Short name T177
Test name
Test status
Simulation time 2069762634 ps
CPU time 235.71 seconds
Started Sep 04 03:26:21 PM UTC 24
Finished Sep 04 03:30:21 PM UTC 24
Peak memory 279468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579466081 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.579466081
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3261306150
Short name T203
Test name
Test status
Simulation time 4494940640 ps
CPU time 100.44 seconds
Started Sep 04 03:27:14 PM UTC 24
Finished Sep 04 03:28:57 PM UTC 24
Peak memory 262804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261306150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3261306150
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.767807220
Short name T178
Test name
Test status
Simulation time 10184367371 ps
CPU time 226.88 seconds
Started Sep 04 03:28:06 PM UTC 24
Finished Sep 04 03:31:57 PM UTC 24
Peak memory 279596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767807220 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.767807220
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.724483298
Short name T179
Test name
Test status
Simulation time 2931679488 ps
CPU time 342.58 seconds
Started Sep 04 03:28:06 PM UTC 24
Finished Sep 04 03:33:53 PM UTC 24
Peak memory 285804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724483298 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shado
w_reg_errors_with_csr_rw.724483298
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_intg_err.540364764
Short name T212
Test name
Test status
Simulation time 68048954 ps
CPU time 4.82 seconds
Started Sep 04 03:25:15 PM UTC 24
Finished Sep 04 03:25:21 PM UTC 24
Peak memory 250528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540364764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.540364764
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3716281586
Short name T215
Test name
Test status
Simulation time 189651705 ps
CPU time 30.34 seconds
Started Sep 04 03:26:10 PM UTC 24
Finished Sep 04 03:26:42 PM UTC 24
Peak memory 252436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716281586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3716281586
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2912252942
Short name T197
Test name
Test status
Simulation time 1796570766 ps
CPU time 55.75 seconds
Started Sep 04 03:20:51 PM UTC 24
Finished Sep 04 03:21:48 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912252942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2912252942
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_intg_err.299943878
Short name T202
Test name
Test status
Simulation time 1210379279 ps
CPU time 64.03 seconds
Started Sep 04 03:22:11 PM UTC 24
Finished Sep 04 03:23:17 PM UTC 24
Peak memory 252440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299943878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te
st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.299943878
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2059336147
Short name T214
Test name
Test status
Simulation time 1790451949 ps
CPU time 41.79 seconds
Started Sep 04 03:25:34 PM UTC 24
Finished Sep 04 03:26:17 PM UTC 24
Peak memory 252520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059336147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2059336147
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3787576723
Short name T216
Test name
Test status
Simulation time 5201970694 ps
CPU time 132.88 seconds
Started Sep 04 03:25:51 PM UTC 24
Finished Sep 04 03:28:06 PM UTC 24
Peak memory 252572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787576723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3787576723
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3058846827
Short name T234
Test name
Test status
Simulation time 2235292209 ps
CPU time 96.06 seconds
Started Sep 04 03:18:40 PM UTC 24
Finished Sep 04 03:20:18 PM UTC 24
Peak memory 250588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058846827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3058846827
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.4053711628
Short name T232
Test name
Test status
Simulation time 10992293410 ps
CPU time 277.83 seconds
Started Sep 04 03:18:29 PM UTC 24
Finished Sep 04 03:23:11 PM UTC 24
Peak memory 250460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053711628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.4053711628
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2166038950
Short name T199
Test name
Test status
Simulation time 554126110 ps
CPU time 10.73 seconds
Started Sep 04 03:18:09 PM UTC 24
Finished Sep 04 03:18:21 PM UTC 24
Peak memory 262612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166038950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2166038950
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1066672718
Short name T210
Test name
Test status
Simulation time 123173182 ps
CPU time 14.42 seconds
Started Sep 04 03:19:26 PM UTC 24
Finished Sep 04 03:19:42 PM UTC 24
Peak memory 262740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066672718 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_
rw_with_rand_reset.1066672718
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.4035549395
Short name T225
Test name
Test status
Simulation time 509935488 ps
CPU time 56.32 seconds
Started Sep 04 03:19:22 PM UTC 24
Finished Sep 04 03:20:20 PM UTC 24
Peak memory 260704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035549395 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.4035549395
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_errors.794430166
Short name T262
Test name
Test status
Simulation time 218775477 ps
CPU time 21.31 seconds
Started Sep 04 03:17:36 PM UTC 24
Finished Sep 04 03:17:58 PM UTC 24
Peak memory 262816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794430166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.794430166
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3264438024
Short name T233
Test name
Test status
Simulation time 8731574511 ps
CPU time 202.82 seconds
Started Sep 04 03:20:20 PM UTC 24
Finished Sep 04 03:23:46 PM UTC 24
Peak memory 252644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264438024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3264438024
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.903821542
Short name T726
Test name
Test status
Simulation time 1709619907 ps
CPU time 285.74 seconds
Started Sep 04 03:20:19 PM UTC 24
Finished Sep 04 03:25:09 PM UTC 24
Peak memory 252516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903821542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/al
ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.903821542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3325239478
Short name T237
Test name
Test status
Simulation time 22690325 ps
CPU time 5.73 seconds
Started Sep 04 03:20:16 PM UTC 24
Finished Sep 04 03:20:22 PM UTC 24
Peak memory 262616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325239478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3325239478
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.596749583
Short name T240
Test name
Test status
Simulation time 497969559 ps
CPU time 15.07 seconds
Started Sep 04 03:20:21 PM UTC 24
Finished Sep 04 03:20:38 PM UTC 24
Peak memory 252508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596749583 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_r
w_with_rand_reset.596749583
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_rw.373928497
Short name T238
Test name
Test status
Simulation time 203343433 ps
CPU time 7.39 seconds
Started Sep 04 03:20:18 PM UTC 24
Finished Sep 04 03:20:28 PM UTC 24
Peak memory 252376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373928497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.373928497
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_intr_test.828221979
Short name T200
Test name
Test status
Simulation time 10784273 ps
CPU time 2.18 seconds
Started Sep 04 03:20:12 PM UTC 24
Finished Sep 04 03:20:15 PM UTC 24
Peak memory 250340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828221979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.828221979
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.161567605
Short name T228
Test name
Test status
Simulation time 2519763843 ps
CPU time 79.02 seconds
Started Sep 04 03:20:21 PM UTC 24
Finished Sep 04 03:21:42 PM UTC 24
Peak memory 262944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161567605 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.161567605
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2696324190
Short name T168
Test name
Test status
Simulation time 16332143860 ps
CPU time 589.76 seconds
Started Sep 04 03:19:43 PM UTC 24
Finished Sep 04 03:29:40 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696324190 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shado
w_reg_errors_with_csr_rw.2696324190
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_errors.257314580
Short name T267
Test name
Test status
Simulation time 237423323 ps
CPU time 26.31 seconds
Started Sep 04 03:19:43 PM UTC 24
Finished Sep 04 03:20:10 PM UTC 24
Peak memory 262756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257314580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.257314580
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1799935566
Short name T747
Test name
Test status
Simulation time 419100821 ps
CPU time 6.87 seconds
Started Sep 04 03:26:19 PM UTC 24
Finished Sep 04 03:26:27 PM UTC 24
Peak memory 252572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799935566 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_mem
_rw_with_rand_reset.1799935566
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_rw.3004080180
Short name T746
Test name
Test status
Simulation time 65940865 ps
CPU time 7.9 seconds
Started Sep 04 03:26:17 PM UTC 24
Finished Sep 04 03:26:26 PM UTC 24
Peak memory 252376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004080180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3004080180
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_intr_test.2351241528
Short name T743
Test name
Test status
Simulation time 8732489 ps
CPU time 2.05 seconds
Started Sep 04 03:26:16 PM UTC 24
Finished Sep 04 03:26:19 PM UTC 24
Peak memory 250340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351241528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2351241528
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1463852970
Short name T750
Test name
Test status
Simulation time 267675795 ps
CPU time 26.35 seconds
Started Sep 04 03:26:18 PM UTC 24
Finished Sep 04 03:26:45 PM UTC 24
Peak memory 260768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463852970 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outstanding.1463852970
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.963920320
Short name T182
Test name
Test status
Simulation time 3227034452 ps
CPU time 169.9 seconds
Started Sep 04 03:26:08 PM UTC 24
Finished Sep 04 03:29:01 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963920320 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.963920320
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2050261455
Short name T190
Test name
Test status
Simulation time 6324618236 ps
CPU time 599.44 seconds
Started Sep 04 03:26:07 PM UTC 24
Finished Sep 04 03:36:14 PM UTC 24
Peak memory 279592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050261455 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shad
ow_reg_errors_with_csr_rw.2050261455
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_errors.58590014
Short name T749
Test name
Test status
Simulation time 606498672 ps
CPU time 32.13 seconds
Started Sep 04 03:26:08 PM UTC 24
Finished Sep 04 03:26:41 PM UTC 24
Peak memory 262756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58590014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handle
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.58590014
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3471253965
Short name T752
Test name
Test status
Simulation time 499677756 ps
CPU time 7.43 seconds
Started Sep 04 03:26:40 PM UTC 24
Finished Sep 04 03:26:48 PM UTC 24
Peak memory 252500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471253965 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_mem
_rw_with_rand_reset.3471253965
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_rw.4199342887
Short name T748
Test name
Test status
Simulation time 127615448 ps
CPU time 8.95 seconds
Started Sep 04 03:26:27 PM UTC 24
Finished Sep 04 03:26:37 PM UTC 24
Peak memory 250400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199342887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.4199342887
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_intr_test.2831228710
Short name T391
Test name
Test status
Simulation time 8549856 ps
CPU time 2.09 seconds
Started Sep 04 03:26:27 PM UTC 24
Finished Sep 04 03:26:30 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831228710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2831228710
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4088101631
Short name T756
Test name
Test status
Simulation time 5625154185 ps
CPU time 26.2 seconds
Started Sep 04 03:26:31 PM UTC 24
Finished Sep 04 03:26:59 PM UTC 24
Peak memory 262880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088101631 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outstanding.4088101631
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1820473061
Short name T395
Test name
Test status
Simulation time 48819017609 ps
CPU time 955.99 seconds
Started Sep 04 03:26:20 PM UTC 24
Finished Sep 04 03:42:27 PM UTC 24
Peak memory 285800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820473061 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shad
ow_reg_errors_with_csr_rw.1820473061
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_errors.3469962487
Short name T751
Test name
Test status
Simulation time 295335318 ps
CPU time 22.7 seconds
Started Sep 04 03:26:22 PM UTC 24
Finished Sep 04 03:26:46 PM UTC 24
Peak memory 262828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469962487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3469962487
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2369348268
Short name T757
Test name
Test status
Simulation time 337250156 ps
CPU time 15.39 seconds
Started Sep 04 03:26:53 PM UTC 24
Finished Sep 04 03:27:10 PM UTC 24
Peak memory 264788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369348268 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_mem
_rw_with_rand_reset.2369348268
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_rw.1638382235
Short name T755
Test name
Test status
Simulation time 65337367 ps
CPU time 7.49 seconds
Started Sep 04 03:26:49 PM UTC 24
Finished Sep 04 03:26:58 PM UTC 24
Peak memory 250464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638382235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1638382235
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_intr_test.799897496
Short name T753
Test name
Test status
Simulation time 6316015 ps
CPU time 2.25 seconds
Started Sep 04 03:26:47 PM UTC 24
Finished Sep 04 03:26:51 PM UTC 24
Peak memory 248284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799897496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.799897496
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.982787999
Short name T760
Test name
Test status
Simulation time 504749123 ps
CPU time 52.24 seconds
Started Sep 04 03:26:51 PM UTC 24
Finished Sep 04 03:27:45 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982787999 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outstanding.982787999
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3782851155
Short name T171
Test name
Test status
Simulation time 10577671830 ps
CPU time 236.65 seconds
Started Sep 04 03:26:42 PM UTC 24
Finished Sep 04 03:30:42 PM UTC 24
Peak memory 279592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782851155 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.3782851155
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_errors.64402357
Short name T754
Test name
Test status
Simulation time 44877010 ps
CPU time 8.12 seconds
Started Sep 04 03:26:43 PM UTC 24
Finished Sep 04 03:26:52 PM UTC 24
Peak memory 262756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64402357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handle
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.64402357
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2038984910
Short name T213
Test name
Test status
Simulation time 1072623022 ps
CPU time 55.05 seconds
Started Sep 04 03:26:46 PM UTC 24
Finished Sep 04 03:27:43 PM UTC 24
Peak memory 250384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038984910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2038984910
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.722172634
Short name T762
Test name
Test status
Simulation time 442565792 ps
CPU time 10.12 seconds
Started Sep 04 03:27:46 PM UTC 24
Finished Sep 04 03:27:58 PM UTC 24
Peak memory 252636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722172634 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_mem_
rw_with_rand_reset.722172634
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_rw.2717383211
Short name T764
Test name
Test status
Simulation time 134893282 ps
CPU time 14.8 seconds
Started Sep 04 03:27:43 PM UTC 24
Finished Sep 04 03:27:59 PM UTC 24
Peak memory 250464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717383211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2717383211
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_intr_test.612169406
Short name T759
Test name
Test status
Simulation time 9595496 ps
CPU time 2.2 seconds
Started Sep 04 03:27:39 PM UTC 24
Finished Sep 04 03:27:42 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612169406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.612169406
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.55344353
Short name T763
Test name
Test status
Simulation time 92573042 ps
CPU time 13.5 seconds
Started Sep 04 03:27:44 PM UTC 24
Finished Sep 04 03:27:59 PM UTC 24
Peak memory 260828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55344353 -assert nopostproc +UVM_TESTNAME=alert_handler
_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outstanding.55344353
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2001621328
Short name T174
Test name
Test status
Simulation time 3777764509 ps
CPU time 279.12 seconds
Started Sep 04 03:27:00 PM UTC 24
Finished Sep 04 03:31:43 PM UTC 24
Peak memory 279592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001621328 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.2001621328
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1427865387
Short name T173
Test name
Test status
Simulation time 2227837153 ps
CPU time 342.83 seconds
Started Sep 04 03:26:59 PM UTC 24
Finished Sep 04 03:32:47 PM UTC 24
Peak memory 281512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427865387 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shad
ow_reg_errors_with_csr_rw.1427865387
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_errors.1506358129
Short name T758
Test name
Test status
Simulation time 1173218452 ps
CPU time 26.07 seconds
Started Sep 04 03:27:11 PM UTC 24
Finished Sep 04 03:27:38 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506358129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1506358129
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.268541251
Short name T766
Test name
Test status
Simulation time 166106951 ps
CPU time 6.71 seconds
Started Sep 04 03:28:04 PM UTC 24
Finished Sep 04 03:28:12 PM UTC 24
Peak memory 269020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268541251 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_mem_
rw_with_rand_reset.268541251
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_rw.1935121022
Short name T769
Test name
Test status
Simulation time 517964258 ps
CPU time 15.13 seconds
Started Sep 04 03:28:00 PM UTC 24
Finished Sep 04 03:28:17 PM UTC 24
Peak memory 250328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935121022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1935121022
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_intr_test.2215365237
Short name T765
Test name
Test status
Simulation time 7354358 ps
CPU time 1.77 seconds
Started Sep 04 03:28:00 PM UTC 24
Finished Sep 04 03:28:03 PM UTC 24
Peak memory 246796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215365237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2215365237
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.4238185935
Short name T776
Test name
Test status
Simulation time 169860282 ps
CPU time 34.72 seconds
Started Sep 04 03:28:04 PM UTC 24
Finished Sep 04 03:28:40 PM UTC 24
Peak memory 262816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238185935 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outstanding.4238185935
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3165616207
Short name T189
Test name
Test status
Simulation time 56095135138 ps
CPU time 1092.88 seconds
Started Sep 04 03:27:49 PM UTC 24
Finished Sep 04 03:46:15 PM UTC 24
Peak memory 285596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165616207 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shad
ow_reg_errors_with_csr_rw.3165616207
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_errors.1754207570
Short name T767
Test name
Test status
Simulation time 143891507 ps
CPU time 13.92 seconds
Started Sep 04 03:27:58 PM UTC 24
Finished Sep 04 03:28:13 PM UTC 24
Peak memory 262828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754207570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1754207570
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2648986616
Short name T208
Test name
Test status
Simulation time 636877066 ps
CPU time 36.72 seconds
Started Sep 04 03:27:59 PM UTC 24
Finished Sep 04 03:28:37 PM UTC 24
Peak memory 252436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648986616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2648986616
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2377269883
Short name T773
Test name
Test status
Simulation time 104532725 ps
CPU time 8.85 seconds
Started Sep 04 03:28:17 PM UTC 24
Finished Sep 04 03:28:28 PM UTC 24
Peak memory 254508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377269883 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_mem
_rw_with_rand_reset.2377269883
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_rw.501155790
Short name T772
Test name
Test status
Simulation time 122998447 ps
CPU time 7.9 seconds
Started Sep 04 03:28:14 PM UTC 24
Finished Sep 04 03:28:23 PM UTC 24
Peak memory 252512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501155790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.501155790
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_intr_test.3214197657
Short name T768
Test name
Test status
Simulation time 12604937 ps
CPU time 2.51 seconds
Started Sep 04 03:28:13 PM UTC 24
Finished Sep 04 03:28:16 PM UTC 24
Peak memory 250340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214197657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3214197657
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1051819049
Short name T774
Test name
Test status
Simulation time 88546024 ps
CPU time 17.25 seconds
Started Sep 04 03:28:17 PM UTC 24
Finished Sep 04 03:28:37 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051819049 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outstanding.1051819049
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_errors.1314682682
Short name T771
Test name
Test status
Simulation time 102546979 ps
CPU time 11.04 seconds
Started Sep 04 03:28:07 PM UTC 24
Finished Sep 04 03:28:19 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314682682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1314682682
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1612649902
Short name T770
Test name
Test status
Simulation time 61690126 ps
CPU time 5.97 seconds
Started Sep 04 03:28:10 PM UTC 24
Finished Sep 04 03:28:17 PM UTC 24
Peak memory 252432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612649902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1612649902
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1737581663
Short name T779
Test name
Test status
Simulation time 156049801 ps
CPU time 10.44 seconds
Started Sep 04 03:28:38 PM UTC 24
Finished Sep 04 03:28:50 PM UTC 24
Peak memory 252636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737581663 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_mem
_rw_with_rand_reset.1737581663
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.2512710810
Short name T778
Test name
Test status
Simulation time 51623114 ps
CPU time 7.12 seconds
Started Sep 04 03:28:38 PM UTC 24
Finished Sep 04 03:28:46 PM UTC 24
Peak memory 250400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512710810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2512710810
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.2425316586
Short name T777
Test name
Test status
Simulation time 29633143 ps
CPU time 2.17 seconds
Started Sep 04 03:28:38 PM UTC 24
Finished Sep 04 03:28:41 PM UTC 24
Peak memory 248288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425316586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2425316586
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3325379114
Short name T783
Test name
Test status
Simulation time 262750062 ps
CPU time 31.01 seconds
Started Sep 04 03:28:38 PM UTC 24
Finished Sep 04 03:29:10 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325379114 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outstanding.3325379114
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1886707203
Short name T394
Test name
Test status
Simulation time 154939574577 ps
CPU time 545.46 seconds
Started Sep 04 03:28:18 PM UTC 24
Finished Sep 04 03:37:31 PM UTC 24
Peak memory 279412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886707203 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shad
ow_reg_errors_with_csr_rw.1886707203
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.1885086305
Short name T775
Test name
Test status
Simulation time 241559779 ps
CPU time 11.85 seconds
Started Sep 04 03:28:24 PM UTC 24
Finished Sep 04 03:28:37 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885086305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1885086305
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.4282547071
Short name T784
Test name
Test status
Simulation time 566352816 ps
CPU time 18.16 seconds
Started Sep 04 03:28:56 PM UTC 24
Finished Sep 04 03:29:15 PM UTC 24
Peak memory 264860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282547071 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_mem
_rw_with_rand_reset.4282547071
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.1783579271
Short name T782
Test name
Test status
Simulation time 181681171 ps
CPU time 5.83 seconds
Started Sep 04 03:28:51 PM UTC 24
Finished Sep 04 03:28:57 PM UTC 24
Peak memory 250464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783579271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1783579271
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.1465496459
Short name T780
Test name
Test status
Simulation time 8594945 ps
CPU time 1.74 seconds
Started Sep 04 03:28:49 PM UTC 24
Finished Sep 04 03:28:52 PM UTC 24
Peak memory 248848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465496459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1465496459
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.253132809
Short name T785
Test name
Test status
Simulation time 371718979 ps
CPU time 23.3 seconds
Started Sep 04 03:28:53 PM UTC 24
Finished Sep 04 03:29:17 PM UTC 24
Peak memory 262816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253132809 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outstanding.253132809
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3624597032
Short name T396
Test name
Test status
Simulation time 25942723733 ps
CPU time 479.95 seconds
Started Sep 04 03:28:41 PM UTC 24
Finished Sep 04 03:36:47 PM UTC 24
Peak memory 279592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624597032 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shad
ow_reg_errors_with_csr_rw.3624597032
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.502541295
Short name T781
Test name
Test status
Simulation time 218673529 ps
CPU time 10.22 seconds
Started Sep 04 03:28:43 PM UTC 24
Finished Sep 04 03:28:55 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502541295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.502541295
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3530488480
Short name T294
Test name
Test status
Simulation time 954057241 ps
CPU time 34.17 seconds
Started Sep 04 03:28:48 PM UTC 24
Finished Sep 04 03:29:24 PM UTC 24
Peak memory 250524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530488480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3530488480
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2059324419
Short name T789
Test name
Test status
Simulation time 349136768 ps
CPU time 10.79 seconds
Started Sep 04 03:29:22 PM UTC 24
Finished Sep 04 03:29:34 PM UTC 24
Peak memory 252572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059324419 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_mem
_rw_with_rand_reset.2059324419
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.1810316261
Short name T788
Test name
Test status
Simulation time 256505579 ps
CPU time 5.29 seconds
Started Sep 04 03:29:18 PM UTC 24
Finished Sep 04 03:29:25 PM UTC 24
Peak memory 250400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810316261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1810316261
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.3204834485
Short name T786
Test name
Test status
Simulation time 12791708 ps
CPU time 2.08 seconds
Started Sep 04 03:29:16 PM UTC 24
Finished Sep 04 03:29:19 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204834485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3204834485
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.911308076
Short name T800
Test name
Test status
Simulation time 308362925 ps
CPU time 26.52 seconds
Started Sep 04 03:29:22 PM UTC 24
Finished Sep 04 03:29:50 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911308076 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outstanding.911308076
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.116387925
Short name T397
Test name
Test status
Simulation time 24787310470 ps
CPU time 1110.65 seconds
Started Sep 04 03:28:57 PM UTC 24
Finished Sep 04 03:47:41 PM UTC 24
Peak memory 279596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116387925 -assert
nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shado
w_reg_errors_with_csr_rw.116387925
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.3289810605
Short name T787
Test name
Test status
Simulation time 719154813 ps
CPU time 18.91 seconds
Started Sep 04 03:29:02 PM UTC 24
Finished Sep 04 03:29:22 PM UTC 24
Peak memory 267052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289810605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3289810605
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1637415482
Short name T797
Test name
Test status
Simulation time 345493787 ps
CPU time 8.86 seconds
Started Sep 04 03:29:37 PM UTC 24
Finished Sep 04 03:29:47 PM UTC 24
Peak memory 252572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637415482 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_mem
_rw_with_rand_reset.1637415482
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.1544145419
Short name T742
Test name
Test status
Simulation time 54024735 ps
CPU time 7.85 seconds
Started Sep 04 03:29:35 PM UTC 24
Finished Sep 04 03:29:44 PM UTC 24
Peak memory 250328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544145419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1544145419
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2330354677
Short name T825
Test name
Test status
Simulation time 7410860197 ps
CPU time 41.2 seconds
Started Sep 04 03:29:36 PM UTC 24
Finished Sep 04 03:30:19 PM UTC 24
Peak memory 260756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330354677 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outstanding.2330354677
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.3578787117
Short name T792
Test name
Test status
Simulation time 156874866 ps
CPU time 13.97 seconds
Started Sep 04 03:29:25 PM UTC 24
Finished Sep 04 03:29:40 PM UTC 24
Peak memory 266692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578787117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3578787117
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2387765184
Short name T724
Test name
Test status
Simulation time 1680322896 ps
CPU time 181.01 seconds
Started Sep 04 03:21:45 PM UTC 24
Finished Sep 04 03:24:49 PM UTC 24
Peak memory 252380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387765184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2387765184
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1211282083
Short name T722
Test name
Test status
Simulation time 1950774028 ps
CPU time 204.81 seconds
Started Sep 04 03:21:15 PM UTC 24
Finished Sep 04 03:24:43 PM UTC 24
Peak memory 250328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211282083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1211282083
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3342649694
Short name T226
Test name
Test status
Simulation time 276553654 ps
CPU time 8.49 seconds
Started Sep 04 03:20:55 PM UTC 24
Finished Sep 04 03:21:05 PM UTC 24
Peak memory 252376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342649694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3342649694
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1133571064
Short name T392
Test name
Test status
Simulation time 83876063 ps
CPU time 13.24 seconds
Started Sep 04 03:21:49 PM UTC 24
Finished Sep 04 03:22:03 PM UTC 24
Peak memory 252640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133571064 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_
rw_with_rand_reset.1133571064
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_rw.2399148158
Short name T227
Test name
Test status
Simulation time 97716113 ps
CPU time 6.96 seconds
Started Sep 04 03:21:05 PM UTC 24
Finished Sep 04 03:21:13 PM UTC 24
Peak memory 252376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399148158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2399148158
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.4271068517
Short name T229
Test name
Test status
Simulation time 1056253417 ps
CPU time 19.84 seconds
Started Sep 04 03:21:45 PM UTC 24
Finished Sep 04 03:22:06 PM UTC 24
Peak memory 252440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271068517 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.4271068517
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2871885111
Short name T180
Test name
Test status
Simulation time 8924663098 ps
CPU time 218.85 seconds
Started Sep 04 03:20:28 PM UTC 24
Finished Sep 04 03:24:11 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871885111 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.2871885111
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3006690847
Short name T163
Test name
Test status
Simulation time 21982242073 ps
CPU time 456.02 seconds
Started Sep 04 03:20:23 PM UTC 24
Finished Sep 04 03:28:05 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006690847 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shado
w_reg_errors_with_csr_rw.3006690847
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_errors.2875811119
Short name T715
Test name
Test status
Simulation time 51009633 ps
CPU time 10.26 seconds
Started Sep 04 03:20:38 PM UTC 24
Finished Sep 04 03:20:50 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875811119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2875811119
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.3227629597
Short name T793
Test name
Test status
Simulation time 28411319 ps
CPU time 2.06 seconds
Started Sep 04 03:29:38 PM UTC 24
Finished Sep 04 03:29:41 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227629597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3227629597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/20.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.1019440183
Short name T794
Test name
Test status
Simulation time 16869350 ps
CPU time 2.01 seconds
Started Sep 04 03:29:41 PM UTC 24
Finished Sep 04 03:29:44 PM UTC 24
Peak memory 248424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019440183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1019440183
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/21.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.828447846
Short name T795
Test name
Test status
Simulation time 6504727 ps
CPU time 2.16 seconds
Started Sep 04 03:29:42 PM UTC 24
Finished Sep 04 03:29:46 PM UTC 24
Peak memory 250332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828447846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.828447846
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/22.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.1230102546
Short name T796
Test name
Test status
Simulation time 26151280 ps
CPU time 2.36 seconds
Started Sep 04 03:29:43 PM UTC 24
Finished Sep 04 03:29:46 PM UTC 24
Peak memory 250412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230102546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1230102546
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/23.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.2909086297
Short name T799
Test name
Test status
Simulation time 7980023 ps
CPU time 2.08 seconds
Started Sep 04 03:29:45 PM UTC 24
Finished Sep 04 03:29:48 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909086297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2909086297
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/24.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.2562115477
Short name T798
Test name
Test status
Simulation time 11326134 ps
CPU time 1.98 seconds
Started Sep 04 03:29:45 PM UTC 24
Finished Sep 04 03:29:48 PM UTC 24
Peak memory 248848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562115477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.2562115477
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/25.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.1265834044
Short name T802
Test name
Test status
Simulation time 11276666 ps
CPU time 2.51 seconds
Started Sep 04 03:29:48 PM UTC 24
Finished Sep 04 03:29:51 PM UTC 24
Peak memory 250344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265834044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1265834044
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/26.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.1015249248
Short name T801
Test name
Test status
Simulation time 18878145 ps
CPU time 2.03 seconds
Started Sep 04 03:29:48 PM UTC 24
Finished Sep 04 03:29:51 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015249248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1015249248
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/27.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.1618325133
Short name T804
Test name
Test status
Simulation time 8261076 ps
CPU time 2.45 seconds
Started Sep 04 03:29:49 PM UTC 24
Finished Sep 04 03:29:53 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618325133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1618325133
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/28.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.4004187481
Short name T803
Test name
Test status
Simulation time 7770694 ps
CPU time 2.34 seconds
Started Sep 04 03:29:49 PM UTC 24
Finished Sep 04 03:29:53 PM UTC 24
Peak memory 250312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004187481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.4004187481
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/29.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2732812539
Short name T235
Test name
Test status
Simulation time 544433073 ps
CPU time 92.51 seconds
Started Sep 04 03:22:30 PM UTC 24
Finished Sep 04 03:24:05 PM UTC 24
Peak memory 250332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732812539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2732812539
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3113068038
Short name T745
Test name
Test status
Simulation time 1639117271 ps
CPU time 228.74 seconds
Started Sep 04 03:22:28 PM UTC 24
Finished Sep 04 03:26:21 PM UTC 24
Peak memory 250332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113068038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3113068038
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3964070014
Short name T717
Test name
Test status
Simulation time 41384384 ps
CPU time 9.02 seconds
Started Sep 04 03:22:17 PM UTC 24
Finished Sep 04 03:22:27 PM UTC 24
Peak memory 252516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964070014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3964070014
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1799346449
Short name T393
Test name
Test status
Simulation time 502017370 ps
CPU time 8.04 seconds
Started Sep 04 03:22:40 PM UTC 24
Finished Sep 04 03:22:49 PM UTC 24
Peak memory 252504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799346449 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_
rw_with_rand_reset.1799346449
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_rw.3095660036
Short name T230
Test name
Test status
Simulation time 64427732 ps
CPU time 7.25 seconds
Started Sep 04 03:22:21 PM UTC 24
Finished Sep 04 03:22:30 PM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095660036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3095660036
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_intr_test.1841457956
Short name T386
Test name
Test status
Simulation time 16590422 ps
CPU time 2.35 seconds
Started Sep 04 03:22:13 PM UTC 24
Finished Sep 04 03:22:16 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841457956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1841457956
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1818376396
Short name T231
Test name
Test status
Simulation time 92936869 ps
CPU time 17.96 seconds
Started Sep 04 03:22:40 PM UTC 24
Finished Sep 04 03:22:59 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818376396 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.1818376396
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2478953476
Short name T181
Test name
Test status
Simulation time 51161346500 ps
CPU time 304.4 seconds
Started Sep 04 03:22:04 PM UTC 24
Finished Sep 04 03:27:13 PM UTC 24
Peak memory 279596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478953476 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.2478953476
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2352649619
Short name T191
Test name
Test status
Simulation time 36100238542 ps
CPU time 704.64 seconds
Started Sep 04 03:21:58 PM UTC 24
Finished Sep 04 03:33:52 PM UTC 24
Peak memory 279456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352649619 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shado
w_reg_errors_with_csr_rw.2352649619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_errors.1718559662
Short name T716
Test name
Test status
Simulation time 106227215 ps
CPU time 12.07 seconds
Started Sep 04 03:22:06 PM UTC 24
Finished Sep 04 03:22:20 PM UTC 24
Peak memory 266988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718559662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1718559662
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.3077877159
Short name T805
Test name
Test status
Simulation time 8344191 ps
CPU time 2.38 seconds
Started Sep 04 03:29:49 PM UTC 24
Finished Sep 04 03:29:53 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077877159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3077877159
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/30.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.2461089461
Short name T806
Test name
Test status
Simulation time 14657825 ps
CPU time 1.96 seconds
Started Sep 04 03:29:51 PM UTC 24
Finished Sep 04 03:29:54 PM UTC 24
Peak memory 248848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461089461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2461089461
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/31.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.2572918950
Short name T808
Test name
Test status
Simulation time 7717234 ps
CPU time 2.32 seconds
Started Sep 04 03:29:52 PM UTC 24
Finished Sep 04 03:29:56 PM UTC 24
Peak memory 248292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572918950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2572918950
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/32.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.3507137529
Short name T807
Test name
Test status
Simulation time 6269868 ps
CPU time 2.24 seconds
Started Sep 04 03:29:52 PM UTC 24
Finished Sep 04 03:29:56 PM UTC 24
Peak memory 248424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507137529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3507137529
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/33.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.2129752967
Short name T809
Test name
Test status
Simulation time 12183268 ps
CPU time 2.41 seconds
Started Sep 04 03:29:54 PM UTC 24
Finished Sep 04 03:29:57 PM UTC 24
Peak memory 250340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129752967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2129752967
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/34.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.413836381
Short name T811
Test name
Test status
Simulation time 8556600 ps
CPU time 2.36 seconds
Started Sep 04 03:29:55 PM UTC 24
Finished Sep 04 03:29:59 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413836381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.413836381
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/35.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.2986397091
Short name T812
Test name
Test status
Simulation time 38201651 ps
CPU time 2.94 seconds
Started Sep 04 03:29:55 PM UTC 24
Finished Sep 04 03:29:59 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986397091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2986397091
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/36.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.338443667
Short name T810
Test name
Test status
Simulation time 10303590 ps
CPU time 2.13 seconds
Started Sep 04 03:29:56 PM UTC 24
Finished Sep 04 03:29:59 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338443667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.338443667
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/37.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.1846383208
Short name T814
Test name
Test status
Simulation time 8692998 ps
CPU time 2.17 seconds
Started Sep 04 03:29:57 PM UTC 24
Finished Sep 04 03:30:00 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846383208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1846383208
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/38.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.4085595662
Short name T813
Test name
Test status
Simulation time 10346214 ps
CPU time 1.97 seconds
Started Sep 04 03:29:57 PM UTC 24
Finished Sep 04 03:30:00 PM UTC 24
Peak memory 248848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085595662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.4085595662
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/39.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3168526907
Short name T791
Test name
Test status
Simulation time 4868310916 ps
CPU time 356.81 seconds
Started Sep 04 03:23:35 PM UTC 24
Finished Sep 04 03:29:37 PM UTC 24
Peak memory 252508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168526907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3168526907
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2062384663
Short name T761
Test name
Test status
Simulation time 1669945992 ps
CPU time 251.95 seconds
Started Sep 04 03:23:32 PM UTC 24
Finished Sep 04 03:27:48 PM UTC 24
Peak memory 252376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062384663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2062384663
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1138339989
Short name T718
Test name
Test status
Simulation time 37874370 ps
CPU time 10.01 seconds
Started Sep 04 03:23:21 PM UTC 24
Finished Sep 04 03:23:33 PM UTC 24
Peak memory 262756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138339989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/a
lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1138339989
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1045054088
Short name T720
Test name
Test status
Simulation time 56072036 ps
CPU time 14.02 seconds
Started Sep 04 03:23:35 PM UTC 24
Finished Sep 04 03:23:50 PM UTC 24
Peak memory 266840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045054088 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_
rw_with_rand_reset.1045054088
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_rw.2429704902
Short name T719
Test name
Test status
Simulation time 53271835 ps
CPU time 7.15 seconds
Started Sep 04 03:23:29 PM UTC 24
Finished Sep 04 03:23:38 PM UTC 24
Peak memory 250332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429704902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2429704902
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_intr_test.3133777851
Short name T390
Test name
Test status
Simulation time 8162131 ps
CPU time 2.31 seconds
Started Sep 04 03:23:17 PM UTC 24
Finished Sep 04 03:23:21 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133777851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3133777851
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.146951512
Short name T236
Test name
Test status
Simulation time 2382480295 ps
CPU time 40.93 seconds
Started Sep 04 03:23:35 PM UTC 24
Finished Sep 04 03:24:17 PM UTC 24
Peak memory 260836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146951512 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.146951512
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.832435663
Short name T162
Test name
Test status
Simulation time 5820882004 ps
CPU time 188.69 seconds
Started Sep 04 03:22:50 PM UTC 24
Finished Sep 04 03:26:01 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832435663 -assert nopostproc +UVM_TESTNAME=alert_handler_b
ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.832435663
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_errors.2432752114
Short name T268
Test name
Test status
Simulation time 1330962667 ps
CPU time 31.05 seconds
Started Sep 04 03:23:00 PM UTC 24
Finished Sep 04 03:23:32 PM UTC 24
Peak memory 269036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432752114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2432752114
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.2553217494
Short name T815
Test name
Test status
Simulation time 19080402 ps
CPU time 2.3 seconds
Started Sep 04 03:29:58 PM UTC 24
Finished Sep 04 03:30:01 PM UTC 24
Peak memory 250476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553217494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2553217494
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/40.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.620365273
Short name T819
Test name
Test status
Simulation time 19566547 ps
CPU time 2.21 seconds
Started Sep 04 03:30:01 PM UTC 24
Finished Sep 04 03:30:04 PM UTC 24
Peak memory 250472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620365273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.620365273
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/41.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.999759940
Short name T818
Test name
Test status
Simulation time 7803841 ps
CPU time 2.15 seconds
Started Sep 04 03:30:01 PM UTC 24
Finished Sep 04 03:30:04 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999759940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.999759940
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/42.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.1922149914
Short name T816
Test name
Test status
Simulation time 11040965 ps
CPU time 1.64 seconds
Started Sep 04 03:30:01 PM UTC 24
Finished Sep 04 03:30:04 PM UTC 24
Peak memory 248780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922149914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1922149914
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/43.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.3053347486
Short name T817
Test name
Test status
Simulation time 7347086 ps
CPU time 1.95 seconds
Started Sep 04 03:30:01 PM UTC 24
Finished Sep 04 03:30:04 PM UTC 24
Peak memory 248848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053347486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3053347486
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/44.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.3883885943
Short name T820
Test name
Test status
Simulation time 10243932 ps
CPU time 2.03 seconds
Started Sep 04 03:30:01 PM UTC 24
Finished Sep 04 03:30:04 PM UTC 24
Peak memory 250340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883885943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3883885943
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/45.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.1924038926
Short name T821
Test name
Test status
Simulation time 9588563 ps
CPU time 2.2 seconds
Started Sep 04 03:30:03 PM UTC 24
Finished Sep 04 03:30:06 PM UTC 24
Peak memory 248288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924038926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1924038926
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/46.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.446610254
Short name T823
Test name
Test status
Simulation time 13088582 ps
CPU time 2.6 seconds
Started Sep 04 03:30:05 PM UTC 24
Finished Sep 04 03:30:09 PM UTC 24
Peak memory 250408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446610254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.446610254
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/47.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.3738144354
Short name T822
Test name
Test status
Simulation time 18086026 ps
CPU time 1.95 seconds
Started Sep 04 03:30:05 PM UTC 24
Finished Sep 04 03:30:08 PM UTC 24
Peak memory 248848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738144354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3738144354
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/48.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.3584739864
Short name T824
Test name
Test status
Simulation time 10403473 ps
CPU time 2.56 seconds
Started Sep 04 03:30:05 PM UTC 24
Finished Sep 04 03:30:09 PM UTC 24
Peak memory 250344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584739864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3584739864
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/49.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.857744065
Short name T269
Test name
Test status
Simulation time 87108898 ps
CPU time 10.04 seconds
Started Sep 04 03:24:18 PM UTC 24
Finished Sep 04 03:24:29 PM UTC 24
Peak memory 252708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857744065 -assert no
postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_mem_r
w_with_rand_reset.857744065
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_rw.150038711
Short name T398
Test name
Test status
Simulation time 37968805 ps
CPU time 9.69 seconds
Started Sep 04 03:24:15 PM UTC 24
Finished Sep 04 03:24:26 PM UTC 24
Peak memory 250464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150038711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_ha
ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.150038711
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_intr_test.2306646500
Short name T389
Test name
Test status
Simulation time 15077817 ps
CPU time 2.67 seconds
Started Sep 04 03:24:12 PM UTC 24
Finished Sep 04 03:24:15 PM UTC 24
Peak memory 250340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306646500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2306646500
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3131877266
Short name T727
Test name
Test status
Simulation time 700059899 ps
CPU time 70.07 seconds
Started Sep 04 03:24:16 PM UTC 24
Finished Sep 04 03:25:28 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131877266 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outstanding.3131877266
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_errors.791025780
Short name T721
Test name
Test status
Simulation time 235819712 ps
CPU time 23.98 seconds
Started Sep 04 03:23:51 PM UTC 24
Finished Sep 04 03:24:17 PM UTC 24
Peak memory 266924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791025780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.791025780
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1493766412
Short name T239
Test name
Test status
Simulation time 210148056 ps
CPU time 6.8 seconds
Started Sep 04 03:24:06 PM UTC 24
Finished Sep 04 03:24:14 PM UTC 24
Peak memory 250400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=
UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493766412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t
est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1493766412
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3036562933
Short name T725
Test name
Test status
Simulation time 129862410 ps
CPU time 14.33 seconds
Started Sep 04 03:24:50 PM UTC 24
Finished Sep 04 03:25:06 PM UTC 24
Peak memory 268888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036562933 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_mem_
rw_with_rand_reset.3036562933
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_rw.1781651046
Short name T270
Test name
Test status
Simulation time 470298141 ps
CPU time 12.91 seconds
Started Sep 04 03:24:45 PM UTC 24
Finished Sep 04 03:24:59 PM UTC 24
Peak memory 252376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781651046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1781651046
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_intr_test.4231797215
Short name T387
Test name
Test status
Simulation time 26499810 ps
CPU time 2.22 seconds
Started Sep 04 03:24:44 PM UTC 24
Finished Sep 04 03:24:47 PM UTC 24
Peak memory 250336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231797215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.4231797215
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1621348924
Short name T732
Test name
Test status
Simulation time 742013961 ps
CPU time 54.23 seconds
Started Sep 04 03:24:48 PM UTC 24
Finished Sep 04 03:25:44 PM UTC 24
Peak memory 260632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621348924 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outstanding.1621348924
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4242818943
Short name T170
Test name
Test status
Simulation time 19916419586 ps
CPU time 401.94 seconds
Started Sep 04 03:24:26 PM UTC 24
Finished Sep 04 03:31:14 PM UTC 24
Peak memory 285740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242818943 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.4242818943
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_errors.492327350
Short name T723
Test name
Test status
Simulation time 320408840 ps
CPU time 12.37 seconds
Started Sep 04 03:24:30 PM UTC 24
Finished Sep 04 03:24:44 PM UTC 24
Peak memory 266924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492327350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.492327350
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2010071149
Short name T730
Test name
Test status
Simulation time 492064828 ps
CPU time 10.7 seconds
Started Sep 04 03:25:23 PM UTC 24
Finished Sep 04 03:25:35 PM UTC 24
Peak memory 252504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010071149 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_mem_
rw_with_rand_reset.2010071149
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_rw.2164663834
Short name T728
Test name
Test status
Simulation time 245547614 ps
CPU time 6.62 seconds
Started Sep 04 03:25:22 PM UTC 24
Finished Sep 04 03:25:30 PM UTC 24
Peak memory 250328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164663834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2164663834
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_intr_test.666462328
Short name T388
Test name
Test status
Simulation time 17920256 ps
CPU time 2.48 seconds
Started Sep 04 03:25:19 PM UTC 24
Finished Sep 04 03:25:23 PM UTC 24
Peak memory 250340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666462328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.666462328
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3841695799
Short name T741
Test name
Test status
Simulation time 630516715 ps
CPU time 51.73 seconds
Started Sep 04 03:25:23 PM UTC 24
Finished Sep 04 03:26:17 PM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841695799 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outstanding.3841695799
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_errors.2841956510
Short name T729
Test name
Test status
Simulation time 1099905259 ps
CPU time 20.92 seconds
Started Sep 04 03:25:11 PM UTC 24
Finished Sep 04 03:25:33 PM UTC 24
Peak memory 268896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841956510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2841956510
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3292219558
Short name T734
Test name
Test status
Simulation time 240854855 ps
CPU time 14.03 seconds
Started Sep 04 03:25:38 PM UTC 24
Finished Sep 04 03:25:53 PM UTC 24
Peak memory 264864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292219558 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_mem_
rw_with_rand_reset.3292219558
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_rw.3554761704
Short name T733
Test name
Test status
Simulation time 74110686 ps
CPU time 9.14 seconds
Started Sep 04 03:25:34 PM UTC 24
Finished Sep 04 03:25:44 PM UTC 24
Peak memory 252372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554761704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3554761704
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_intr_test.2555902647
Short name T731
Test name
Test status
Simulation time 10505767 ps
CPU time 1.98 seconds
Started Sep 04 03:25:34 PM UTC 24
Finished Sep 04 03:25:37 PM UTC 24
Peak memory 248848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555902647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2555902647
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.427823929
Short name T739
Test name
Test status
Simulation time 1143582541 ps
CPU time 31.17 seconds
Started Sep 04 03:25:36 PM UTC 24
Finished Sep 04 03:26:09 PM UTC 24
Peak memory 260704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427823929 -assert nopostproc +UVM_TESTNAME=alert_handle
r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outstanding.427823929
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.4218486633
Short name T164
Test name
Test status
Simulation time 4364164436 ps
CPU time 241.48 seconds
Started Sep 04 03:25:29 PM UTC 24
Finished Sep 04 03:29:35 PM UTC 24
Peak memory 279532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218486633 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.4218486633
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1186389349
Short name T188
Test name
Test status
Simulation time 24763653163 ps
CPU time 448.44 seconds
Started Sep 04 03:25:26 PM UTC 24
Finished Sep 04 03:33:00 PM UTC 24
Peak memory 279452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186389349 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shado
w_reg_errors_with_csr_rw.1186389349
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_errors.989716581
Short name T737
Test name
Test status
Simulation time 1314595129 ps
CPU time 33.76 seconds
Started Sep 04 03:25:31 PM UTC 24
Finished Sep 04 03:26:07 PM UTC 24
Peak memory 262828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989716581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.989716581
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1442296609
Short name T744
Test name
Test status
Simulation time 62558676 ps
CPU time 12.95 seconds
Started Sep 04 03:26:05 PM UTC 24
Finished Sep 04 03:26:20 PM UTC 24
Peak memory 264928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442296609 -assert n
opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_mem_
rw_with_rand_reset.1442296609
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_rw.1200629706
Short name T736
Test name
Test status
Simulation time 217152245 ps
CPU time 6.56 seconds
Started Sep 04 03:25:58 PM UTC 24
Finished Sep 04 03:26:06 PM UTC 24
Peak memory 250324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200629706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1200629706
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_intr_test.4219001945
Short name T735
Test name
Test status
Simulation time 16514134 ps
CPU time 1.99 seconds
Started Sep 04 03:25:54 PM UTC 24
Finished Sep 04 03:25:57 PM UTC 24
Peak memory 248848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219001945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.4219001945
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1286818054
Short name T740
Test name
Test status
Simulation time 337833143 ps
CPU time 13.18 seconds
Started Sep 04 03:26:02 PM UTC 24
Finished Sep 04 03:26:17 PM UTC 24
Peak memory 260832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286818054 -assert nopostproc +UVM_TESTNAME=alert_handl
er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outstanding.1286818054
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3805326009
Short name T167
Test name
Test status
Simulation time 1064860068 ps
CPU time 134.15 seconds
Started Sep 04 03:25:48 PM UTC 24
Finished Sep 04 03:28:05 PM UTC 24
Peak memory 269228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805326009 -assert nopostproc +UVM_TESTNAME=alert_handler_
base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.3805326009
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1580328611
Short name T184
Test name
Test status
Simulation time 13463284477 ps
CPU time 632.4 seconds
Started Sep 04 03:25:48 PM UTC 24
Finished Sep 04 03:36:29 PM UTC 24
Peak memory 281640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs
r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580328611 -asser
t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shado
w_reg_errors_with_csr_rw.1580328611
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_errors.3174574415
Short name T738
Test name
Test status
Simulation time 163273269 ps
CPU time 18.01 seconds
Started Sep 04 03:25:48 PM UTC 24
Finished Sep 04 03:26:07 PM UTC 24
Peak memory 262892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174574415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_hand
ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3174574415
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy.4275792049
Short name T56
Test name
Test status
Simulation time 15693771927 ps
CPU time 1565.86 seconds
Started Sep 04 01:39:10 PM UTC 24
Finished Sep 04 02:05:34 PM UTC 24
Peak memory 302276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275792049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.4275792049
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy_stress.321910472
Short name T5
Test name
Test status
Simulation time 960396375 ps
CPU time 33.56 seconds
Started Sep 04 01:39:11 PM UTC 24
Finished Sep 04 01:39:46 PM UTC 24
Peak memory 262292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321910472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.321910472
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_alert_accum.4030814075
Short name T47
Test name
Test status
Simulation time 14909964709 ps
CPU time 195.28 seconds
Started Sep 04 01:39:10 PM UTC 24
Finished Sep 04 01:42:29 PM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030814075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.4030814075
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_intr_timeout.1586664656
Short name T14
Test name
Test status
Simulation time 1150516952 ps
CPU time 35.42 seconds
Started Sep 04 01:39:10 PM UTC 24
Finished Sep 04 01:39:47 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586664656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1586664656
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg.2795941269
Short name T305
Test name
Test status
Simulation time 10951550667 ps
CPU time 968.24 seconds
Started Sep 04 01:39:11 PM UTC 24
Finished Sep 04 01:55:31 PM UTC 24
Peak memory 298116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795941269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2795941269
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg_stub_clk.3276695390
Short name T118
Test name
Test status
Simulation time 14047462096 ps
CPU time 1530.35 seconds
Started Sep 04 01:39:11 PM UTC 24
Finished Sep 04 02:05:00 PM UTC 24
Peak memory 295812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276695390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3276695390
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_alerts.1984768132
Short name T23
Test name
Test status
Simulation time 5681443451 ps
CPU time 45.76 seconds
Started Sep 04 01:39:09 PM UTC 24
Finished Sep 04 01:39:57 PM UTC 24
Peak memory 269220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984768132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1984768132
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_classes.886160086
Short name T1
Test name
Test status
Simulation time 37928813 ps
CPU time 4.87 seconds
Started Sep 04 01:39:09 PM UTC 24
Finished Sep 04 01:39:15 PM UTC 24
Peak memory 262960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886160086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.886160086
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/0.alert_handler_sig_int_fail.1900257756
Short name T10
Test name
Test status
Simulation time 1612193686 ps
CPU time 23.57 seconds
Started Sep 04 01:39:10 PM UTC 24
Finished Sep 04 01:39:35 PM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900257756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1900257756
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/0.alert_handler_smoke.343543424
Short name T3
Test name
Test status
Simulation time 577703990 ps
CPU time 17.85 seconds
Started Sep 04 01:39:09 PM UTC 24
Finished Sep 04 01:39:29 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343543424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.343543424
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all.2913500461
Short name T258
Test name
Test status
Simulation time 12223933780 ps
CPU time 1209.24 seconds
Started Sep 04 01:39:11 PM UTC 24
Finished Sep 04 01:59:35 PM UTC 24
Peak memory 297852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913500461 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all.2913500461
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/0.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy.3373941494
Short name T125
Test name
Test status
Simulation time 502293370264 ps
CPU time 3178.93 seconds
Started Sep 04 01:39:13 PM UTC 24
Finished Sep 04 02:32:45 PM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373941494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3373941494
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_alert_accum.1675557404
Short name T45
Test name
Test status
Simulation time 734523999 ps
CPU time 88.33 seconds
Started Sep 04 01:39:12 PM UTC 24
Finished Sep 04 01:40:43 PM UTC 24
Peak memory 269072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675557404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1675557404
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_intr_timeout.1274881503
Short name T12
Test name
Test status
Simulation time 298929100 ps
CPU time 28.03 seconds
Started Sep 04 01:39:11 PM UTC 24
Finished Sep 04 01:39:41 PM UTC 24
Peak memory 262844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274881503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1274881503
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/1.alert_handler_ping_timeout.2051636834
Short name T7
Test name
Test status
Simulation time 1710804267 ps
CPU time 64.79 seconds
Started Sep 04 01:39:17 PM UTC 24
Finished Sep 04 01:40:23 PM UTC 24
Peak memory 269056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051636834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2051636834
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/1.alert_handler_smoke.4254176644
Short name T24
Test name
Test status
Simulation time 1088259337 ps
CPU time 48.42 seconds
Started Sep 04 01:39:11 PM UTC 24
Finished Sep 04 01:40:01 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254176644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.4254176644
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all.1757320115
Short name T51
Test name
Test status
Simulation time 37429869584 ps
CPU time 520.33 seconds
Started Sep 04 01:39:30 PM UTC 24
Finished Sep 04 01:48:17 PM UTC 24
Peak memory 269500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757320115 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all.1757320115
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/1.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy_stress.1812190385
Short name T406
Test name
Test status
Simulation time 1868623730 ps
CPU time 17.56 seconds
Started Sep 04 01:49:13 PM UTC 24
Finished Sep 04 01:49:32 PM UTC 24
Peak memory 263240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812190385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1812190385
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_alert_accum.231874745
Short name T304
Test name
Test status
Simulation time 1740817181 ps
CPU time 147.43 seconds
Started Sep 04 01:48:50 PM UTC 24
Finished Sep 04 01:51:21 PM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231874745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.231874745
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_intr_timeout.173212767
Short name T139
Test name
Test status
Simulation time 175044405 ps
CPU time 18.47 seconds
Started Sep 04 01:48:29 PM UTC 24
Finished Sep 04 01:48:49 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173212767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.173212767
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg_stub_clk.3665508888
Short name T306
Test name
Test status
Simulation time 191765332030 ps
CPU time 1592.35 seconds
Started Sep 04 01:49:11 PM UTC 24
Finished Sep 04 02:16:02 PM UTC 24
Peak memory 301884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665508888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3665508888
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_alerts.2928610265
Short name T297
Test name
Test status
Simulation time 254607909 ps
CPU time 36.58 seconds
Started Sep 04 01:48:26 PM UTC 24
Finished Sep 04 01:49:04 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928610265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2928610265
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_classes.1444304864
Short name T83
Test name
Test status
Simulation time 444059550 ps
CPU time 42.16 seconds
Started Sep 04 01:48:26 PM UTC 24
Finished Sep 04 01:49:10 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444304864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1444304864
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/10.alert_handler_sig_int_fail.3084272336
Short name T82
Test name
Test status
Simulation time 189312122 ps
CPU time 6.9 seconds
Started Sep 04 01:48:55 PM UTC 24
Finished Sep 04 01:49:03 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084272336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3084272336
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/10.alert_handler_smoke.2697660674
Short name T404
Test name
Test status
Simulation time 14831922761 ps
CPU time 42.88 seconds
Started Sep 04 01:48:20 PM UTC 24
Finished Sep 04 01:49:04 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697660674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2697660674
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all.3795992442
Short name T533
Test name
Test status
Simulation time 97064678447 ps
CPU time 3274.67 seconds
Started Sep 04 01:49:18 PM UTC 24
Finished Sep 04 02:44:30 PM UTC 24
Peak memory 320984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795992442 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all.3795992442
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/10.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy.2156573054
Short name T255
Test name
Test status
Simulation time 14136622241 ps
CPU time 784.84 seconds
Started Sep 04 01:50:19 PM UTC 24
Finished Sep 04 02:03:33 PM UTC 24
Peak memory 279356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156573054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2156573054
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy_stress.1523976206
Short name T409
Test name
Test status
Simulation time 129191224 ps
CPU time 12.96 seconds
Started Sep 04 01:50:40 PM UTC 24
Finished Sep 04 01:50:54 PM UTC 24
Peak memory 262984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523976206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1523976206
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_alert_accum.3765831560
Short name T411
Test name
Test status
Simulation time 1241026628 ps
CPU time 143.85 seconds
Started Sep 04 01:50:10 PM UTC 24
Finished Sep 04 01:52:36 PM UTC 24
Peak memory 269040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765831560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3765831560
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_intr_timeout.2906142482
Short name T407
Test name
Test status
Simulation time 1244163939 ps
CPU time 17.54 seconds
Started Sep 04 01:49:57 PM UTC 24
Finished Sep 04 01:50:16 PM UTC 24
Peak memory 267020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906142482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2906142482
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg.1344372158
Short name T361
Test name
Test status
Simulation time 189665219903 ps
CPU time 2463.38 seconds
Started Sep 04 01:50:31 PM UTC 24
Finished Sep 04 02:32:01 PM UTC 24
Peak memory 297860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344372158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1344372158
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg_stub_clk.2998050614
Short name T376
Test name
Test status
Simulation time 59492349694 ps
CPU time 1253.18 seconds
Started Sep 04 01:50:39 PM UTC 24
Finished Sep 04 02:11:48 PM UTC 24
Peak memory 279360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998050614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2998050614
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_alerts.4247955074
Short name T408
Test name
Test status
Simulation time 509615283 ps
CPU time 32.26 seconds
Started Sep 04 01:49:44 PM UTC 24
Finished Sep 04 01:50:18 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247955074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.4247955074
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_classes.2533456029
Short name T303
Test name
Test status
Simulation time 1040245732 ps
CPU time 41.45 seconds
Started Sep 04 01:49:56 PM UTC 24
Finished Sep 04 01:50:39 PM UTC 24
Peak memory 263260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533456029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2533456029
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/11.alert_handler_sig_int_fail.305343316
Short name T254
Test name
Test status
Simulation time 103405255 ps
CPU time 20.09 seconds
Started Sep 04 01:50:17 PM UTC 24
Finished Sep 04 01:50:38 PM UTC 24
Peak memory 269472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305343316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.305343316
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/11.alert_handler_smoke.3223677773
Short name T326
Test name
Test status
Simulation time 3457655637 ps
CPU time 66.03 seconds
Started Sep 04 01:49:33 PM UTC 24
Finished Sep 04 01:50:41 PM UTC 24
Peak memory 263296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223677773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3223677773
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all.1704602428
Short name T94
Test name
Test status
Simulation time 2081756410 ps
CPU time 49.39 seconds
Started Sep 04 01:50:41 PM UTC 24
Finished Sep 04 01:51:32 PM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704602428 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all.1704602428
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all_with_rand_reset.1891491991
Short name T54
Test name
Test status
Simulation time 5486977016 ps
CPU time 440.51 seconds
Started Sep 04 01:51:03 PM UTC 24
Finished Sep 04 01:58:29 PM UTC 24
Peak memory 281596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1891491991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.a
lert_handler_stress_all_with_rand_reset.1891491991
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/12.alert_handler_alert_accum_saturation.578983010
Short name T246
Test name
Test status
Simulation time 112685970 ps
CPU time 5.02 seconds
Started Sep 04 01:53:23 PM UTC 24
Finished Sep 04 01:53:29 PM UTC 24
Peak memory 263528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578983010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.578983010
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy.2822320795
Short name T70
Test name
Test status
Simulation time 99258229195 ps
CPU time 1189.45 seconds
Started Sep 04 01:52:31 PM UTC 24
Finished Sep 04 02:12:36 PM UTC 24
Peak memory 285696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822320795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2822320795
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy_stress.3484393786
Short name T414
Test name
Test status
Simulation time 383302356 ps
CPU time 27.64 seconds
Started Sep 04 01:52:54 PM UTC 24
Finished Sep 04 01:53:23 PM UTC 24
Peak memory 263304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484393786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3484393786
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_alert_accum.2314784744
Short name T413
Test name
Test status
Simulation time 911357679 ps
CPU time 53.37 seconds
Started Sep 04 01:51:58 PM UTC 24
Finished Sep 04 01:52:53 PM UTC 24
Peak memory 269368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314784744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2314784744
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_intr_timeout.162804037
Short name T92
Test name
Test status
Simulation time 559400935 ps
CPU time 40.79 seconds
Started Sep 04 01:51:48 PM UTC 24
Finished Sep 04 01:52:31 PM UTC 24
Peak memory 263264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162804037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.162804037
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg.519679383
Short name T355
Test name
Test status
Simulation time 214731952761 ps
CPU time 1527.8 seconds
Started Sep 04 01:52:42 PM UTC 24
Finished Sep 04 02:18:26 PM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519679383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.519679383
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg_stub_clk.1500974773
Short name T311
Test name
Test status
Simulation time 60683672093 ps
CPU time 721.33 seconds
Started Sep 04 01:52:43 PM UTC 24
Finished Sep 04 02:04:53 PM UTC 24
Peak memory 285896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500974773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1500974773
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_alerts.3697456640
Short name T52
Test name
Test status
Simulation time 546736442 ps
CPU time 32.04 seconds
Started Sep 04 01:51:23 PM UTC 24
Finished Sep 04 01:51:57 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697456640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3697456640
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_classes.1791546729
Short name T412
Test name
Test status
Simulation time 787730200 ps
CPU time 65.98 seconds
Started Sep 04 01:51:33 PM UTC 24
Finished Sep 04 01:52:41 PM UTC 24
Peak memory 263260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791546729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1791546729
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/12.alert_handler_sig_int_fail.4093011931
Short name T154
Test name
Test status
Simulation time 3762073641 ps
CPU time 51.78 seconds
Started Sep 04 01:52:28 PM UTC 24
Finished Sep 04 01:53:22 PM UTC 24
Peak memory 269500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093011931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.4093011931
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/12.alert_handler_smoke.853456335
Short name T410
Test name
Test status
Simulation time 283260446 ps
CPU time 24.52 seconds
Started Sep 04 01:51:22 PM UTC 24
Finished Sep 04 01:51:48 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853456335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.853456335
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all.3330980235
Short name T415
Test name
Test status
Simulation time 310269501 ps
CPU time 21.29 seconds
Started Sep 04 01:53:04 PM UTC 24
Finished Sep 04 01:53:27 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330980235 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all.3330980235
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/12.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/13.alert_handler_alert_accum_saturation.2536539762
Short name T247
Test name
Test status
Simulation time 270659384 ps
CPU time 4.89 seconds
Started Sep 04 01:56:20 PM UTC 24
Finished Sep 04 01:56:27 PM UTC 24
Peak memory 263248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536539762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2536539762
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy.2502651535
Short name T512
Test name
Test status
Simulation time 42936022106 ps
CPU time 2593.02 seconds
Started Sep 04 01:54:24 PM UTC 24
Finished Sep 04 02:38:06 PM UTC 24
Peak memory 304676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502651535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2502651535
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy_stress.891270203
Short name T417
Test name
Test status
Simulation time 3683448319 ps
CPU time 64.21 seconds
Started Sep 04 01:55:33 PM UTC 24
Finished Sep 04 01:56:39 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891270203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.891270203
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_alert_accum.4268879917
Short name T416
Test name
Test status
Simulation time 5397739461 ps
CPU time 121.82 seconds
Started Sep 04 01:53:58 PM UTC 24
Finished Sep 04 01:56:02 PM UTC 24
Peak memory 269496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268879917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.4268879917
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_intr_timeout.1674177038
Short name T96
Test name
Test status
Simulation time 1143129484 ps
CPU time 36.83 seconds
Started Sep 04 01:53:57 PM UTC 24
Finished Sep 04 01:54:35 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674177038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1674177038
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg.532597484
Short name T333
Test name
Test status
Simulation time 82930529551 ps
CPU time 1485.3 seconds
Started Sep 04 01:54:43 PM UTC 24
Finished Sep 04 02:19:46 PM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532597484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.532597484
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg_stub_clk.1480816590
Short name T502
Test name
Test status
Simulation time 35437916141 ps
CPU time 2432.33 seconds
Started Sep 04 01:55:03 PM UTC 24
Finished Sep 04 02:36:03 PM UTC 24
Peak memory 288620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480816590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1480816590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/13.alert_handler_ping_timeout.1792507457
Short name T327
Test name
Test status
Simulation time 3065801000 ps
CPU time 182.91 seconds
Started Sep 04 01:54:36 PM UTC 24
Finished Sep 04 01:57:43 PM UTC 24
Peak memory 269192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792507457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1792507457
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_alerts.787160222
Short name T317
Test name
Test status
Simulation time 1872836648 ps
CPU time 51.18 seconds
Started Sep 04 01:53:30 PM UTC 24
Finished Sep 04 01:54:24 PM UTC 24
Peak memory 263012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787160222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.787160222
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_classes.4240635708
Short name T310
Test name
Test status
Simulation time 610511718 ps
CPU time 40.54 seconds
Started Sep 04 01:53:35 PM UTC 24
Finished Sep 04 01:54:17 PM UTC 24
Peak memory 269076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240635708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.4240635708
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/13.alert_handler_sig_int_fail.1731709576
Short name T257
Test name
Test status
Simulation time 3560210144 ps
CPU time 43.66 seconds
Started Sep 04 01:54:17 PM UTC 24
Finished Sep 04 01:55:02 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731709576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1731709576
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/13.alert_handler_smoke.1051943693
Short name T95
Test name
Test status
Simulation time 2394323198 ps
CPU time 27.73 seconds
Started Sep 04 01:53:27 PM UTC 24
Finished Sep 04 01:53:57 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051943693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1051943693
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all.4128338383
Short name T464
Test name
Test status
Simulation time 16549150882 ps
CPU time 1762.8 seconds
Started Sep 04 01:56:03 PM UTC 24
Finished Sep 04 02:25:48 PM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128338383 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all.4128338383
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/13.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/14.alert_handler_alert_accum_saturation.193760409
Short name T248
Test name
Test status
Simulation time 26296531 ps
CPU time 3.82 seconds
Started Sep 04 01:58:38 PM UTC 24
Finished Sep 04 01:58:43 PM UTC 24
Peak memory 263504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193760409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.193760409
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy.1121688045
Short name T531
Test name
Test status
Simulation time 47283122898 ps
CPU time 2615.94 seconds
Started Sep 04 01:57:23 PM UTC 24
Finished Sep 04 02:41:28 PM UTC 24
Peak memory 298460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121688045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1121688045
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy_stress.1596419327
Short name T420
Test name
Test status
Simulation time 1880461071 ps
CPU time 33.61 seconds
Started Sep 04 01:58:02 PM UTC 24
Finished Sep 04 01:58:37 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596419327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1596419327
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_alert_accum.293130168
Short name T425
Test name
Test status
Simulation time 3725354061 ps
CPU time 300.07 seconds
Started Sep 04 01:57:02 PM UTC 24
Finished Sep 04 02:02:06 PM UTC 24
Peak memory 269276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293130168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.293130168
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_intr_timeout.1257761194
Short name T418
Test name
Test status
Simulation time 103405364 ps
CPU time 12.08 seconds
Started Sep 04 01:56:49 PM UTC 24
Finished Sep 04 01:57:02 PM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257761194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1257761194
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg_stub_clk.16769660
Short name T575
Test name
Test status
Simulation time 60708725311 ps
CPU time 3319.62 seconds
Started Sep 04 01:57:43 PM UTC 24
Finished Sep 04 02:53:40 PM UTC 24
Peak memory 304680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16769660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.16769660
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/14.alert_handler_ping_timeout.1674664910
Short name T29
Test name
Test status
Simulation time 18869510358 ps
CPU time 408.46 seconds
Started Sep 04 01:57:36 PM UTC 24
Finished Sep 04 02:04:30 PM UTC 24
Peak memory 263304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674664910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1674664910
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_alerts.3747526046
Short name T320
Test name
Test status
Simulation time 203795122 ps
CPU time 6.84 seconds
Started Sep 04 01:56:40 PM UTC 24
Finished Sep 04 01:56:48 PM UTC 24
Peak memory 265340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747526046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3747526046
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_classes.859571412
Short name T419
Test name
Test status
Simulation time 3205794468 ps
CPU time 58.71 seconds
Started Sep 04 01:56:41 PM UTC 24
Finished Sep 04 01:57:41 PM UTC 24
Peak memory 269500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859571412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.859571412
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/14.alert_handler_sig_int_fail.2056738164
Short name T256
Test name
Test status
Simulation time 742678571 ps
CPU time 30.99 seconds
Started Sep 04 01:57:03 PM UTC 24
Finished Sep 04 01:57:35 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056738164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2056738164
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/14.alert_handler_smoke.4214239809
Short name T296
Test name
Test status
Simulation time 2620282028 ps
CPU time 27.04 seconds
Started Sep 04 01:56:33 PM UTC 24
Finished Sep 04 01:57:01 PM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214239809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.4214239809
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/14.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/15.alert_handler_alert_accum_saturation.3967801259
Short name T249
Test name
Test status
Simulation time 49796233 ps
CPU time 6.06 seconds
Started Sep 04 02:00:55 PM UTC 24
Finished Sep 04 02:01:03 PM UTC 24
Peak memory 263248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967801259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3967801259
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy.1054504222
Short name T543
Test name
Test status
Simulation time 73144600256 ps
CPU time 2777.37 seconds
Started Sep 04 01:59:37 PM UTC 24
Finished Sep 04 02:46:27 PM UTC 24
Peak memory 304600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054504222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1054504222
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy_stress.443764042
Short name T424
Test name
Test status
Simulation time 539661038 ps
CPU time 34.45 seconds
Started Sep 04 02:00:18 PM UTC 24
Finished Sep 04 02:00:54 PM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443764042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.443764042
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_alert_accum.3477444128
Short name T423
Test name
Test status
Simulation time 1372746655 ps
CPU time 43.57 seconds
Started Sep 04 01:59:32 PM UTC 24
Finished Sep 04 02:00:18 PM UTC 24
Peak memory 269304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477444128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3477444128
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_intr_timeout.3354919544
Short name T421
Test name
Test status
Simulation time 222660801 ps
CPU time 6.88 seconds
Started Sep 04 01:59:23 PM UTC 24
Finished Sep 04 01:59:31 PM UTC 24
Peak memory 262936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354919544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3354919544
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg.3712298655
Short name T365
Test name
Test status
Simulation time 19581740888 ps
CPU time 1685.07 seconds
Started Sep 04 01:59:54 PM UTC 24
Finished Sep 04 02:28:19 PM UTC 24
Peak memory 301884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712298655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3712298655
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg_stub_clk.214245878
Short name T519
Test name
Test status
Simulation time 71130405429 ps
CPU time 2313.04 seconds
Started Sep 04 02:00:01 PM UTC 24
Finished Sep 04 02:39:07 PM UTC 24
Peak memory 302216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214245878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.214245878
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/15.alert_handler_ping_timeout.1916081709
Short name T344
Test name
Test status
Simulation time 10839410296 ps
CPU time 400.21 seconds
Started Sep 04 01:59:43 PM UTC 24
Finished Sep 04 02:06:29 PM UTC 24
Peak memory 269192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916081709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1916081709
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_alerts.1991055979
Short name T142
Test name
Test status
Simulation time 923979569 ps
CPU time 65.05 seconds
Started Sep 04 01:58:53 PM UTC 24
Finished Sep 04 02:00:00 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991055979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1991055979
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_classes.626748459
Short name T307
Test name
Test status
Simulation time 4538395948 ps
CPU time 106.41 seconds
Started Sep 04 01:59:19 PM UTC 24
Finished Sep 04 02:01:07 PM UTC 24
Peak memory 263292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626748459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.626748459
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/15.alert_handler_sig_int_fail.3950856412
Short name T97
Test name
Test status
Simulation time 346027289 ps
CPU time 15.75 seconds
Started Sep 04 01:59:37 PM UTC 24
Finished Sep 04 01:59:54 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950856412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3950856412
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/15.alert_handler_smoke.2118466622
Short name T422
Test name
Test status
Simulation time 449147685 ps
CPU time 46.88 seconds
Started Sep 04 01:58:53 PM UTC 24
Finished Sep 04 01:59:42 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118466622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2118466622
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/15.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/16.alert_handler_alert_accum_saturation.1299473964
Short name T250
Test name
Test status
Simulation time 154482912 ps
CPU time 4.44 seconds
Started Sep 04 02:04:00 PM UTC 24
Finished Sep 04 02:04:06 PM UTC 24
Peak memory 263172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299473964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1299473964
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy.732118658
Short name T144
Test name
Test status
Simulation time 149032365454 ps
CPU time 1995.38 seconds
Started Sep 04 02:02:33 PM UTC 24
Finished Sep 04 02:36:10 PM UTC 24
Peak memory 301880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732118658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.732118658
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy_stress.3381545807
Short name T428
Test name
Test status
Simulation time 718966894 ps
CPU time 45.62 seconds
Started Sep 04 02:03:35 PM UTC 24
Finished Sep 04 02:04:22 PM UTC 24
Peak memory 262920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381545807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3381545807
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_alert_accum.2489175467
Short name T429
Test name
Test status
Simulation time 1377469480 ps
CPU time 140.2 seconds
Started Sep 04 02:02:14 PM UTC 24
Finished Sep 04 02:04:37 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489175467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2489175467
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_intr_timeout.3809051502
Short name T99
Test name
Test status
Simulation time 2155765549 ps
CPU time 45.06 seconds
Started Sep 04 02:02:07 PM UTC 24
Finished Sep 04 02:02:54 PM UTC 24
Peak memory 263072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809051502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3809051502
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg_stub_clk.3160056218
Short name T321
Test name
Test status
Simulation time 31527181929 ps
CPU time 834.9 seconds
Started Sep 04 02:03:03 PM UTC 24
Finished Sep 04 02:17:08 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160056218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3160056218
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/16.alert_handler_ping_timeout.101536506
Short name T347
Test name
Test status
Simulation time 6431318070 ps
CPU time 278.84 seconds
Started Sep 04 02:02:44 PM UTC 24
Finished Sep 04 02:07:27 PM UTC 24
Peak memory 263304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101536506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.101536506
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_alerts.1914102163
Short name T426
Test name
Test status
Simulation time 1091874752 ps
CPU time 51.6 seconds
Started Sep 04 02:01:20 PM UTC 24
Finished Sep 04 02:02:13 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914102163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1914102163
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_classes.270755401
Short name T300
Test name
Test status
Simulation time 648361529 ps
CPU time 56.04 seconds
Started Sep 04 02:02:05 PM UTC 24
Finished Sep 04 02:03:03 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270755401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.270755401
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/16.alert_handler_smoke.778887490
Short name T427
Test name
Test status
Simulation time 1119220141 ps
CPU time 81.11 seconds
Started Sep 04 02:01:08 PM UTC 24
Finished Sep 04 02:02:31 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778887490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.778887490
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all.1285294510
Short name T567
Test name
Test status
Simulation time 195944163525 ps
CPU time 2783.16 seconds
Started Sep 04 02:03:59 PM UTC 24
Finished Sep 04 02:50:52 PM UTC 24
Peak memory 314976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285294510 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all.1285294510
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all_with_rand_reset.2424960776
Short name T217
Test name
Test status
Simulation time 2447920354 ps
CPU time 321.37 seconds
Started Sep 04 02:04:06 PM UTC 24
Finished Sep 04 02:09:32 PM UTC 24
Peak memory 281524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2424960776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.a
lert_handler_stress_all_with_rand_reset.2424960776
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/17.alert_handler_alert_accum_saturation.2617131328
Short name T251
Test name
Test status
Simulation time 26879968 ps
CPU time 3.8 seconds
Started Sep 04 02:05:37 PM UTC 24
Finished Sep 04 02:05:43 PM UTC 24
Peak memory 263504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617131328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2617131328
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy_stress.4242606867
Short name T434
Test name
Test status
Simulation time 172215326 ps
CPU time 15.4 seconds
Started Sep 04 02:05:18 PM UTC 24
Finished Sep 04 02:05:35 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242606867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.4242606867
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_alert_accum.3544382120
Short name T432
Test name
Test status
Simulation time 445038882 ps
CPU time 18.06 seconds
Started Sep 04 02:04:55 PM UTC 24
Finished Sep 04 02:05:14 PM UTC 24
Peak memory 269036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544382120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3544382120
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_intr_timeout.2442474231
Short name T100
Test name
Test status
Simulation time 2160687540 ps
CPU time 37.87 seconds
Started Sep 04 02:04:46 PM UTC 24
Finished Sep 04 02:05:25 PM UTC 24
Peak memory 263000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442474231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2442474231
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg.3071802643
Short name T364
Test name
Test status
Simulation time 135319107631 ps
CPU time 2315.61 seconds
Started Sep 04 02:05:13 PM UTC 24
Finished Sep 04 02:44:15 PM UTC 24
Peak memory 301884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071802643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3071802643
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg_stub_clk.911075451
Short name T460
Test name
Test status
Simulation time 8619059412 ps
CPU time 990.03 seconds
Started Sep 04 02:05:15 PM UTC 24
Finished Sep 04 02:21:58 PM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911075451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.911075451
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/17.alert_handler_ping_timeout.1436596788
Short name T351
Test name
Test status
Simulation time 6762057842 ps
CPU time 243.56 seconds
Started Sep 04 02:05:10 PM UTC 24
Finished Sep 04 02:09:17 PM UTC 24
Peak memory 269448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436596788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1436596788
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_alerts.4290120020
Short name T433
Test name
Test status
Simulation time 377958459 ps
CPU time 45.84 seconds
Started Sep 04 02:04:30 PM UTC 24
Finished Sep 04 02:05:18 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290120020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.4290120020
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_classes.990296878
Short name T431
Test name
Test status
Simulation time 904533786 ps
CPU time 28.81 seconds
Started Sep 04 02:04:39 PM UTC 24
Finished Sep 04 02:05:09 PM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990296878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.990296878
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/17.alert_handler_sig_int_fail.2574163670
Short name T316
Test name
Test status
Simulation time 432943964 ps
CPU time 36.54 seconds
Started Sep 04 02:05:02 PM UTC 24
Finished Sep 04 02:05:40 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574163670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2574163670
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/17.alert_handler_smoke.1668404413
Short name T430
Test name
Test status
Simulation time 203198074 ps
CPU time 20.55 seconds
Started Sep 04 02:04:23 PM UTC 24
Finished Sep 04 02:04:45 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668404413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1668404413
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/17.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/18.alert_handler_alert_accum_saturation.2148890703
Short name T252
Test name
Test status
Simulation time 15343587 ps
CPU time 3.64 seconds
Started Sep 04 02:06:54 PM UTC 24
Finished Sep 04 02:06:59 PM UTC 24
Peak memory 263504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148890703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2148890703
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy.4068851659
Short name T468
Test name
Test status
Simulation time 23881242706 ps
CPU time 1204.19 seconds
Started Sep 04 02:06:19 PM UTC 24
Finished Sep 04 02:26:38 PM UTC 24
Peak memory 301880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068851659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.4068851659
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy_stress.2842423693
Short name T439
Test name
Test status
Simulation time 217915110 ps
CPU time 17.59 seconds
Started Sep 04 02:06:34 PM UTC 24
Finished Sep 04 02:06:53 PM UTC 24
Peak memory 263240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842423693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2842423693
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_alert_accum.4279590725
Short name T444
Test name
Test status
Simulation time 8087358412 ps
CPU time 217.31 seconds
Started Sep 04 02:06:04 PM UTC 24
Finished Sep 04 02:09:45 PM UTC 24
Peak memory 269176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279590725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.4279590725
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_intr_timeout.3541028144
Short name T101
Test name
Test status
Simulation time 508591484 ps
CPU time 38.95 seconds
Started Sep 04 02:05:53 PM UTC 24
Finished Sep 04 02:06:33 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541028144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3541028144
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg.4163819384
Short name T383
Test name
Test status
Simulation time 143526326246 ps
CPU time 2375.28 seconds
Started Sep 04 02:06:27 PM UTC 24
Finished Sep 04 02:46:29 PM UTC 24
Peak memory 301956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163819384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.4163819384
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg_stub_clk.1651232413
Short name T505
Test name
Test status
Simulation time 23278035913 ps
CPU time 1795.99 seconds
Started Sep 04 02:06:29 PM UTC 24
Finished Sep 04 02:36:46 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651232413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1651232413
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_alerts.1088504560
Short name T435
Test name
Test status
Simulation time 54030020 ps
CPU time 6.81 seconds
Started Sep 04 02:05:44 PM UTC 24
Finished Sep 04 02:05:52 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088504560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1088504560
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_classes.1686259083
Short name T437
Test name
Test status
Simulation time 446962339 ps
CPU time 38.77 seconds
Started Sep 04 02:05:46 PM UTC 24
Finished Sep 04 02:06:26 PM UTC 24
Peak memory 262932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686259083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1686259083
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/18.alert_handler_sig_int_fail.595031217
Short name T440
Test name
Test status
Simulation time 752799322 ps
CPU time 77.47 seconds
Started Sep 04 02:06:08 PM UTC 24
Finished Sep 04 02:07:28 PM UTC 24
Peak memory 269080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595031217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.595031217
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/18.alert_handler_smoke.948517289
Short name T436
Test name
Test status
Simulation time 364423322 ps
CPU time 35.09 seconds
Started Sep 04 02:05:42 PM UTC 24
Finished Sep 04 02:06:18 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948517289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.948517289
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all.2438438359
Short name T522
Test name
Test status
Simulation time 69844168796 ps
CPU time 1969.33 seconds
Started Sep 04 02:06:44 PM UTC 24
Finished Sep 04 02:39:56 PM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438438359 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all.2438438359
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/18.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/19.alert_handler_alert_accum_saturation.809753501
Short name T253
Test name
Test status
Simulation time 45381023 ps
CPU time 5.22 seconds
Started Sep 04 02:09:58 PM UTC 24
Finished Sep 04 02:10:04 PM UTC 24
Peak memory 263500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809753501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.809753501
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy.277485873
Short name T518
Test name
Test status
Simulation time 293602869907 ps
CPU time 1749.52 seconds
Started Sep 04 02:09:17 PM UTC 24
Finished Sep 04 02:38:46 PM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277485873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.277485873
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy_stress.1420358909
Short name T445
Test name
Test status
Simulation time 4276691029 ps
CPU time 70.35 seconds
Started Sep 04 02:09:55 PM UTC 24
Finished Sep 04 02:11:07 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420358909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1420358909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_alert_accum.669402320
Short name T443
Test name
Test status
Simulation time 5402239291 ps
CPU time 64.81 seconds
Started Sep 04 02:08:38 PM UTC 24
Finished Sep 04 02:09:44 PM UTC 24
Peak memory 262996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669402320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.669402320
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_intr_timeout.2998904867
Short name T102
Test name
Test status
Simulation time 1523300365 ps
CPU time 33.86 seconds
Started Sep 04 02:08:01 PM UTC 24
Finished Sep 04 02:08:37 PM UTC 24
Peak memory 269080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998904867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2998904867
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg.868270146
Short name T318
Test name
Test status
Simulation time 27189082401 ps
CPU time 1397.68 seconds
Started Sep 04 02:09:46 PM UTC 24
Finished Sep 04 02:33:19 PM UTC 24
Peak memory 285824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868270146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.868270146
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg_stub_clk.2191127509
Short name T478
Test name
Test status
Simulation time 24371382489 ps
CPU time 1082.57 seconds
Started Sep 04 02:09:46 PM UTC 24
Finished Sep 04 02:28:01 PM UTC 24
Peak memory 299840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191127509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2191127509
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_alerts.2755809476
Short name T31
Test name
Test status
Simulation time 1203826541 ps
CPU time 98.01 seconds
Started Sep 04 02:07:29 PM UTC 24
Finished Sep 04 02:09:09 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755809476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2755809476
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_classes.2030970457
Short name T442
Test name
Test status
Simulation time 2245452797 ps
CPU time 16.24 seconds
Started Sep 04 02:07:43 PM UTC 24
Finished Sep 04 02:08:01 PM UTC 24
Peak memory 263068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030970457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2030970457
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/19.alert_handler_sig_int_fail.2427749600
Short name T37
Test name
Test status
Simulation time 992233877 ps
CPU time 43.04 seconds
Started Sep 04 02:09:10 PM UTC 24
Finished Sep 04 02:09:55 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427749600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2427749600
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/19.alert_handler_smoke.2398303299
Short name T441
Test name
Test status
Simulation time 129634480 ps
CPU time 13.65 seconds
Started Sep 04 02:07:27 PM UTC 24
Finished Sep 04 02:07:42 PM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398303299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2398303299
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all.999383906
Short name T302
Test name
Test status
Simulation time 50319166285 ps
CPU time 1155.45 seconds
Started Sep 04 02:09:56 PM UTC 24
Finished Sep 04 02:29:25 PM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999383906 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all.999383906
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all_with_rand_reset.1187081624
Short name T104
Test name
Test status
Simulation time 11302285466 ps
CPU time 244.66 seconds
Started Sep 04 02:10:05 PM UTC 24
Finished Sep 04 02:14:13 PM UTC 24
Peak memory 279676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1187081624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.a
lert_handler_stress_all_with_rand_reset.1187081624
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/2.alert_handler_alert_accum_saturation.2253213316
Short name T43
Test name
Test status
Simulation time 139499604 ps
CPU time 5.47 seconds
Started Sep 04 01:40:05 PM UTC 24
Finished Sep 04 01:40:11 PM UTC 24
Peak memory 263172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253213316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2253213316
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy.2293254506
Short name T84
Test name
Test status
Simulation time 20933240546 ps
CPU time 1067.17 seconds
Started Sep 04 01:40:01 PM UTC 24
Finished Sep 04 01:58:00 PM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293254506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2293254506
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy_stress.181061021
Short name T17
Test name
Test status
Simulation time 254635570 ps
CPU time 18.98 seconds
Started Sep 04 01:40:03 PM UTC 24
Finished Sep 04 01:40:24 PM UTC 24
Peak memory 262712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181061021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.181061021
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_intr_timeout.678088676
Short name T86
Test name
Test status
Simulation time 945310899 ps
CPU time 73.67 seconds
Started Sep 04 01:39:52 PM UTC 24
Finished Sep 04 01:41:07 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678088676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.678088676
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg_stub_clk.76944140
Short name T335
Test name
Test status
Simulation time 7835521175 ps
CPU time 963.59 seconds
Started Sep 04 01:40:03 PM UTC 24
Finished Sep 04 01:56:18 PM UTC 24
Peak memory 301960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76944140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.76944140
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/2.alert_handler_ping_timeout.3708955980
Short name T158
Test name
Test status
Simulation time 19019317416 ps
CPU time 547.88 seconds
Started Sep 04 01:40:02 PM UTC 24
Finished Sep 04 01:49:17 PM UTC 24
Peak memory 263364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708955980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3708955980
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_alerts.34536651
Short name T44
Test name
Test status
Simulation time 895895220 ps
CPU time 33.41 seconds
Started Sep 04 01:39:47 PM UTC 24
Finished Sep 04 01:40:22 PM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34536651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran
dom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.34536651
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/2.alert_handler_sec_cm.3120711047
Short name T9
Test name
Test status
Simulation time 888996521 ps
CPU time 29.74 seconds
Started Sep 04 01:40:09 PM UTC 24
Finished Sep 04 01:40:40 PM UTC 24
Peak memory 297316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120711047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3120711047
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/2.alert_handler_sig_int_fail.910454071
Short name T35
Test name
Test status
Simulation time 37382753 ps
CPU time 5.21 seconds
Started Sep 04 01:39:58 PM UTC 24
Finished Sep 04 01:40:04 PM UTC 24
Peak memory 252664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910454071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.910454071
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/2.alert_handler_smoke.864743637
Short name T42
Test name
Test status
Simulation time 215856538 ps
CPU time 24.1 seconds
Started Sep 04 01:39:44 PM UTC 24
Finished Sep 04 01:40:10 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864743637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.864743637
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/2.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/20.alert_handler_entropy.3994410690
Short name T61
Test name
Test status
Simulation time 8637953118 ps
CPU time 954.52 seconds
Started Sep 04 02:11:53 PM UTC 24
Finished Sep 04 02:27:59 PM UTC 24
Peak memory 285568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994410690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3994410690
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/20.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_alert_accum.4129789946
Short name T448
Test name
Test status
Simulation time 156178037 ps
CPU time 13.84 seconds
Started Sep 04 02:11:50 PM UTC 24
Finished Sep 04 02:12:05 PM UTC 24
Peak memory 262896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129789946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.4129789946
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_intr_timeout.3481539609
Short name T72
Test name
Test status
Simulation time 1092567936 ps
CPU time 95.05 seconds
Started Sep 04 02:11:27 PM UTC 24
Finished Sep 04 02:13:04 PM UTC 24
Peak memory 269052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481539609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3481539609
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg.3368491863
Short name T372
Test name
Test status
Simulation time 53557141421 ps
CPU time 2869.04 seconds
Started Sep 04 02:12:11 PM UTC 24
Finished Sep 04 03:00:33 PM UTC 24
Peak memory 300512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368491863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3368491863
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/20.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg_stub_clk.4122504048
Short name T123
Test name
Test status
Simulation time 60046678955 ps
CPU time 2573.85 seconds
Started Sep 04 02:12:24 PM UTC 24
Finished Sep 04 02:55:47 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122504048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.4122504048
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/20.alert_handler_ping_timeout.111153998
Short name T352
Test name
Test status
Simulation time 43916228816 ps
CPU time 508.83 seconds
Started Sep 04 02:12:05 PM UTC 24
Finished Sep 04 02:20:40 PM UTC 24
Peak memory 263304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111153998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.111153998
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_alerts.3052109297
Short name T447
Test name
Test status
Simulation time 1476149483 ps
CPU time 42.05 seconds
Started Sep 04 02:11:08 PM UTC 24
Finished Sep 04 02:11:52 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052109297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3052109297
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/20.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_classes.3511758217
Short name T115
Test name
Test status
Simulation time 2547345170 ps
CPU time 51.88 seconds
Started Sep 04 02:11:17 PM UTC 24
Finished Sep 04 02:12:10 PM UTC 24
Peak memory 269140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511758217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3511758217
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/20.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/20.alert_handler_sig_int_fail.546765545
Short name T345
Test name
Test status
Simulation time 726402998 ps
CPU time 28.13 seconds
Started Sep 04 02:11:53 PM UTC 24
Finished Sep 04 02:12:22 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546765545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.546765545
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/20.alert_handler_smoke.137183286
Short name T446
Test name
Test status
Simulation time 1485423722 ps
CPU time 45.05 seconds
Started Sep 04 02:10:39 PM UTC 24
Finished Sep 04 02:11:26 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137183286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.137183286
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/20.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all.4205910098
Short name T559
Test name
Test status
Simulation time 250861449862 ps
CPU time 2182.57 seconds
Started Sep 04 02:12:38 PM UTC 24
Finished Sep 04 02:49:26 PM UTC 24
Peak memory 285756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205910098 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all.4205910098
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/20.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all_with_rand_reset.2383478409
Short name T218
Test name
Test status
Simulation time 4431413668 ps
CPU time 152.63 seconds
Started Sep 04 02:12:50 PM UTC 24
Finished Sep 04 02:15:25 PM UTC 24
Peak memory 285624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2383478409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.a
lert_handler_stress_all_with_rand_reset.2383478409
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/21.alert_handler_entropy.1012405808
Short name T149
Test name
Test status
Simulation time 127316671270 ps
CPU time 2003.82 seconds
Started Sep 04 02:14:15 PM UTC 24
Finished Sep 04 02:48:01 PM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012405808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1012405808
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/21.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_alert_accum.1265694544
Short name T263
Test name
Test status
Simulation time 1088023390 ps
CPU time 15.03 seconds
Started Sep 04 02:14:00 PM UTC 24
Finished Sep 04 02:14:17 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265694544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1265694544
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_intr_timeout.3056867934
Short name T134
Test name
Test status
Simulation time 849122858 ps
CPU time 26.85 seconds
Started Sep 04 02:13:34 PM UTC 24
Finished Sep 04 02:14:02 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056867934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3056867934
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg.494596476
Short name T384
Test name
Test status
Simulation time 52587398441 ps
CPU time 2955.81 seconds
Started Sep 04 02:14:20 PM UTC 24
Finished Sep 04 03:04:09 PM UTC 24
Peak memory 304676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494596476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.494596476
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/21.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg_stub_clk.3730744359
Short name T553
Test name
Test status
Simulation time 113755524950 ps
CPU time 2041.84 seconds
Started Sep 04 02:14:20 PM UTC 24
Finished Sep 04 02:48:46 PM UTC 24
Peak memory 295744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730744359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3730744359
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/21.alert_handler_ping_timeout.2155008102
Short name T350
Test name
Test status
Simulation time 242353106465 ps
CPU time 639.57 seconds
Started Sep 04 02:14:17 PM UTC 24
Finished Sep 04 02:25:04 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155008102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2155008102
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_alerts.1525343383
Short name T264
Test name
Test status
Simulation time 2278610714 ps
CPU time 99.47 seconds
Started Sep 04 02:13:10 PM UTC 24
Finished Sep 04 02:14:52 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525343383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1525343383
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/21.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_classes.1809140173
Short name T59
Test name
Test status
Simulation time 1047133060 ps
CPU time 60.42 seconds
Started Sep 04 02:13:27 PM UTC 24
Finished Sep 04 02:14:29 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809140173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1809140173
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/21.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/21.alert_handler_smoke.4272556446
Short name T73
Test name
Test status
Simulation time 40584255 ps
CPU time 4.38 seconds
Started Sep 04 02:13:04 PM UTC 24
Finished Sep 04 02:13:10 PM UTC 24
Peak memory 265280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272556446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.4272556446
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/21.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all.546150303
Short name T489
Test name
Test status
Simulation time 8432550918 ps
CPU time 925.84 seconds
Started Sep 04 02:14:25 PM UTC 24
Finished Sep 04 02:30:02 PM UTC 24
Peak memory 285492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546150303 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all.546150303
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/21.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all_with_rand_reset.2699663891
Short name T219
Test name
Test status
Simulation time 1115577301 ps
CPU time 125.94 seconds
Started Sep 04 02:14:30 PM UTC 24
Finished Sep 04 02:16:38 PM UTC 24
Peak memory 279740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2699663891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.a
lert_handler_stress_all_with_rand_reset.2699663891
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/22.alert_handler_entropy.3899131008
Short name T560
Test name
Test status
Simulation time 29975951406 ps
CPU time 2024.06 seconds
Started Sep 04 02:15:38 PM UTC 24
Finished Sep 04 02:49:48 PM UTC 24
Peak memory 300032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899131008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3899131008
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/22.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_alert_accum.1459925040
Short name T451
Test name
Test status
Simulation time 482926042 ps
CPU time 23.78 seconds
Started Sep 04 02:15:27 PM UTC 24
Finished Sep 04 02:15:52 PM UTC 24
Peak memory 269368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459925040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1459925040
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_intr_timeout.1156284456
Short name T450
Test name
Test status
Simulation time 1167820775 ps
CPU time 24.93 seconds
Started Sep 04 02:15:16 PM UTC 24
Finished Sep 04 02:15:42 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156284456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1156284456
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg_stub_clk.2320973845
Short name T117
Test name
Test status
Simulation time 169840576575 ps
CPU time 945.58 seconds
Started Sep 04 02:16:04 PM UTC 24
Finished Sep 04 02:32:01 PM UTC 24
Peak memory 300232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320973845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2320973845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/22.alert_handler_ping_timeout.2356066537
Short name T346
Test name
Test status
Simulation time 14374426121 ps
CPU time 224.81 seconds
Started Sep 04 02:15:42 PM UTC 24
Finished Sep 04 02:19:30 PM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356066537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2356066537
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_alerts.820722301
Short name T449
Test name
Test status
Simulation time 699152670 ps
CPU time 27.03 seconds
Started Sep 04 02:15:02 PM UTC 24
Finished Sep 04 02:15:31 PM UTC 24
Peak memory 269036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820722301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.820722301
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/22.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_classes.3592900030
Short name T121
Test name
Test status
Simulation time 379931396 ps
CPU time 31.22 seconds
Started Sep 04 02:15:04 PM UTC 24
Finished Sep 04 02:15:37 PM UTC 24
Peak memory 269468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592900030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3592900030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/22.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/22.alert_handler_sig_int_fail.1417851871
Short name T288
Test name
Test status
Simulation time 2715226634 ps
CPU time 50.59 seconds
Started Sep 04 02:15:32 PM UTC 24
Finished Sep 04 02:16:25 PM UTC 24
Peak memory 263036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417851871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1417851871
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/22.alert_handler_smoke.2578635181
Short name T266
Test name
Test status
Simulation time 1820498729 ps
CPU time 20.4 seconds
Started Sep 04 02:14:53 PM UTC 24
Finished Sep 04 02:15:15 PM UTC 24
Peak memory 263296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578635181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2578635181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/22.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all.1825562747
Short name T610
Test name
Test status
Simulation time 161793097499 ps
CPU time 2854.29 seconds
Started Sep 04 02:16:26 PM UTC 24
Finished Sep 04 03:04:34 PM UTC 24
Peak memory 304600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825562747 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all.1825562747
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/22.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/23.alert_handler_entropy.2798503824
Short name T557
Test name
Test status
Simulation time 108533992670 ps
CPU time 1868.46 seconds
Started Sep 04 02:17:34 PM UTC 24
Finished Sep 04 02:49:02 PM UTC 24
Peak memory 299832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798503824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2798503824
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/23.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_alert_accum.2485503773
Short name T455
Test name
Test status
Simulation time 5593266756 ps
CPU time 155.84 seconds
Started Sep 04 02:17:12 PM UTC 24
Finished Sep 04 02:19:50 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485503773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2485503773
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_intr_timeout.2061224059
Short name T454
Test name
Test status
Simulation time 140165656 ps
CPU time 20.49 seconds
Started Sep 04 02:17:11 PM UTC 24
Finished Sep 04 02:17:33 PM UTC 24
Peak memory 269052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061224059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2061224059
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg.127842028
Short name T382
Test name
Test status
Simulation time 98894139939 ps
CPU time 1685.03 seconds
Started Sep 04 02:17:55 PM UTC 24
Finished Sep 04 02:46:20 PM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127842028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.127842028
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/23.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg_stub_clk.120922007
Short name T621
Test name
Test status
Simulation time 159737803791 ps
CPU time 2872.27 seconds
Started Sep 04 02:18:28 PM UTC 24
Finished Sep 04 03:06:54 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120922007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.120922007
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/23.alert_handler_ping_timeout.1354725440
Short name T466
Test name
Test status
Simulation time 13837979311 ps
CPU time 498.56 seconds
Started Sep 04 02:17:35 PM UTC 24
Finished Sep 04 02:25:59 PM UTC 24
Peak memory 269512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354725440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1354725440
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_alerts.4162453500
Short name T452
Test name
Test status
Simulation time 59626294 ps
CPU time 7.92 seconds
Started Sep 04 02:16:58 PM UTC 24
Finished Sep 04 02:17:07 PM UTC 24
Peak memory 265020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162453500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.4162453500
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/23.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_classes.889300266
Short name T308
Test name
Test status
Simulation time 188372672 ps
CPU time 24.68 seconds
Started Sep 04 02:17:08 PM UTC 24
Finished Sep 04 02:17:34 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889300266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.889300266
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/23.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/23.alert_handler_sig_int_fail.2703546149
Short name T284
Test name
Test status
Simulation time 151136904 ps
CPU time 24.93 seconds
Started Sep 04 02:17:28 PM UTC 24
Finished Sep 04 02:17:54 PM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703546149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2703546149
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/23.alert_handler_smoke.1738320328
Short name T453
Test name
Test status
Simulation time 1669100126 ps
CPU time 38.54 seconds
Started Sep 04 02:16:47 PM UTC 24
Finished Sep 04 02:17:27 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738320328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1738320328
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/23.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/24.alert_handler_entropy.1146490396
Short name T501
Test name
Test status
Simulation time 16999632561 ps
CPU time 828.95 seconds
Started Sep 04 02:22:00 PM UTC 24
Finished Sep 04 02:35:59 PM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146490396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1146490396
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/24.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_alert_accum.145320505
Short name T462
Test name
Test status
Simulation time 4422329777 ps
CPU time 154.81 seconds
Started Sep 04 02:21:14 PM UTC 24
Finished Sep 04 02:23:52 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145320505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.145320505
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_intr_timeout.2651063874
Short name T459
Test name
Test status
Simulation time 2872080841 ps
CPU time 61.89 seconds
Started Sep 04 02:20:53 PM UTC 24
Finished Sep 04 02:21:57 PM UTC 24
Peak memory 263072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651063874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2651063874
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg.13861530
Short name T594
Test name
Test status
Simulation time 41785117383 ps
CPU time 2232.47 seconds
Started Sep 04 02:22:00 PM UTC 24
Finished Sep 04 02:59:37 PM UTC 24
Peak memory 297204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13861530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.13861530
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/24.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg_stub_clk.3913186385
Short name T536
Test name
Test status
Simulation time 26051556450 ps
CPU time 1354.86 seconds
Started Sep 04 02:22:15 PM UTC 24
Finished Sep 04 02:45:05 PM UTC 24
Peak memory 281480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913186385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3913186385
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/24.alert_handler_ping_timeout.642337031
Short name T353
Test name
Test status
Simulation time 23958839103 ps
CPU time 246.04 seconds
Started Sep 04 02:22:00 PM UTC 24
Finished Sep 04 02:26:10 PM UTC 24
Peak memory 263304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642337031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.642337031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_alerts.1654134941
Short name T457
Test name
Test status
Simulation time 1921674934 ps
CPU time 46.57 seconds
Started Sep 04 02:20:04 PM UTC 24
Finished Sep 04 02:20:52 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654134941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1654134941
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/24.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_classes.2905736936
Short name T458
Test name
Test status
Simulation time 2042910310 ps
CPU time 73.52 seconds
Started Sep 04 02:20:41 PM UTC 24
Finished Sep 04 02:21:57 PM UTC 24
Peak memory 269052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905736936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2905736936
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/24.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/24.alert_handler_sig_int_fail.501198081
Short name T309
Test name
Test status
Simulation time 90149350 ps
CPU time 15.94 seconds
Started Sep 04 02:21:57 PM UTC 24
Finished Sep 04 02:22:15 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501198081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.501198081
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/24.alert_handler_smoke.1790143690
Short name T456
Test name
Test status
Simulation time 356877976 ps
CPU time 10.62 seconds
Started Sep 04 02:19:52 PM UTC 24
Finished Sep 04 02:20:04 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790143690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1790143690
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/24.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all.2282659849
Short name T279
Test name
Test status
Simulation time 17885212786 ps
CPU time 1086.56 seconds
Started Sep 04 02:22:18 PM UTC 24
Finished Sep 04 02:40:38 PM UTC 24
Peak memory 302204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282659849 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all.2282659849
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/24.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all_with_rand_reset.3927949370
Short name T281
Test name
Test status
Simulation time 5646760182 ps
CPU time 562.85 seconds
Started Sep 04 02:22:38 PM UTC 24
Finished Sep 04 02:32:08 PM UTC 24
Peak memory 281788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3927949370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.a
lert_handler_stress_all_with_rand_reset.3927949370
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/25.alert_handler_entropy.292234129
Short name T510
Test name
Test status
Simulation time 25581005237 ps
CPU time 807.06 seconds
Started Sep 04 02:24:14 PM UTC 24
Finished Sep 04 02:37:52 PM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292234129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.292234129
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/25.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_alert_accum.2159533007
Short name T474
Test name
Test status
Simulation time 1723656190 ps
CPU time 204.89 seconds
Started Sep 04 02:24:06 PM UTC 24
Finished Sep 04 02:27:35 PM UTC 24
Peak memory 269040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159533007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2159533007
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/25.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_intr_timeout.52857965
Short name T463
Test name
Test status
Simulation time 2285921467 ps
CPU time 32.39 seconds
Started Sep 04 02:24:06 PM UTC 24
Finished Sep 04 02:24:40 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52857965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc
_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.52857965
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg_stub_clk.1371980823
Short name T590
Test name
Test status
Simulation time 37137772832 ps
CPU time 1947.89 seconds
Started Sep 04 02:24:42 PM UTC 24
Finished Sep 04 02:57:32 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371980823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1371980823
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_alerts.296239609
Short name T301
Test name
Test status
Simulation time 1405617464 ps
CPU time 53.93 seconds
Started Sep 04 02:23:05 PM UTC 24
Finished Sep 04 02:24:00 PM UTC 24
Peak memory 269156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296239609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.296239609
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/25.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_classes.4173249126
Short name T147
Test name
Test status
Simulation time 1824257228 ps
CPU time 47.24 seconds
Started Sep 04 02:23:53 PM UTC 24
Finished Sep 04 02:24:41 PM UTC 24
Peak memory 263132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173249126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.4173249126
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/25.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/25.alert_handler_smoke.1041948961
Short name T461
Test name
Test status
Simulation time 679703256 ps
CPU time 20.2 seconds
Started Sep 04 02:22:43 PM UTC 24
Finished Sep 04 02:23:04 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041948961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1041948961
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/25.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all.1117957630
Short name T475
Test name
Test status
Simulation time 7747583967 ps
CPU time 179.31 seconds
Started Sep 04 02:24:42 PM UTC 24
Finished Sep 04 02:27:44 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117957630 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all.1117957630
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/25.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all_with_rand_reset.1942560298
Short name T473
Test name
Test status
Simulation time 4894730512 ps
CPU time 149.1 seconds
Started Sep 04 02:24:49 PM UTC 24
Finished Sep 04 02:27:21 PM UTC 24
Peak memory 279548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1942560298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.a
lert_handler_stress_all_with_rand_reset.1942560298
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/26.alert_handler_entropy.214753423
Short name T633
Test name
Test status
Simulation time 41802596883 ps
CPU time 2589.86 seconds
Started Sep 04 02:26:09 PM UTC 24
Finished Sep 04 03:09:47 PM UTC 24
Peak memory 300512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214753423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.214753423
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/26.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_alert_accum.2234114286
Short name T323
Test name
Test status
Simulation time 11254789362 ps
CPU time 232.23 seconds
Started Sep 04 02:26:01 PM UTC 24
Finished Sep 04 02:29:57 PM UTC 24
Peak memory 269240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234114286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2234114286
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/26.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_intr_timeout.3204073619
Short name T469
Test name
Test status
Simulation time 1788620671 ps
CPU time 45.45 seconds
Started Sep 04 02:25:53 PM UTC 24
Finished Sep 04 02:26:40 PM UTC 24
Peak memory 263328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204073619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3204073619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg_stub_clk.807487
Short name T615
Test name
Test status
Simulation time 39230038815 ps
CPU time 2308.95 seconds
Started Sep 04 02:26:41 PM UTC 24
Finished Sep 04 03:05:34 PM UTC 24
Peak memory 303680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +U
VM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.807487
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/26.alert_handler_ping_timeout.2030006971
Short name T348
Test name
Test status
Simulation time 5812664448 ps
CPU time 188.08 seconds
Started Sep 04 02:26:10 PM UTC 24
Finished Sep 04 02:29:21 PM UTC 24
Peak memory 263304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030006971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2030006971
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_alerts.3535414204
Short name T467
Test name
Test status
Simulation time 430881320 ps
CPU time 42.24 seconds
Started Sep 04 02:25:20 PM UTC 24
Finished Sep 04 02:26:03 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535414204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3535414204
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/26.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_classes.793717730
Short name T60
Test name
Test status
Simulation time 936538722 ps
CPU time 15.64 seconds
Started Sep 04 02:25:52 PM UTC 24
Finished Sep 04 02:26:09 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793717730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.793717730
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/26.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/26.alert_handler_sig_int_fail.799064305
Short name T472
Test name
Test status
Simulation time 2212329568 ps
CPU time 59.35 seconds
Started Sep 04 02:26:04 PM UTC 24
Finished Sep 04 02:27:05 PM UTC 24
Peak memory 263328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799064305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.799064305
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/26.alert_handler_smoke.1977918366
Short name T465
Test name
Test status
Simulation time 3107350267 ps
CPU time 43.91 seconds
Started Sep 04 02:25:05 PM UTC 24
Finished Sep 04 02:25:50 PM UTC 24
Peak memory 269440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977918366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1977918366
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/26.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all.4215003965
Short name T642
Test name
Test status
Simulation time 156631929788 ps
CPU time 2659 seconds
Started Sep 04 02:26:46 PM UTC 24
Finished Sep 04 03:11:36 PM UTC 24
Peak memory 321184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215003965 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all.4215003965
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/26.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all_with_rand_reset.1095890536
Short name T490
Test name
Test status
Simulation time 9717346230 ps
CPU time 219.59 seconds
Started Sep 04 02:26:52 PM UTC 24
Finished Sep 04 02:30:35 PM UTC 24
Peak memory 279804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1095890536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.a
lert_handler_stress_all_with_rand_reset.1095890536
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/27.alert_handler_entropy.3193301421
Short name T122
Test name
Test status
Simulation time 275755937582 ps
CPU time 1122.21 seconds
Started Sep 04 02:28:01 PM UTC 24
Finished Sep 04 02:46:55 PM UTC 24
Peak memory 285568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193301421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3193301421
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/27.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_alert_accum.877196239
Short name T482
Test name
Test status
Simulation time 1093815421 ps
CPU time 60 seconds
Started Sep 04 02:27:47 PM UTC 24
Finished Sep 04 02:28:49 PM UTC 24
Peak memory 269404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877196239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.877196239
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/27.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_intr_timeout.1650731290
Short name T481
Test name
Test status
Simulation time 868552100 ps
CPU time 42.9 seconds
Started Sep 04 02:27:45 PM UTC 24
Finished Sep 04 02:28:30 PM UTC 24
Peak memory 263136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650731290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1650731290
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg.2642122181
Short name T370
Test name
Test status
Simulation time 55498457084 ps
CPU time 2289.5 seconds
Started Sep 04 02:28:11 PM UTC 24
Finished Sep 04 03:06:47 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642122181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2642122181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/27.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg_stub_clk.1327400918
Short name T605
Test name
Test status
Simulation time 126161686320 ps
CPU time 2053.61 seconds
Started Sep 04 02:28:16 PM UTC 24
Finished Sep 04 03:02:52 PM UTC 24
Peak memory 301960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327400918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1327400918
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/27.alert_handler_ping_timeout.3128515911
Short name T513
Test name
Test status
Simulation time 47526785568 ps
CPU time 596.55 seconds
Started Sep 04 02:28:03 PM UTC 24
Finished Sep 04 02:38:08 PM UTC 24
Peak memory 263368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128515911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3128515911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_alerts.3244644444
Short name T477
Test name
Test status
Simulation time 390831611 ps
CPU time 24.62 seconds
Started Sep 04 02:27:22 PM UTC 24
Finished Sep 04 02:27:48 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244644444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3244644444
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/27.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_classes.3873517523
Short name T476
Test name
Test status
Simulation time 528095212 ps
CPU time 9.19 seconds
Started Sep 04 02:27:36 PM UTC 24
Finished Sep 04 02:27:47 PM UTC 24
Peak memory 265308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873517523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3873517523
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/27.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/27.alert_handler_sig_int_fail.3616397878
Short name T480
Test name
Test status
Simulation time 842348122 ps
CPU time 25.56 seconds
Started Sep 04 02:27:49 PM UTC 24
Finished Sep 04 02:28:15 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616397878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3616397878
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/27.alert_handler_smoke.2601045794
Short name T479
Test name
Test status
Simulation time 1681356818 ps
CPU time 61.43 seconds
Started Sep 04 02:27:06 PM UTC 24
Finished Sep 04 02:28:10 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601045794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2601045794
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/27.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all_with_rand_reset.736865963
Short name T298
Test name
Test status
Simulation time 4180265095 ps
CPU time 164.39 seconds
Started Sep 04 02:28:31 PM UTC 24
Finished Sep 04 02:31:19 PM UTC 24
Peak memory 279552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=736865963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.al
ert_handler_stress_all_with_rand_reset.736865963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/28.alert_handler_entropy.3430416572
Short name T549
Test name
Test status
Simulation time 9322973036 ps
CPU time 1091.24 seconds
Started Sep 04 02:29:22 PM UTC 24
Finished Sep 04 02:47:46 PM UTC 24
Peak memory 285696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430416572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3430416572
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/28.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_alert_accum.1070750722
Short name T495
Test name
Test status
Simulation time 11922701034 ps
CPU time 214.63 seconds
Started Sep 04 02:29:13 PM UTC 24
Finished Sep 04 02:32:51 PM UTC 24
Peak memory 269100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070750722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1070750722
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/28.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_intr_timeout.2780735677
Short name T486
Test name
Test status
Simulation time 1591318912 ps
CPU time 8.77 seconds
Started Sep 04 02:29:10 PM UTC 24
Finished Sep 04 02:29:20 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780735677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2780735677
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg.646386574
Short name T374
Test name
Test status
Simulation time 31117303475 ps
CPU time 930.08 seconds
Started Sep 04 02:29:48 PM UTC 24
Finished Sep 04 02:45:31 PM UTC 24
Peak memory 279352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646386574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.646386574
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/28.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg_stub_clk.4288739909
Short name T614
Test name
Test status
Simulation time 87853318964 ps
CPU time 2099.79 seconds
Started Sep 04 02:29:51 PM UTC 24
Finished Sep 04 03:05:16 PM UTC 24
Peak memory 302216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288739909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.4288739909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_alerts.2536636616
Short name T485
Test name
Test status
Simulation time 987032465 ps
CPU time 21.01 seconds
Started Sep 04 02:28:50 PM UTC 24
Finished Sep 04 02:29:13 PM UTC 24
Peak memory 267132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536636616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2536636616
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/28.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_classes.940856924
Short name T487
Test name
Test status
Simulation time 8404316791 ps
CPU time 50.44 seconds
Started Sep 04 02:28:55 PM UTC 24
Finished Sep 04 02:29:47 PM UTC 24
Peak memory 262964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940856924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.940856924
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/28.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/28.alert_handler_sig_int_fail.2995395191
Short name T488
Test name
Test status
Simulation time 1747607546 ps
CPU time 28.24 seconds
Started Sep 04 02:29:20 PM UTC 24
Finished Sep 04 02:29:50 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995395191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2995395191
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/28.alert_handler_smoke.4243125482
Short name T484
Test name
Test status
Simulation time 794026448 ps
CPU time 32.67 seconds
Started Sep 04 02:28:35 PM UTC 24
Finished Sep 04 02:29:09 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243125482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.4243125482
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/28.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all.2386710769
Short name T585
Test name
Test status
Simulation time 56346295238 ps
CPU time 1530.11 seconds
Started Sep 04 02:29:58 PM UTC 24
Finished Sep 04 02:55:45 PM UTC 24
Peak memory 302204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386710769 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all.2386710769
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/28.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/29.alert_handler_entropy.3716330481
Short name T656
Test name
Test status
Simulation time 45299560271 ps
CPU time 2541.02 seconds
Started Sep 04 02:32:05 PM UTC 24
Finished Sep 04 03:14:53 PM UTC 24
Peak memory 300504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716330481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3716330481
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/29.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_alert_accum.1695548870
Short name T499
Test name
Test status
Simulation time 5265200807 ps
CPU time 139.76 seconds
Started Sep 04 02:31:34 PM UTC 24
Finished Sep 04 02:33:57 PM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695548870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1695548870
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/29.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_intr_timeout.1945587378
Short name T494
Test name
Test status
Simulation time 302862644 ps
CPU time 37.74 seconds
Started Sep 04 02:31:28 PM UTC 24
Finished Sep 04 02:32:08 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945587378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1945587378
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg.2172948072
Short name T381
Test name
Test status
Simulation time 7113064393 ps
CPU time 710.27 seconds
Started Sep 04 02:32:06 PM UTC 24
Finished Sep 04 02:44:05 PM UTC 24
Peak memory 279360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172948072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2172948072
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/29.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg_stub_clk.4010393644
Short name T556
Test name
Test status
Simulation time 8412070608 ps
CPU time 995.29 seconds
Started Sep 04 02:32:08 PM UTC 24
Finished Sep 04 02:48:56 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010393644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.4010393644
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/29.alert_handler_ping_timeout.1881914634
Short name T507
Test name
Test status
Simulation time 18188043449 ps
CPU time 293.93 seconds
Started Sep 04 02:32:05 PM UTC 24
Finished Sep 04 02:37:03 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881914634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1881914634
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_alerts.2799595104
Short name T492
Test name
Test status
Simulation time 110450866 ps
CPU time 11.77 seconds
Started Sep 04 02:31:20 PM UTC 24
Finished Sep 04 02:31:33 PM UTC 24
Peak memory 267324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799595104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2799595104
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/29.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_classes.1729740933
Short name T62
Test name
Test status
Simulation time 121921962 ps
CPU time 15.66 seconds
Started Sep 04 02:31:25 PM UTC 24
Finished Sep 04 02:31:42 PM UTC 24
Peak memory 263004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729740933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1729740933
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/29.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/29.alert_handler_sig_int_fail.1654027659
Short name T493
Test name
Test status
Simulation time 203352765 ps
CPU time 20.95 seconds
Started Sep 04 02:31:42 PM UTC 24
Finished Sep 04 02:32:05 PM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654027659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1654027659
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/29.alert_handler_smoke.2946955634
Short name T491
Test name
Test status
Simulation time 1429537287 ps
CPU time 49.36 seconds
Started Sep 04 02:30:36 PM UTC 24
Finished Sep 04 02:31:27 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946955634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2946955634
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/29.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all.4181028670
Short name T623
Test name
Test status
Simulation time 71029679863 ps
CPU time 2110.47 seconds
Started Sep 04 02:32:09 PM UTC 24
Finished Sep 04 03:07:43 PM UTC 24
Peak memory 302204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181028670 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all.4181028670
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/29.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all_with_rand_reset.4199231817
Short name T145
Test name
Test status
Simulation time 12278730833 ps
CPU time 218.45 seconds
Started Sep 04 02:32:48 PM UTC 24
Finished Sep 04 02:36:30 PM UTC 24
Peak memory 285948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4199231817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.a
lert_handler_stress_all_with_rand_reset.4199231817
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/3.alert_handler_alert_accum_saturation.1975929407
Short name T46
Test name
Test status
Simulation time 73359446 ps
CPU time 5.06 seconds
Started Sep 04 01:40:56 PM UTC 24
Finished Sep 04 01:41:02 PM UTC 24
Peak memory 263172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975929407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1975929407
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy.3454486413
Short name T119
Test name
Test status
Simulation time 124137046169 ps
CPU time 1540.89 seconds
Started Sep 04 01:40:24 PM UTC 24
Finished Sep 04 02:06:23 PM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454486413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3454486413
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy_stress.3164361675
Short name T18
Test name
Test status
Simulation time 630253200 ps
CPU time 34.28 seconds
Started Sep 04 01:40:44 PM UTC 24
Finished Sep 04 01:41:20 PM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164361675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3164361675
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_alert_accum.3697398156
Short name T68
Test name
Test status
Simulation time 1884612149 ps
CPU time 150.52 seconds
Started Sep 04 01:40:23 PM UTC 24
Finished Sep 04 01:42:57 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697398156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3697398156
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_intr_timeout.3806895767
Short name T85
Test name
Test status
Simulation time 2014571951 ps
CPU time 41.84 seconds
Started Sep 04 01:40:12 PM UTC 24
Finished Sep 04 01:40:55 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806895767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3806895767
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg_stub_clk.3828557755
Short name T120
Test name
Test status
Simulation time 48397595987 ps
CPU time 2609.48 seconds
Started Sep 04 01:40:41 PM UTC 24
Finished Sep 04 02:24:39 PM UTC 24
Peak memory 302276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828557755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3828557755
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/3.alert_handler_ping_timeout.218888904
Short name T16
Test name
Test status
Simulation time 5023109977 ps
CPU time 191.29 seconds
Started Sep 04 01:40:38 PM UTC 24
Finished Sep 04 01:43:52 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218888904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.218888904
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_alerts.1529480835
Short name T106
Test name
Test status
Simulation time 2207918915 ps
CPU time 47.36 seconds
Started Sep 04 01:40:11 PM UTC 24
Finished Sep 04 01:41:00 PM UTC 24
Peak memory 269140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529480835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1529480835
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_classes.3785164810
Short name T28
Test name
Test status
Simulation time 742374135 ps
CPU time 72.26 seconds
Started Sep 04 01:40:12 PM UTC 24
Finished Sep 04 01:41:26 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785164810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3785164810
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/3.alert_handler_sec_cm.3406210628
Short name T40
Test name
Test status
Simulation time 362431875 ps
CPU time 14.49 seconds
Started Sep 04 01:41:00 PM UTC 24
Finished Sep 04 01:41:16 PM UTC 24
Peak memory 297452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406210628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_
handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3406210628
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/3.alert_handler_smoke.1668760025
Short name T105
Test name
Test status
Simulation time 785914873 ps
CPU time 45.73 seconds
Started Sep 04 01:40:10 PM UTC 24
Finished Sep 04 01:40:57 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668760025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1668760025
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all.948591091
Short name T272
Test name
Test status
Simulation time 15842935816 ps
CPU time 362.31 seconds
Started Sep 04 01:40:56 PM UTC 24
Finished Sep 04 01:47:03 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948591091 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all.948591091
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/3.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/30.alert_handler_entropy.1081251663
Short name T152
Test name
Test status
Simulation time 16315339355 ps
CPU time 1595 seconds
Started Sep 04 02:34:45 PM UTC 24
Finished Sep 04 03:01:39 PM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081251663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1081251663
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/30.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_alert_accum.4039199425
Short name T503
Test name
Test status
Simulation time 7184481284 ps
CPU time 136.04 seconds
Started Sep 04 02:33:50 PM UTC 24
Finished Sep 04 02:36:09 PM UTC 24
Peak memory 265008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039199425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.4039199425
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/30.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_intr_timeout.3111017254
Short name T498
Test name
Test status
Simulation time 124181347 ps
CPU time 12.05 seconds
Started Sep 04 02:33:36 PM UTC 24
Finished Sep 04 02:33:50 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111017254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3111017254
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg.3442883309
Short name T399
Test name
Test status
Simulation time 41049337608 ps
CPU time 1282.66 seconds
Started Sep 04 02:35:50 PM UTC 24
Finished Sep 04 02:57:27 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442883309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3442883309
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/30.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg_stub_clk.1101551625
Short name T671
Test name
Test status
Simulation time 202418785962 ps
CPU time 2446.67 seconds
Started Sep 04 02:36:01 PM UTC 24
Finished Sep 04 03:17:15 PM UTC 24
Peak memory 300512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101551625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1101551625
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/30.alert_handler_ping_timeout.782624516
Short name T356
Test name
Test status
Simulation time 1517585463 ps
CPU time 49.3 seconds
Started Sep 04 02:34:58 PM UTC 24
Finished Sep 04 02:35:49 PM UTC 24
Peak memory 263240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782624516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.782624516
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_alerts.2829700877
Short name T500
Test name
Test status
Simulation time 3489695092 ps
CPU time 86.48 seconds
Started Sep 04 02:33:15 PM UTC 24
Finished Sep 04 02:34:44 PM UTC 24
Peak memory 263292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829700877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2829700877
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/30.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_classes.2335371340
Short name T497
Test name
Test status
Simulation time 535406853 ps
CPU time 13.8 seconds
Started Sep 04 02:33:20 PM UTC 24
Finished Sep 04 02:33:35 PM UTC 24
Peak memory 263004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335371340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2335371340
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/30.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/30.alert_handler_sig_int_fail.2246380185
Short name T282
Test name
Test status
Simulation time 2533730942 ps
CPU time 57.56 seconds
Started Sep 04 02:33:58 PM UTC 24
Finished Sep 04 02:34:57 PM UTC 24
Peak memory 262964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246380185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2246380185
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/30.alert_handler_smoke.2482328564
Short name T496
Test name
Test status
Simulation time 534474358 ps
CPU time 20.3 seconds
Started Sep 04 02:32:53 PM UTC 24
Finished Sep 04 02:33:14 PM UTC 24
Peak memory 267392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482328564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2482328564
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/30.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all.2557664065
Short name T153
Test name
Test status
Simulation time 26558164376 ps
CPU time 1971.03 seconds
Started Sep 04 02:36:05 PM UTC 24
Finished Sep 04 03:09:20 PM UTC 24
Peak memory 301948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557664065 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all.2557664065
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/30.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all_with_rand_reset.477977295
Short name T511
Test name
Test status
Simulation time 5005110372 ps
CPU time 109.32 seconds
Started Sep 04 02:36:12 PM UTC 24
Finished Sep 04 02:38:03 PM UTC 24
Peak memory 279808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=477977295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.al
ert_handler_stress_all_with_rand_reset.477977295
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/31.alert_handler_entropy.1407533597
Short name T678
Test name
Test status
Simulation time 191538120657 ps
CPU time 2646.46 seconds
Started Sep 04 02:37:06 PM UTC 24
Finished Sep 04 03:21:42 PM UTC 24
Peak memory 304600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407533597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1407533597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/31.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_alert_accum.3379068201
Short name T526
Test name
Test status
Simulation time 7248438903 ps
CPU time 222.25 seconds
Started Sep 04 02:37:03 PM UTC 24
Finished Sep 04 02:40:48 PM UTC 24
Peak memory 269100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379068201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3379068201
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/31.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_intr_timeout.2146717252
Short name T509
Test name
Test status
Simulation time 6402294283 ps
CPU time 42.63 seconds
Started Sep 04 02:36:48 PM UTC 24
Finished Sep 04 02:37:32 PM UTC 24
Peak memory 269144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146717252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2146717252
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg.1840070991
Short name T377
Test name
Test status
Simulation time 35415108615 ps
CPU time 1870.58 seconds
Started Sep 04 02:37:32 PM UTC 24
Finished Sep 04 03:09:03 PM UTC 24
Peak memory 301884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840070991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1840070991
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/31.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg_stub_clk.1013617755
Short name T573
Test name
Test status
Simulation time 38996057984 ps
CPU time 922.6 seconds
Started Sep 04 02:37:39 PM UTC 24
Finished Sep 04 02:53:13 PM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013617755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1013617755
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/31.alert_handler_ping_timeout.185728235
Short name T349
Test name
Test status
Simulation time 32229264191 ps
CPU time 456.73 seconds
Started Sep 04 02:37:19 PM UTC 24
Finished Sep 04 02:45:03 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185728235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.185728235
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_alerts.1289082950
Short name T506
Test name
Test status
Simulation time 1447275078 ps
CPU time 33.74 seconds
Started Sep 04 02:36:26 PM UTC 24
Finished Sep 04 02:37:01 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289082950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1289082950
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/31.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_classes.2968095723
Short name T508
Test name
Test status
Simulation time 750083351 ps
CPU time 33.6 seconds
Started Sep 04 02:36:30 PM UTC 24
Finished Sep 04 02:37:05 PM UTC 24
Peak memory 269084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968095723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2968095723
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/31.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/31.alert_handler_sig_int_fail.275104371
Short name T290
Test name
Test status
Simulation time 475332782 ps
CPU time 13.45 seconds
Started Sep 04 02:37:04 PM UTC 24
Finished Sep 04 02:37:19 PM UTC 24
Peak memory 263072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275104371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.275104371
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/31.alert_handler_smoke.2266180530
Short name T504
Test name
Test status
Simulation time 337108609 ps
CPU time 12.23 seconds
Started Sep 04 02:36:12 PM UTC 24
Finished Sep 04 02:36:25 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266180530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2266180530
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/31.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all.2831511890
Short name T130
Test name
Test status
Simulation time 77805271388 ps
CPU time 2463.86 seconds
Started Sep 04 02:37:51 PM UTC 24
Finished Sep 04 03:19:23 PM UTC 24
Peak memory 304864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831511890 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all.2831511890
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/31.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all_with_rand_reset.1532964765
Short name T148
Test name
Test status
Simulation time 4963789551 ps
CPU time 526.11 seconds
Started Sep 04 02:37:54 PM UTC 24
Finished Sep 04 02:46:46 PM UTC 24
Peak memory 283644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1532964765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.a
lert_handler_stress_all_with_rand_reset.1532964765
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/32.alert_handler_entropy.943483036
Short name T591
Test name
Test status
Simulation time 76086384882 ps
CPU time 1171.52 seconds
Started Sep 04 02:38:48 PM UTC 24
Finished Sep 04 02:58:34 PM UTC 24
Peak memory 285700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943483036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.943483036
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/32.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_alert_accum.1305050390
Short name T532
Test name
Test status
Simulation time 6654084477 ps
CPU time 252.34 seconds
Started Sep 04 02:38:21 PM UTC 24
Finished Sep 04 02:42:37 PM UTC 24
Peak memory 269104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305050390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1305050390
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/32.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_intr_timeout.3512778190
Short name T516
Test name
Test status
Simulation time 968759691 ps
CPU time 16.38 seconds
Started Sep 04 02:38:18 PM UTC 24
Finished Sep 04 02:38:35 PM UTC 24
Peak memory 267104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512778190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3512778190
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg.4239096757
Short name T681
Test name
Test status
Simulation time 92475764726 ps
CPU time 2627.33 seconds
Started Sep 04 02:39:10 PM UTC 24
Finished Sep 04 03:23:27 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239096757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.4239096757
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/32.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg_stub_clk.3249049216
Short name T630
Test name
Test status
Simulation time 53437315177 ps
CPU time 1784.42 seconds
Started Sep 04 02:39:10 PM UTC 24
Finished Sep 04 03:09:15 PM UTC 24
Peak memory 295816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249049216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3249049216
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/32.alert_handler_ping_timeout.521432935
Short name T524
Test name
Test status
Simulation time 3010877700 ps
CPU time 110.86 seconds
Started Sep 04 02:38:48 PM UTC 24
Finished Sep 04 02:40:41 PM UTC 24
Peak memory 269448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521432935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.521432935
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_alerts.829815595
Short name T514
Test name
Test status
Simulation time 225053841 ps
CPU time 6.87 seconds
Started Sep 04 02:38:08 PM UTC 24
Finished Sep 04 02:38:16 PM UTC 24
Peak memory 269088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829815595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.829815595
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/32.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_classes.1869596911
Short name T517
Test name
Test status
Simulation time 871182643 ps
CPU time 35.19 seconds
Started Sep 04 02:38:10 PM UTC 24
Finished Sep 04 02:38:46 PM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869596911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1869596911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/32.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/32.alert_handler_sig_int_fail.99724277
Short name T523
Test name
Test status
Simulation time 5305191086 ps
CPU time 84.31 seconds
Started Sep 04 02:38:36 PM UTC 24
Finished Sep 04 02:40:03 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99724277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig
_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.99724277
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/32.alert_handler_smoke.1170001663
Short name T520
Test name
Test status
Simulation time 957176729 ps
CPU time 61.12 seconds
Started Sep 04 02:38:05 PM UTC 24
Finished Sep 04 02:39:07 PM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170001663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1170001663
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/32.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all.889541682
Short name T676
Test name
Test status
Simulation time 130788976470 ps
CPU time 2381.01 seconds
Started Sep 04 02:39:58 PM UTC 24
Finished Sep 04 03:20:07 PM UTC 24
Peak memory 298456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889541682 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all.889541682
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/32.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all_with_rand_reset.1096510691
Short name T539
Test name
Test status
Simulation time 4304941032 ps
CPU time 332.66 seconds
Started Sep 04 02:40:02 PM UTC 24
Finished Sep 04 02:45:40 PM UTC 24
Peak memory 281852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1096510691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.a
lert_handler_stress_all_with_rand_reset.1096510691
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/33.alert_handler_entropy.180178304
Short name T641
Test name
Test status
Simulation time 216285206112 ps
CPU time 1812.73 seconds
Started Sep 04 02:41:00 PM UTC 24
Finished Sep 04 03:11:33 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180178304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.180178304
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/33.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_alert_accum.3673577579
Short name T528
Test name
Test status
Simulation time 830745459 ps
CPU time 23.59 seconds
Started Sep 04 02:40:43 PM UTC 24
Finished Sep 04 02:41:07 PM UTC 24
Peak memory 269036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673577579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3673577579
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/33.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_intr_timeout.3516353086
Short name T529
Test name
Test status
Simulation time 416812128 ps
CPU time 29.73 seconds
Started Sep 04 02:40:42 PM UTC 24
Finished Sep 04 02:41:13 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516353086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3516353086
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg.2948185844
Short name T385
Test name
Test status
Simulation time 96378295084 ps
CPU time 1580.18 seconds
Started Sep 04 02:41:14 PM UTC 24
Finished Sep 04 03:07:52 PM UTC 24
Peak memory 285828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948185844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2948185844
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/33.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg_stub_clk.1381100203
Short name T689
Test name
Test status
Simulation time 37844199332 ps
CPU time 2663.23 seconds
Started Sep 04 02:41:21 PM UTC 24
Finished Sep 04 03:26:14 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381100203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1381100203
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/33.alert_handler_ping_timeout.1197249443
Short name T537
Test name
Test status
Simulation time 16829368665 ps
CPU time 234.69 seconds
Started Sep 04 02:41:08 PM UTC 24
Finished Sep 04 02:45:07 PM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197249443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1197249443
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_alerts.4097220477
Short name T525
Test name
Test status
Simulation time 226237099 ps
CPU time 8.33 seconds
Started Sep 04 02:40:32 PM UTC 24
Finished Sep 04 02:40:41 PM UTC 24
Peak memory 265020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097220477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.4097220477
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/33.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_classes.1208947194
Short name T527
Test name
Test status
Simulation time 1007248542 ps
CPU time 18 seconds
Started Sep 04 02:40:40 PM UTC 24
Finished Sep 04 02:41:00 PM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208947194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1208947194
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/33.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/33.alert_handler_sig_int_fail.3945617662
Short name T530
Test name
Test status
Simulation time 215861223 ps
CPU time 28.66 seconds
Started Sep 04 02:40:50 PM UTC 24
Finished Sep 04 02:41:20 PM UTC 24
Peak memory 263292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945617662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3945617662
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/33.alert_handler_smoke.1340280950
Short name T521
Test name
Test status
Simulation time 1388122806 ps
CPU time 26.02 seconds
Started Sep 04 02:40:03 PM UTC 24
Finished Sep 04 02:40:31 PM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340280950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1340280950
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/33.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all.3684016021
Short name T687
Test name
Test status
Simulation time 37882783784 ps
CPU time 2625.41 seconds
Started Sep 04 02:41:30 PM UTC 24
Finished Sep 04 03:25:48 PM UTC 24
Peak memory 304600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684016021 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all.3684016021
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/33.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/34.alert_handler_entropy.3957082563
Short name T648
Test name
Test status
Simulation time 192630455585 ps
CPU time 1683.76 seconds
Started Sep 04 02:45:03 PM UTC 24
Finished Sep 04 03:13:27 PM UTC 24
Peak memory 285824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957082563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3957082563
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/34.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_alert_accum.2076604128
Short name T546
Test name
Test status
Simulation time 2176878492 ps
CPU time 125.18 seconds
Started Sep 04 02:44:44 PM UTC 24
Finished Sep 04 02:46:52 PM UTC 24
Peak memory 269432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076604128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2076604128
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/34.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_intr_timeout.1462175046
Short name T540
Test name
Test status
Simulation time 1866366359 ps
CPU time 77.12 seconds
Started Sep 04 02:44:35 PM UTC 24
Finished Sep 04 02:45:54 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462175046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1462175046
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg.2605641450
Short name T660
Test name
Test status
Simulation time 103584222664 ps
CPU time 1779.12 seconds
Started Sep 04 02:45:08 PM UTC 24
Finished Sep 04 03:15:07 PM UTC 24
Peak memory 285432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605641450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2605641450
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/34.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg_stub_clk.4032934877
Short name T677
Test name
Test status
Simulation time 63167808116 ps
CPU time 2080.23 seconds
Started Sep 04 02:45:12 PM UTC 24
Finished Sep 04 03:20:16 PM UTC 24
Peak memory 302284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032934877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.4032934877
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/34.alert_handler_ping_timeout.459659628
Short name T359
Test name
Test status
Simulation time 11499141767 ps
CPU time 505.62 seconds
Started Sep 04 02:45:07 PM UTC 24
Finished Sep 04 02:53:40 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459659628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.459659628
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_alerts.3376545052
Short name T534
Test name
Test status
Simulation time 97131311 ps
CPU time 15.8 seconds
Started Sep 04 02:44:17 PM UTC 24
Finished Sep 04 02:44:34 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376545052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3376545052
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/34.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_classes.2997520328
Short name T541
Test name
Test status
Simulation time 1724022875 ps
CPU time 79.86 seconds
Started Sep 04 02:44:34 PM UTC 24
Finished Sep 04 02:45:55 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997520328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2997520328
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/34.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/34.alert_handler_sig_int_fail.213604832
Short name T538
Test name
Test status
Simulation time 712851853 ps
CPU time 22.67 seconds
Started Sep 04 02:44:46 PM UTC 24
Finished Sep 04 02:45:10 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213604832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.213604832
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/34.alert_handler_smoke.297800358
Short name T535
Test name
Test status
Simulation time 680604033 ps
CPU time 34.85 seconds
Started Sep 04 02:44:06 PM UTC 24
Finished Sep 04 02:44:43 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297800358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.297800358
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/34.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all.3999801762
Short name T624
Test name
Test status
Simulation time 26852587743 ps
CPU time 1316.9 seconds
Started Sep 04 02:45:33 PM UTC 24
Finished Sep 04 03:07:46 PM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999801762 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all.3999801762
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/34.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/35.alert_handler_entropy.559243416
Short name T680
Test name
Test status
Simulation time 129528517317 ps
CPU time 2140.04 seconds
Started Sep 04 02:46:34 PM UTC 24
Finished Sep 04 03:22:39 PM UTC 24
Peak memory 304680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559243416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.559243416
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/35.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_alert_accum.805304996
Short name T554
Test name
Test status
Simulation time 2620815719 ps
CPU time 135.39 seconds
Started Sep 04 02:46:29 PM UTC 24
Finished Sep 04 02:48:47 PM UTC 24
Peak memory 269212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805304996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.805304996
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/35.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_intr_timeout.1598840909
Short name T545
Test name
Test status
Simulation time 1691946783 ps
CPU time 19.2 seconds
Started Sep 04 02:46:26 PM UTC 24
Finished Sep 04 02:46:46 PM UTC 24
Peak memory 269080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598840909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1598840909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg.2164709943
Short name T368
Test name
Test status
Simulation time 458987023934 ps
CPU time 3147.24 seconds
Started Sep 04 02:46:47 PM UTC 24
Finished Sep 04 03:39:53 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164709943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2164709943
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/35.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg_stub_clk.3324093190
Short name T638
Test name
Test status
Simulation time 48680252348 ps
CPU time 1388.73 seconds
Started Sep 04 02:46:53 PM UTC 24
Finished Sep 04 03:10:19 PM UTC 24
Peak memory 301888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324093190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3324093190
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/35.alert_handler_ping_timeout.1492564607
Short name T358
Test name
Test status
Simulation time 16094405913 ps
CPU time 290.66 seconds
Started Sep 04 02:46:47 PM UTC 24
Finished Sep 04 02:51:42 PM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492564607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1492564607
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_alerts.298286779
Short name T542
Test name
Test status
Simulation time 492524227 ps
CPU time 27.76 seconds
Started Sep 04 02:45:56 PM UTC 24
Finished Sep 04 02:46:25 PM UTC 24
Peak memory 269052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298286779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.298286779
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/35.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_classes.3110524494
Short name T126
Test name
Test status
Simulation time 1799223818 ps
CPU time 29.9 seconds
Started Sep 04 02:46:22 PM UTC 24
Finished Sep 04 02:46:53 PM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110524494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3110524494
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/35.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/35.alert_handler_sig_int_fail.2723740662
Short name T547
Test name
Test status
Simulation time 276272912 ps
CPU time 36.92 seconds
Started Sep 04 02:46:32 PM UTC 24
Finished Sep 04 02:47:10 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723740662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2723740662
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/35.alert_handler_smoke.3169369061
Short name T544
Test name
Test status
Simulation time 275725182 ps
CPU time 36.77 seconds
Started Sep 04 02:45:55 PM UTC 24
Finished Sep 04 02:46:33 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169369061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3169369061
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/35.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all.2699593159
Short name T324
Test name
Test status
Simulation time 13968505347 ps
CPU time 493.89 seconds
Started Sep 04 02:46:54 PM UTC 24
Finished Sep 04 02:55:15 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699593159 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all.2699593159
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/35.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/36.alert_handler_entropy.3336511177
Short name T694
Test name
Test status
Simulation time 171303588598 ps
CPU time 2458.56 seconds
Started Sep 04 02:47:55 PM UTC 24
Finished Sep 04 03:29:20 PM UTC 24
Peak memory 300900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336511177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3336511177
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/36.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_alert_accum.1106984264
Short name T558
Test name
Test status
Simulation time 621474241 ps
CPU time 76.72 seconds
Started Sep 04 02:47:48 PM UTC 24
Finished Sep 04 02:49:07 PM UTC 24
Peak memory 269036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106984264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1106984264
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/36.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_intr_timeout.2009970241
Short name T551
Test name
Test status
Simulation time 727478055 ps
CPU time 12.06 seconds
Started Sep 04 02:47:41 PM UTC 24
Finished Sep 04 02:47:54 PM UTC 24
Peak memory 262936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009970241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2009970241
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg.2461590991
Short name T598
Test name
Test status
Simulation time 8659795885 ps
CPU time 757 seconds
Started Sep 04 02:48:08 PM UTC 24
Finished Sep 04 03:00:54 PM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461590991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2461590991
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/36.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg_stub_clk.1344200927
Short name T686
Test name
Test status
Simulation time 171858581360 ps
CPU time 2178.99 seconds
Started Sep 04 02:48:48 PM UTC 24
Finished Sep 04 03:25:31 PM UTC 24
Peak memory 295744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344200927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1344200927
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/36.alert_handler_ping_timeout.1310725920
Short name T564
Test name
Test status
Simulation time 2569736123 ps
CPU time 129.27 seconds
Started Sep 04 02:48:04 PM UTC 24
Finished Sep 04 02:50:16 PM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310725920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1310725920
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_alerts.3467812720
Short name T550
Test name
Test status
Simulation time 163105446 ps
CPU time 15.73 seconds
Started Sep 04 02:47:30 PM UTC 24
Finished Sep 04 02:47:47 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467812720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3467812720
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/36.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_classes.2921926454
Short name T555
Test name
Test status
Simulation time 812670677 ps
CPU time 74.45 seconds
Started Sep 04 02:47:38 PM UTC 24
Finished Sep 04 02:48:55 PM UTC 24
Peak memory 263004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921926454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2921926454
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/36.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/36.alert_handler_sig_int_fail.663285015
Short name T552
Test name
Test status
Simulation time 101064118 ps
CPU time 18.33 seconds
Started Sep 04 02:47:48 PM UTC 24
Finished Sep 04 02:48:07 PM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663285015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.663285015
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/36.alert_handler_smoke.357886383
Short name T548
Test name
Test status
Simulation time 208620125 ps
CPU time 25.63 seconds
Started Sep 04 02:47:11 PM UTC 24
Finished Sep 04 02:47:38 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357886383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.357886383
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/36.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all_with_rand_reset.1500882545
Short name T129
Test name
Test status
Simulation time 23431592907 ps
CPU time 668.63 seconds
Started Sep 04 02:48:55 PM UTC 24
Finished Sep 04 03:00:12 PM UTC 24
Peak memory 285620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1500882545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.a
lert_handler_stress_all_with_rand_reset.1500882545
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/37.alert_handler_entropy.3804426105
Short name T657
Test name
Test status
Simulation time 61553785265 ps
CPU time 1475.61 seconds
Started Sep 04 02:50:03 PM UTC 24
Finished Sep 04 03:14:56 PM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804426105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3804426105
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/37.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_alert_accum.1093472338
Short name T574
Test name
Test status
Simulation time 6480754951 ps
CPU time 208.09 seconds
Started Sep 04 02:49:50 PM UTC 24
Finished Sep 04 02:53:22 PM UTC 24
Peak memory 269432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093472338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1093472338
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/37.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_intr_timeout.2510914568
Short name T562
Test name
Test status
Simulation time 680672643 ps
CPU time 32.34 seconds
Started Sep 04 02:49:28 PM UTC 24
Finished Sep 04 02:50:02 PM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510914568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2510914568
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg.1542015238
Short name T367
Test name
Test status
Simulation time 175137221166 ps
CPU time 2255.41 seconds
Started Sep 04 02:50:07 PM UTC 24
Finished Sep 04 03:28:08 PM UTC 24
Peak memory 303352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542015238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1542015238
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/37.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg_stub_clk.3795341800
Short name T683
Test name
Test status
Simulation time 168174931211 ps
CPU time 1974.01 seconds
Started Sep 04 02:50:17 PM UTC 24
Finished Sep 04 03:23:33 PM UTC 24
Peak memory 295740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795341800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3795341800
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/37.alert_handler_ping_timeout.827582643
Short name T570
Test name
Test status
Simulation time 5482147026 ps
CPU time 109.73 seconds
Started Sep 04 02:50:06 PM UTC 24
Finished Sep 04 02:51:58 PM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827582643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.827582643
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_alerts.3177409852
Short name T565
Test name
Test status
Simulation time 1949736645 ps
CPU time 82.46 seconds
Started Sep 04 02:49:05 PM UTC 24
Finished Sep 04 02:50:29 PM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177409852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3177409852
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/37.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_classes.919122326
Short name T561
Test name
Test status
Simulation time 551729505 ps
CPU time 52.94 seconds
Started Sep 04 02:49:07 PM UTC 24
Finished Sep 04 02:50:02 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919122326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.919122326
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/37.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/37.alert_handler_sig_int_fail.1529518563
Short name T566
Test name
Test status
Simulation time 474591223 ps
CPU time 32.31 seconds
Started Sep 04 02:50:02 PM UTC 24
Finished Sep 04 02:50:36 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529518563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1529518563
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/37.alert_handler_smoke.3233714817
Short name T563
Test name
Test status
Simulation time 754222530 ps
CPU time 68 seconds
Started Sep 04 02:48:57 PM UTC 24
Finished Sep 04 02:50:07 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233714817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3233714817
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/37.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all.52078981
Short name T286
Test name
Test status
Simulation time 31433101720 ps
CPU time 2069.55 seconds
Started Sep 04 02:50:30 PM UTC 24
Finished Sep 04 03:25:24 PM UTC 24
Peak memory 299908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52078981 -assert nopostproc +UVM_TES
TNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all.52078981
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/37.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all_with_rand_reset.3166177312
Short name T572
Test name
Test status
Simulation time 5889135423 ps
CPU time 131.86 seconds
Started Sep 04 02:50:37 PM UTC 24
Finished Sep 04 02:52:51 PM UTC 24
Peak memory 279804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3166177312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.a
lert_handler_stress_all_with_rand_reset.3166177312
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/38.alert_handler_entropy.3565945429
Short name T675
Test name
Test status
Simulation time 106672469097 ps
CPU time 1641.27 seconds
Started Sep 04 02:51:59 PM UTC 24
Finished Sep 04 03:19:40 PM UTC 24
Peak memory 285492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565945429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3565945429
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/38.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_alert_accum.3621804074
Short name T583
Test name
Test status
Simulation time 2973768784 ps
CPU time 168.87 seconds
Started Sep 04 02:51:43 PM UTC 24
Finished Sep 04 02:54:35 PM UTC 24
Peak memory 269432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621804074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3621804074
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/38.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_intr_timeout.1116599295
Short name T571
Test name
Test status
Simulation time 293452256 ps
CPU time 26.42 seconds
Started Sep 04 02:51:36 PM UTC 24
Finished Sep 04 02:52:04 PM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116599295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1116599295
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg_stub_clk.1454283788
Short name T697
Test name
Test status
Simulation time 151492481687 ps
CPU time 2321.99 seconds
Started Sep 04 02:53:04 PM UTC 24
Finished Sep 04 03:32:12 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454283788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1454283788
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/38.alert_handler_ping_timeout.1903596683
Short name T576
Test name
Test status
Simulation time 2270617688 ps
CPU time 98.65 seconds
Started Sep 04 02:52:04 PM UTC 24
Finished Sep 04 02:53:45 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903596683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1903596683
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_alerts.168189890
Short name T568
Test name
Test status
Simulation time 195131442 ps
CPU time 25.58 seconds
Started Sep 04 02:50:55 PM UTC 24
Finished Sep 04 02:51:22 PM UTC 24
Peak memory 263012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168189890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.168189890
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/38.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_classes.3513990985
Short name T127
Test name
Test status
Simulation time 214814398 ps
CPU time 9.63 seconds
Started Sep 04 02:51:24 PM UTC 24
Finished Sep 04 02:51:35 PM UTC 24
Peak memory 267028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513990985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3513990985
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/38.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/38.alert_handler_sig_int_fail.1500975268
Short name T150
Test name
Test status
Simulation time 3190608084 ps
CPU time 78.18 seconds
Started Sep 04 02:51:43 PM UTC 24
Finished Sep 04 02:53:03 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500975268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1500975268
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/38.alert_handler_smoke.1997893626
Short name T569
Test name
Test status
Simulation time 574570197 ps
CPU time 51 seconds
Started Sep 04 02:50:50 PM UTC 24
Finished Sep 04 02:51:43 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997893626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1997893626
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/38.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all.1813053618
Short name T579
Test name
Test status
Simulation time 954625082 ps
CPU time 37.49 seconds
Started Sep 04 02:53:15 PM UTC 24
Finished Sep 04 02:53:54 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813053618 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all.1813053618
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/38.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/39.alert_handler_entropy.1258745261
Short name T706
Test name
Test status
Simulation time 229943292333 ps
CPU time 3074.39 seconds
Started Sep 04 02:54:26 PM UTC 24
Finished Sep 04 03:46:15 PM UTC 24
Peak memory 302556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258745261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1258745261
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/39.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_alert_accum.1842749066
Short name T587
Test name
Test status
Simulation time 4197515698 ps
CPU time 132.44 seconds
Started Sep 04 02:53:53 PM UTC 24
Finished Sep 04 02:56:08 PM UTC 24
Peak memory 269100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842749066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1842749066
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/39.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_intr_timeout.3298830847
Short name T582
Test name
Test status
Simulation time 269050118 ps
CPU time 42.02 seconds
Started Sep 04 02:53:46 PM UTC 24
Finished Sep 04 02:54:30 PM UTC 24
Peak memory 263328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298830847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3298830847
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg.3842291774
Short name T378
Test name
Test status
Simulation time 9439799065 ps
CPU time 889.86 seconds
Started Sep 04 02:54:31 PM UTC 24
Finished Sep 04 03:09:32 PM UTC 24
Peak memory 285764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842291774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3842291774
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/39.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg_stub_clk.2396809042
Short name T626
Test name
Test status
Simulation time 8985749110 ps
CPU time 799.24 seconds
Started Sep 04 02:54:36 PM UTC 24
Finished Sep 04 03:08:06 PM UTC 24
Peak memory 285832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396809042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2396809042
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_alerts.4111599552
Short name T581
Test name
Test status
Simulation time 495927413 ps
CPU time 43.96 seconds
Started Sep 04 02:53:40 PM UTC 24
Finished Sep 04 02:54:26 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111599552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.4111599552
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/39.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_classes.3806409831
Short name T580
Test name
Test status
Simulation time 1300167480 ps
CPU time 40.58 seconds
Started Sep 04 02:53:43 PM UTC 24
Finished Sep 04 02:54:25 PM UTC 24
Peak memory 263004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806409831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3806409831
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/39.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/39.alert_handler_sig_int_fail.1385099898
Short name T584
Test name
Test status
Simulation time 588523290 ps
CPU time 42.99 seconds
Started Sep 04 02:53:55 PM UTC 24
Finished Sep 04 02:54:40 PM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385099898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1385099898
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/39.alert_handler_smoke.3900691263
Short name T577
Test name
Test status
Simulation time 323519176 ps
CPU time 25.65 seconds
Started Sep 04 02:53:26 PM UTC 24
Finished Sep 04 02:53:53 PM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900691263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3900691263
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/39.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all_with_rand_reset.3496318808
Short name T260
Test name
Test status
Simulation time 1702868312 ps
CPU time 132.33 seconds
Started Sep 04 02:55:16 PM UTC 24
Finished Sep 04 02:57:31 PM UTC 24
Peak memory 279740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3496318808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.a
lert_handler_stress_all_with_rand_reset.3496318808
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/4.alert_handler_alert_accum_saturation.1035173034
Short name T63
Test name
Test status
Simulation time 31459982 ps
CPU time 5.2 seconds
Started Sep 04 01:41:44 PM UTC 24
Finished Sep 04 01:41:50 PM UTC 24
Peak memory 263436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035173034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1035173034
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy.1829240591
Short name T483
Test name
Test status
Simulation time 618966073733 ps
CPU time 2821.07 seconds
Started Sep 04 01:41:19 PM UTC 24
Finished Sep 04 02:28:52 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829240591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1829240591
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy_stress.1811753008
Short name T19
Test name
Test status
Simulation time 1653922476 ps
CPU time 38.07 seconds
Started Sep 04 01:41:28 PM UTC 24
Finished Sep 04 01:42:07 PM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811753008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1811753008
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_alert_accum.4099935923
Short name T48
Test name
Test status
Simulation time 4768747238 ps
CPU time 127.71 seconds
Started Sep 04 01:41:17 PM UTC 24
Finished Sep 04 01:43:27 PM UTC 24
Peak memory 265112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099935923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.4099935923
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_intr_timeout.2847687407
Short name T64
Test name
Test status
Simulation time 384189261 ps
CPU time 38.15 seconds
Started Sep 04 01:41:14 PM UTC 24
Finished Sep 04 01:41:54 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847687407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2847687407
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg.1849926099
Short name T111
Test name
Test status
Simulation time 97059438159 ps
CPU time 1446.06 seconds
Started Sep 04 01:41:22 PM UTC 24
Finished Sep 04 02:05:44 PM UTC 24
Peak memory 285828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849926099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1849926099
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg_stub_clk.2982917440
Short name T116
Test name
Test status
Simulation time 68802216513 ps
CPU time 2117.23 seconds
Started Sep 04 01:41:26 PM UTC 24
Finished Sep 04 02:17:07 PM UTC 24
Peak memory 301956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982917440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2982917440
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_classes.1383663132
Short name T141
Test name
Test status
Simulation time 335592429 ps
CPU time 9.04 seconds
Started Sep 04 01:41:08 PM UTC 24
Finished Sep 04 01:41:18 PM UTC 24
Peak memory 265244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383663132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1383663132
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/4.alert_handler_sec_cm.22825071
Short name T41
Test name
Test status
Simulation time 709367167 ps
CPU time 30.75 seconds
Started Sep 04 01:41:51 PM UTC 24
Finished Sep 04 01:42:23 PM UTC 24
Peak memory 295468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22825071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_ha
ndler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.22825071
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/4.alert_handler_sig_int_fail.3747787986
Short name T36
Test name
Test status
Simulation time 9110462292 ps
CPU time 88.3 seconds
Started Sep 04 01:41:18 PM UTC 24
Finished Sep 04 01:42:48 PM UTC 24
Peak memory 263328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747787986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3747787986
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/4.alert_handler_smoke.1032344120
Short name T140
Test name
Test status
Simulation time 263880692 ps
CPU time 13.21 seconds
Started Sep 04 01:41:03 PM UTC 24
Finished Sep 04 01:41:17 PM UTC 24
Peak memory 267068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032344120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1032344120
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all.3910065223
Short name T103
Test name
Test status
Simulation time 207895443312 ps
CPU time 1684.97 seconds
Started Sep 04 01:41:28 PM UTC 24
Finished Sep 04 02:09:53 PM UTC 24
Peak memory 301948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910065223 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all.3910065223
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/4.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/40.alert_handler_entropy.2143077253
Short name T684
Test name
Test status
Simulation time 33379450727 ps
CPU time 1679.03 seconds
Started Sep 04 02:56:20 PM UTC 24
Finished Sep 04 03:24:39 PM UTC 24
Peak memory 302080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143077253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2143077253
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/40.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_alert_accum.500442118
Short name T593
Test name
Test status
Simulation time 2492202030 ps
CPU time 197.61 seconds
Started Sep 04 02:56:09 PM UTC 24
Finished Sep 04 02:59:30 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500442118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.500442118
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/40.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_intr_timeout.3243269848
Short name T589
Test name
Test status
Simulation time 370327184 ps
CPU time 18.97 seconds
Started Sep 04 02:56:08 PM UTC 24
Finished Sep 04 02:56:28 PM UTC 24
Peak memory 267032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243269848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3243269848
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg.228081979
Short name T682
Test name
Test status
Simulation time 43936631793 ps
CPU time 1602.23 seconds
Started Sep 04 02:56:29 PM UTC 24
Finished Sep 04 03:23:31 PM UTC 24
Peak memory 285828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228081979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.228081979
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/40.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg_stub_clk.2938862442
Short name T704
Test name
Test status
Simulation time 100260550917 ps
CPU time 2607.49 seconds
Started Sep 04 02:56:58 PM UTC 24
Finished Sep 04 03:40:54 PM UTC 24
Peak memory 298540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938862442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2938862442
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/40.alert_handler_ping_timeout.3052662468
Short name T617
Test name
Test status
Simulation time 25141719017 ps
CPU time 588 seconds
Started Sep 04 02:56:25 PM UTC 24
Finished Sep 04 03:06:21 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052662468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3052662468
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_alerts.2997833237
Short name T586
Test name
Test status
Simulation time 172651533 ps
CPU time 16.67 seconds
Started Sep 04 02:55:50 PM UTC 24
Finished Sep 04 02:56:08 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997833237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2997833237
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/40.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_classes.1194682391
Short name T588
Test name
Test status
Simulation time 1355940278 ps
CPU time 26.96 seconds
Started Sep 04 02:55:56 PM UTC 24
Finished Sep 04 02:56:24 PM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194682391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1194682391
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/40.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/40.alert_handler_smoke.2636452795
Short name T578
Test name
Test status
Simulation time 52219896 ps
CPU time 4.17 seconds
Started Sep 04 02:55:50 PM UTC 24
Finished Sep 04 02:55:55 PM UTC 24
Peak memory 263232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636452795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2636452795
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/40.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all.798479005
Short name T131
Test name
Test status
Simulation time 202862557636 ps
CPU time 1382.63 seconds
Started Sep 04 02:57:29 PM UTC 24
Finished Sep 04 03:20:49 PM UTC 24
Peak memory 302268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798479005 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all.798479005
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/40.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/41.alert_handler_entropy.1745961251
Short name T655
Test name
Test status
Simulation time 54806795040 ps
CPU time 899.19 seconds
Started Sep 04 02:59:40 PM UTC 24
Finished Sep 04 03:14:50 PM UTC 24
Peak memory 285492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745961251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1745961251
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/41.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_alert_accum.1685446912
Short name T600
Test name
Test status
Simulation time 2170572798 ps
CPU time 135.89 seconds
Started Sep 04 02:59:31 PM UTC 24
Finished Sep 04 03:01:50 PM UTC 24
Peak memory 269308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685446912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1685446912
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/41.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_intr_timeout.3119070498
Short name T595
Test name
Test status
Simulation time 1420149275 ps
CPU time 43.24 seconds
Started Sep 04 02:59:04 PM UTC 24
Finished Sep 04 02:59:49 PM UTC 24
Peak memory 263136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119070498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3119070498
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg_stub_clk.2559598535
Short name T312
Test name
Test status
Simulation time 14599364003 ps
CPU time 1324.19 seconds
Started Sep 04 03:00:17 PM UTC 24
Finished Sep 04 03:22:37 PM UTC 24
Peak memory 299836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559598535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2559598535
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_alerts.1640554883
Short name T596
Test name
Test status
Simulation time 5348166304 ps
CPU time 96.65 seconds
Started Sep 04 02:58:36 PM UTC 24
Finished Sep 04 03:00:15 PM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1640554883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1640554883
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/41.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_classes.1961093016
Short name T313
Test name
Test status
Simulation time 736011008 ps
CPU time 46.89 seconds
Started Sep 04 02:58:50 PM UTC 24
Finished Sep 04 02:59:38 PM UTC 24
Peak memory 262932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961093016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1961093016
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/41.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/41.alert_handler_sig_int_fail.3045373896
Short name T275
Test name
Test status
Simulation time 752180214 ps
CPU time 61 seconds
Started Sep 04 02:59:40 PM UTC 24
Finished Sep 04 03:00:42 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045373896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3045373896
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/41.alert_handler_smoke.4254144921
Short name T592
Test name
Test status
Simulation time 965984817 ps
CPU time 73.08 seconds
Started Sep 04 02:57:34 PM UTC 24
Finished Sep 04 02:58:49 PM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254144921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.4254144921
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/41.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all.3575244058
Short name T328
Test name
Test status
Simulation time 346721393198 ps
CPU time 4790.68 seconds
Started Sep 04 03:00:35 PM UTC 24
Finished Sep 04 04:21:20 PM UTC 24
Peak memory 321312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575244058 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all.3575244058
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/41.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/42.alert_handler_entropy.247000374
Short name T693
Test name
Test status
Simulation time 25918658451 ps
CPU time 1594.58 seconds
Started Sep 04 03:01:52 PM UTC 24
Finished Sep 04 03:28:46 PM UTC 24
Peak memory 302212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247000374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.247000374
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/42.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_alert_accum.167855935
Short name T613
Test name
Test status
Simulation time 3975079827 ps
CPU time 199.58 seconds
Started Sep 04 03:01:41 PM UTC 24
Finished Sep 04 03:05:04 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167855935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.167855935
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/42.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_intr_timeout.3588203456
Short name T601
Test name
Test status
Simulation time 228601401 ps
CPU time 32.39 seconds
Started Sep 04 03:01:23 PM UTC 24
Finished Sep 04 03:01:56 PM UTC 24
Peak memory 263264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588203456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3588203456
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg.1429268170
Short name T707
Test name
Test status
Simulation time 204366214518 ps
CPU time 2686.67 seconds
Started Sep 04 03:02:22 PM UTC 24
Finished Sep 04 03:47:39 PM UTC 24
Peak memory 298536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429268170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1429268170
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/42.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg_stub_clk.2705901601
Short name T672
Test name
Test status
Simulation time 7452352698 ps
CPU time 881.92 seconds
Started Sep 04 03:02:27 PM UTC 24
Finished Sep 04 03:17:20 PM UTC 24
Peak memory 285500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705901601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2705901601
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_alerts.2881113838
Short name T603
Test name
Test status
Simulation time 10533143558 ps
CPU time 93.24 seconds
Started Sep 04 03:00:54 PM UTC 24
Finished Sep 04 03:02:30 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881113838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2881113838
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/42.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_classes.1261594599
Short name T599
Test name
Test status
Simulation time 195338885 ps
CPU time 23.95 seconds
Started Sep 04 03:00:56 PM UTC 24
Finished Sep 04 03:01:22 PM UTC 24
Peak memory 263260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261594599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1261594599
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/42.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/42.alert_handler_sig_int_fail.3179220441
Short name T604
Test name
Test status
Simulation time 2477726198 ps
CPU time 51.45 seconds
Started Sep 04 03:01:51 PM UTC 24
Finished Sep 04 03:02:44 PM UTC 24
Peak memory 263036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179220441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3179220441
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/42.alert_handler_smoke.2620402844
Short name T602
Test name
Test status
Simulation time 1108986652 ps
CPU time 90.4 seconds
Started Sep 04 03:00:53 PM UTC 24
Finished Sep 04 03:02:26 PM UTC 24
Peak memory 269376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620402844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2620402844
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/42.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all.1409170646
Short name T712
Test name
Test status
Simulation time 49201004121 ps
CPU time 3370.07 seconds
Started Sep 04 03:02:31 PM UTC 24
Finished Sep 04 03:59:19 PM UTC 24
Peak memory 314840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409170646 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all.1409170646
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/42.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all_with_rand_reset.1672666582
Short name T632
Test name
Test status
Simulation time 13697478233 ps
CPU time 412.09 seconds
Started Sep 04 03:02:45 PM UTC 24
Finished Sep 04 03:09:43 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1672666582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.a
lert_handler_stress_all_with_rand_reset.1672666582
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/43.alert_handler_entropy.2523741079
Short name T669
Test name
Test status
Simulation time 52082975315 ps
CPU time 749.29 seconds
Started Sep 04 03:04:28 PM UTC 24
Finished Sep 04 03:17:07 PM UTC 24
Peak memory 285824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523741079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2523741079
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/43.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_alert_accum.186774113
Short name T611
Test name
Test status
Simulation time 499947914 ps
CPU time 29.44 seconds
Started Sep 04 03:04:12 PM UTC 24
Finished Sep 04 03:04:42 PM UTC 24
Peak memory 269404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186774113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.186774113
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/43.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_intr_timeout.2325463943
Short name T608
Test name
Test status
Simulation time 138496459 ps
CPU time 5.82 seconds
Started Sep 04 03:04:06 PM UTC 24
Finished Sep 04 03:04:12 PM UTC 24
Peak memory 252696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325463943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2325463943
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg.1782106778
Short name T674
Test name
Test status
Simulation time 18617332169 ps
CPU time 871.22 seconds
Started Sep 04 03:04:37 PM UTC 24
Finished Sep 04 03:19:20 PM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782106778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1782106778
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/43.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg_stub_clk.1342041403
Short name T703
Test name
Test status
Simulation time 32990055947 ps
CPU time 2060.28 seconds
Started Sep 04 03:04:43 PM UTC 24
Finished Sep 04 03:39:27 PM UTC 24
Peak memory 285580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342041403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1342041403
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/43.alert_handler_ping_timeout.3360387170
Short name T325
Test name
Test status
Simulation time 56380297303 ps
CPU time 437.63 seconds
Started Sep 04 03:04:30 PM UTC 24
Finished Sep 04 03:11:53 PM UTC 24
Peak memory 263304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360387170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3360387170
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_alerts.1959065368
Short name T607
Test name
Test status
Simulation time 1121036190 ps
CPU time 39.62 seconds
Started Sep 04 03:03:23 PM UTC 24
Finished Sep 04 03:04:04 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959065368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1959065368
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/43.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_classes.1529972674
Short name T609
Test name
Test status
Simulation time 1956599887 ps
CPU time 33.63 seconds
Started Sep 04 03:03:52 PM UTC 24
Finished Sep 04 03:04:27 PM UTC 24
Peak memory 262932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529972674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1529972674
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/43.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/43.alert_handler_sig_int_fail.2850418459
Short name T612
Test name
Test status
Simulation time 481823063 ps
CPU time 29.8 seconds
Started Sep 04 03:04:14 PM UTC 24
Finished Sep 04 03:04:45 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850418459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2850418459
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/43.alert_handler_smoke.4218200363
Short name T606
Test name
Test status
Simulation time 1028535448 ps
CPU time 27.25 seconds
Started Sep 04 03:02:54 PM UTC 24
Finished Sep 04 03:03:23 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218200363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.4218200363
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/43.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all.2089738388
Short name T278
Test name
Test status
Simulation time 9429943891 ps
CPU time 163.69 seconds
Started Sep 04 03:04:45 PM UTC 24
Finished Sep 04 03:07:32 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089738388 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all.2089738388
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/43.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/44.alert_handler_entropy.1180370616
Short name T696
Test name
Test status
Simulation time 10328257565 ps
CPU time 1437.07 seconds
Started Sep 04 03:06:35 PM UTC 24
Finished Sep 04 03:30:51 PM UTC 24
Peak memory 301952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180370616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1180370616
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/44.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_alert_accum.1250911890
Short name T627
Test name
Test status
Simulation time 5664218684 ps
CPU time 115.2 seconds
Started Sep 04 03:06:23 PM UTC 24
Finished Sep 04 03:08:21 PM UTC 24
Peak memory 269176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250911890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1250911890
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/44.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_intr_timeout.1945362002
Short name T619
Test name
Test status
Simulation time 185711907 ps
CPU time 7.29 seconds
Started Sep 04 03:06:22 PM UTC 24
Finished Sep 04 03:06:30 PM UTC 24
Peak memory 263328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945362002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1945362002
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg.2485350623
Short name T375
Test name
Test status
Simulation time 36800596116 ps
CPU time 2177.37 seconds
Started Sep 04 03:06:57 PM UTC 24
Finished Sep 04 03:43:40 PM UTC 24
Peak memory 304604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485350623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2485350623
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/44.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg_stub_clk.1974089276
Short name T679
Test name
Test status
Simulation time 7879198789 ps
CPU time 888.12 seconds
Started Sep 04 03:07:11 PM UTC 24
Finished Sep 04 03:22:11 PM UTC 24
Peak memory 285504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974089276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1974089276
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/44.alert_handler_ping_timeout.3953547324
Short name T670
Test name
Test status
Simulation time 16080629267 ps
CPU time 611.53 seconds
Started Sep 04 03:06:49 PM UTC 24
Finished Sep 04 03:17:07 PM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3953547324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3953547324
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_alerts.3040648719
Short name T618
Test name
Test status
Simulation time 685817721 ps
CPU time 43.03 seconds
Started Sep 04 03:05:38 PM UTC 24
Finished Sep 04 03:06:22 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040648719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3040648719
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/44.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_classes.2195120776
Short name T620
Test name
Test status
Simulation time 250687703 ps
CPU time 37.04 seconds
Started Sep 04 03:05:56 PM UTC 24
Finished Sep 04 03:06:34 PM UTC 24
Peak memory 269076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195120776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2195120776
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/44.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/44.alert_handler_sig_int_fail.534615975
Short name T622
Test name
Test status
Simulation time 1456799977 ps
CPU time 37.59 seconds
Started Sep 04 03:06:31 PM UTC 24
Finished Sep 04 03:07:10 PM UTC 24
Peak memory 269152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534615975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.534615975
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/44.alert_handler_smoke.1398379258
Short name T616
Test name
Test status
Simulation time 836424541 ps
CPU time 34.25 seconds
Started Sep 04 03:05:19 PM UTC 24
Finished Sep 04 03:05:55 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398379258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1398379258
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/44.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/45.alert_handler_entropy.3028440209
Short name T710
Test name
Test status
Simulation time 97029384042 ps
CPU time 2729.3 seconds
Started Sep 04 03:08:22 PM UTC 24
Finished Sep 04 03:54:22 PM UTC 24
Peak memory 302552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028440209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3028440209
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/45.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_alert_accum.3725594017
Short name T654
Test name
Test status
Simulation time 5175369884 ps
CPU time 407.23 seconds
Started Sep 04 03:07:57 PM UTC 24
Finished Sep 04 03:14:50 PM UTC 24
Peak memory 267060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725594017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3725594017
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/45.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_intr_timeout.1786506335
Short name T628
Test name
Test status
Simulation time 348937493 ps
CPU time 29.42 seconds
Started Sep 04 03:07:54 PM UTC 24
Finished Sep 04 03:08:24 PM UTC 24
Peak memory 262936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786506335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1786506335
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg.3206024391
Short name T702
Test name
Test status
Simulation time 123331988098 ps
CPU time 1669.05 seconds
Started Sep 04 03:08:49 PM UTC 24
Finished Sep 04 03:36:57 PM UTC 24
Peak memory 285892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206024391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3206024391
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/45.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg_stub_clk.1585117678
Short name T698
Test name
Test status
Simulation time 14527522974 ps
CPU time 1458.5 seconds
Started Sep 04 03:08:52 PM UTC 24
Finished Sep 04 03:33:29 PM UTC 24
Peak memory 302280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585117678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1585117678
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/45.alert_handler_ping_timeout.1710746047
Short name T639
Test name
Test status
Simulation time 10966037338 ps
CPU time 162.23 seconds
Started Sep 04 03:08:25 PM UTC 24
Finished Sep 04 03:11:10 PM UTC 24
Peak memory 263048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710746047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1710746047
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_alerts.4260047281
Short name T629
Test name
Test status
Simulation time 1275895640 ps
CPU time 58.68 seconds
Started Sep 04 03:07:48 PM UTC 24
Finished Sep 04 03:08:49 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260047281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.4260047281
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/45.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_classes.3449286788
Short name T625
Test name
Test status
Simulation time 55159915 ps
CPU time 6.57 seconds
Started Sep 04 03:07:48 PM UTC 24
Finished Sep 04 03:07:56 PM UTC 24
Peak memory 252672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449286788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3449286788
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/45.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/45.alert_handler_sig_int_fail.3927801749
Short name T631
Test name
Test status
Simulation time 3219183783 ps
CPU time 67.97 seconds
Started Sep 04 03:08:08 PM UTC 24
Finished Sep 04 03:09:17 PM UTC 24
Peak memory 263356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927801749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3927801749
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/45.alert_handler_smoke.971245961
Short name T597
Test name
Test status
Simulation time 7234437555 ps
CPU time 63.96 seconds
Started Sep 04 03:07:46 PM UTC 24
Finished Sep 04 03:08:51 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971245961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.971245961
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/45.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all_with_rand_reset.3683356634
Short name T650
Test name
Test status
Simulation time 1824947049 ps
CPU time 277.74 seconds
Started Sep 04 03:09:17 PM UTC 24
Finished Sep 04 03:13:59 PM UTC 24
Peak memory 279676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3683356634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.a
lert_handler_stress_all_with_rand_reset.3683356634
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/46.alert_handler_entropy.1452437257
Short name T695
Test name
Test status
Simulation time 45520577290 ps
CPU time 1220.73 seconds
Started Sep 04 03:09:50 PM UTC 24
Finished Sep 04 03:30:26 PM UTC 24
Peak memory 301952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452437257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1452437257
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/46.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_alert_accum.2427576398
Short name T647
Test name
Test status
Simulation time 17072207476 ps
CPU time 185.69 seconds
Started Sep 04 03:09:45 PM UTC 24
Finished Sep 04 03:12:53 PM UTC 24
Peak memory 269432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427576398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2427576398
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/46.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_intr_timeout.4081080028
Short name T634
Test name
Test status
Simulation time 171256410 ps
CPU time 4.17 seconds
Started Sep 04 03:09:44 PM UTC 24
Finished Sep 04 03:09:50 PM UTC 24
Peak memory 263264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081080028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.4081080028
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg.1021329065
Short name T700
Test name
Test status
Simulation time 91392085475 ps
CPU time 1552.27 seconds
Started Sep 04 03:09:59 PM UTC 24
Finished Sep 04 03:36:10 PM UTC 24
Peak memory 285892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021329065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1021329065
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/46.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg_stub_clk.2041798759
Short name T709
Test name
Test status
Simulation time 374385237736 ps
CPU time 2543.35 seconds
Started Sep 04 03:10:10 PM UTC 24
Finished Sep 04 03:53:02 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041798759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2041798759
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/46.alert_handler_ping_timeout.852150259
Short name T673
Test name
Test status
Simulation time 11653076104 ps
CPU time 504.12 seconds
Started Sep 04 03:09:57 PM UTC 24
Finished Sep 04 03:18:28 PM UTC 24
Peak memory 269384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852150259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.852150259
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_alerts.2662459026
Short name T636
Test name
Test status
Simulation time 334780139 ps
CPU time 33.21 seconds
Started Sep 04 03:09:23 PM UTC 24
Finished Sep 04 03:09:57 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662459026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2662459026
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/46.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_classes.2534916936
Short name T637
Test name
Test status
Simulation time 2112306848 ps
CPU time 32.98 seconds
Started Sep 04 03:09:34 PM UTC 24
Finished Sep 04 03:10:08 PM UTC 24
Peak memory 269084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534916936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2534916936
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/46.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/46.alert_handler_smoke.3914013975
Short name T635
Test name
Test status
Simulation time 1459608988 ps
CPU time 37.62 seconds
Started Sep 04 03:09:18 PM UTC 24
Finished Sep 04 03:09:57 PM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914013975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3914013975
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/46.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/47.alert_handler_entropy.637597866
Short name T109
Test name
Test status
Simulation time 41963127285 ps
CPU time 2399.36 seconds
Started Sep 04 03:11:53 PM UTC 24
Finished Sep 04 03:52:19 PM UTC 24
Peak memory 298460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637597866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/
alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.637597866
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/47.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_alert_accum.2217149350
Short name T649
Test name
Test status
Simulation time 2857135370 ps
CPU time 131.09 seconds
Started Sep 04 03:11:39 PM UTC 24
Finished Sep 04 03:13:53 PM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217149350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2217149350
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/47.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_intr_timeout.1076340086
Short name T644
Test name
Test status
Simulation time 604549509 ps
CPU time 19.37 seconds
Started Sep 04 03:11:34 PM UTC 24
Finished Sep 04 03:11:55 PM UTC 24
Peak memory 262924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076340086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1076340086
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg.1086490781
Short name T705
Test name
Test status
Simulation time 51798634012 ps
CPU time 1721.27 seconds
Started Sep 04 03:12:10 PM UTC 24
Finished Sep 04 03:41:11 PM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086490781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1086490781
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/47.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg_stub_clk.3527418617
Short name T713
Test name
Test status
Simulation time 156511417257 ps
CPU time 2815.88 seconds
Started Sep 04 03:12:13 PM UTC 24
Finished Sep 04 03:59:42 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527418617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3527418617
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/47.alert_handler_ping_timeout.3560617682
Short name T685
Test name
Test status
Simulation time 14044110058 ps
CPU time 788 seconds
Started Sep 04 03:11:56 PM UTC 24
Finished Sep 04 03:25:14 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560617682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3560617682
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_alerts.746271880
Short name T640
Test name
Test status
Simulation time 126563836 ps
CPU time 15.15 seconds
Started Sep 04 03:11:11 PM UTC 24
Finished Sep 04 03:11:27 PM UTC 24
Peak memory 269156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746271880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.746271880
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/47.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_classes.122177172
Short name T645
Test name
Test status
Simulation time 486172113 ps
CPU time 39.02 seconds
Started Sep 04 03:11:28 PM UTC 24
Finished Sep 04 03:12:09 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122177172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.122177172
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/47.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/47.alert_handler_sig_int_fail.3465559178
Short name T646
Test name
Test status
Simulation time 289370246 ps
CPU time 25.65 seconds
Started Sep 04 03:11:45 PM UTC 24
Finished Sep 04 03:12:12 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465559178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3465559178
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/47.alert_handler_smoke.1398684005
Short name T643
Test name
Test status
Simulation time 300324432 ps
CPU time 32.05 seconds
Started Sep 04 03:11:11 PM UTC 24
Finished Sep 04 03:11:44 PM UTC 24
Peak memory 269120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398684005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1398684005
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/47.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all_with_rand_reset.3535498629
Short name T664
Test name
Test status
Simulation time 27977674275 ps
CPU time 186.46 seconds
Started Sep 04 03:12:54 PM UTC 24
Finished Sep 04 03:16:04 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3535498629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.a
lert_handler_stress_all_with_rand_reset.3535498629
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/48.alert_handler_entropy.1665427825
Short name T701
Test name
Test status
Simulation time 19878446420 ps
CPU time 1288.1 seconds
Started Sep 04 03:14:37 PM UTC 24
Finished Sep 04 03:36:21 PM UTC 24
Peak memory 283448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665427825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1665427825
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/48.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_alert_accum.4149736415
Short name T668
Test name
Test status
Simulation time 2061483916 ps
CPU time 129.89 seconds
Started Sep 04 03:14:19 PM UTC 24
Finished Sep 04 03:16:31 PM UTC 24
Peak memory 269368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149736415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.4149736415
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/48.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_intr_timeout.2345410705
Short name T653
Test name
Test status
Simulation time 1154226703 ps
CPU time 24.46 seconds
Started Sep 04 03:14:11 PM UTC 24
Finished Sep 04 03:14:36 PM UTC 24
Peak memory 263328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345410705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2345410705
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg.691217554
Short name T690
Test name
Test status
Simulation time 15688171036 ps
CPU time 681.97 seconds
Started Sep 04 03:14:52 PM UTC 24
Finished Sep 04 03:26:22 PM UTC 24
Peak memory 285824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691217554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.691217554
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/48.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg_stub_clk.224645284
Short name T691
Test name
Test status
Simulation time 6024112837 ps
CPU time 693.93 seconds
Started Sep 04 03:14:56 PM UTC 24
Finished Sep 04 03:26:38 PM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224645284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.224645284
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/48.alert_handler_ping_timeout.2325376894
Short name T692
Test name
Test status
Simulation time 27278541932 ps
CPU time 820.43 seconds
Started Sep 04 03:14:52 PM UTC 24
Finished Sep 04 03:28:43 PM UTC 24
Peak memory 263304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325376894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2325376894
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_alerts.611110402
Short name T652
Test name
Test status
Simulation time 895185504 ps
CPU time 36.56 seconds
Started Sep 04 03:13:53 PM UTC 24
Finished Sep 04 03:14:31 PM UTC 24
Peak memory 269084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611110402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.611110402
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/48.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_classes.3243207278
Short name T658
Test name
Test status
Simulation time 3532133080 ps
CPU time 61.11 seconds
Started Sep 04 03:14:00 PM UTC 24
Finished Sep 04 03:15:03 PM UTC 24
Peak memory 263000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243207278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3243207278
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/48.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/48.alert_handler_sig_int_fail.2515483689
Short name T659
Test name
Test status
Simulation time 2808069255 ps
CPU time 32.95 seconds
Started Sep 04 03:14:32 PM UTC 24
Finished Sep 04 03:15:07 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515483689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2515483689
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/48.alert_handler_smoke.414555989
Short name T651
Test name
Test status
Simulation time 2099807480 ps
CPU time 40.39 seconds
Started Sep 04 03:13:28 PM UTC 24
Finished Sep 04 03:14:10 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414555989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.414555989
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/48.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/49.alert_handler_entropy.2666207719
Short name T699
Test name
Test status
Simulation time 46280485421 ps
CPU time 1189.61 seconds
Started Sep 04 03:16:05 PM UTC 24
Finished Sep 04 03:36:09 PM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666207719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2666207719
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/49.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_alert_accum.3960416682
Short name T667
Test name
Test status
Simulation time 1212891464 ps
CPU time 29.08 seconds
Started Sep 04 03:15:58 PM UTC 24
Finished Sep 04 03:16:29 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960416682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3960416682
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/49.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_intr_timeout.615253687
Short name T665
Test name
Test status
Simulation time 2159833171 ps
CPU time 35.3 seconds
Started Sep 04 03:15:27 PM UTC 24
Finished Sep 04 03:16:04 PM UTC 24
Peak memory 269112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615253687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es
c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.615253687
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg.2591681921
Short name T714
Test name
Test status
Simulation time 206686876857 ps
CPU time 2847.33 seconds
Started Sep 04 03:16:30 PM UTC 24
Finished Sep 04 04:04:32 PM UTC 24
Peak memory 300512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591681921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2591681921
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/49.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg_stub_clk.947281617
Short name T711
Test name
Test status
Simulation time 39896332921 ps
CPU time 2448.99 seconds
Started Sep 04 03:16:32 PM UTC 24
Finished Sep 04 03:57:49 PM UTC 24
Peak memory 304608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947281617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.947281617
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/49.alert_handler_ping_timeout.92635398
Short name T688
Test name
Test status
Simulation time 31628110030 ps
CPU time 578.88 seconds
Started Sep 04 03:16:19 PM UTC 24
Finished Sep 04 03:26:05 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92635398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.92635398
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_alerts.3698369266
Short name T663
Test name
Test status
Simulation time 559316977 ps
CPU time 46.63 seconds
Started Sep 04 03:15:09 PM UTC 24
Finished Sep 04 03:15:57 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698369266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3698369266
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/49.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_classes.2153033109
Short name T662
Test name
Test status
Simulation time 439753831 ps
CPU time 5.39 seconds
Started Sep 04 03:15:20 PM UTC 24
Finished Sep 04 03:15:27 PM UTC 24
Peak memory 252660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153033109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2153033109
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/49.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/49.alert_handler_sig_int_fail.2693772461
Short name T666
Test name
Test status
Simulation time 252172106 ps
CPU time 11.74 seconds
Started Sep 04 03:16:05 PM UTC 24
Finished Sep 04 03:16:18 PM UTC 24
Peak memory 264948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693772461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2693772461
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/49.alert_handler_smoke.725283152
Short name T661
Test name
Test status
Simulation time 96021333 ps
CPU time 9.49 seconds
Started Sep 04 03:15:09 PM UTC 24
Finished Sep 04 03:15:20 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725283152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm
oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.725283152
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/49.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all.282190240
Short name T291
Test name
Test status
Simulation time 47558652573 ps
CPU time 2875.17 seconds
Started Sep 04 03:17:08 PM UTC 24
Finished Sep 04 04:05:36 PM UTC 24
Peak memory 304532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282190240 -assert nopostproc +UVM_TE
STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all.282190240
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/49.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all_with_rand_reset.1721156480
Short name T132
Test name
Test status
Simulation time 2984326779 ps
CPU time 296.68 seconds
Started Sep 04 03:17:08 PM UTC 24
Finished Sep 04 03:22:10 PM UTC 24
Peak memory 279740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1721156480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.a
lert_handler_stress_all_with_rand_reset.1721156480
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/5.alert_handler_alert_accum_saturation.47719830
Short name T69
Test name
Test status
Simulation time 48418740 ps
CPU time 6.17 seconds
Started Sep 04 01:42:50 PM UTC 24
Finished Sep 04 01:42:57 PM UTC 24
Peak memory 263164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47719830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_h
andler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.47719830
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy_stress.1599461430
Short name T20
Test name
Test status
Simulation time 916303604 ps
CPU time 38.14 seconds
Started Sep 04 01:42:45 PM UTC 24
Finished Sep 04 01:43:24 PM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599461430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1599461430
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_alert_accum.4193502136
Short name T336
Test name
Test status
Simulation time 2409623502 ps
CPU time 94.63 seconds
Started Sep 04 01:42:24 PM UTC 24
Finished Sep 04 01:44:00 PM UTC 24
Peak memory 269140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193502136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.4193502136
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_intr_timeout.2131673036
Short name T87
Test name
Test status
Simulation time 2604062904 ps
CPU time 37.5 seconds
Started Sep 04 01:42:20 PM UTC 24
Finished Sep 04 01:42:58 PM UTC 24
Peak memory 263292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131673036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2131673036
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg.423441514
Short name T329
Test name
Test status
Simulation time 7721102142 ps
CPU time 624.91 seconds
Started Sep 04 01:42:29 PM UTC 24
Finished Sep 04 01:53:02 PM UTC 24
Peak memory 285764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423441514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.423441514
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg_stub_clk.544631896
Short name T363
Test name
Test status
Simulation time 60286190183 ps
CPU time 1654.14 seconds
Started Sep 04 01:42:42 PM UTC 24
Finished Sep 04 02:10:36 PM UTC 24
Peak memory 296068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544631896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.544631896
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/5.alert_handler_ping_timeout.904024363
Short name T338
Test name
Test status
Simulation time 9383661679 ps
CPU time 299.16 seconds
Started Sep 04 01:42:27 PM UTC 24
Finished Sep 04 01:47:30 PM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904024363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.904024363
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_alerts.1872793162
Short name T107
Test name
Test status
Simulation time 3775222804 ps
CPU time 59.02 seconds
Started Sep 04 01:42:08 PM UTC 24
Finished Sep 04 01:43:09 PM UTC 24
Peak memory 269128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872793162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1872793162
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_classes.1744738219
Short name T66
Test name
Test status
Simulation time 468382411 ps
CPU time 31.97 seconds
Started Sep 04 01:42:08 PM UTC 24
Finished Sep 04 01:42:42 PM UTC 24
Peak memory 263260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744738219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1744738219
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/5.alert_handler_sig_int_fail.4016406904
Short name T67
Test name
Test status
Simulation time 269188000 ps
CPU time 23 seconds
Started Sep 04 01:42:24 PM UTC 24
Finished Sep 04 01:42:48 PM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016406904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.4016406904
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/5.alert_handler_smoke.3526716934
Short name T65
Test name
Test status
Simulation time 652135175 ps
CPU time 27.1 seconds
Started Sep 04 01:41:54 PM UTC 24
Finished Sep 04 01:42:23 PM UTC 24
Peak memory 269372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526716934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3526716934
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all_with_rand_reset.817074223
Short name T53
Test name
Test status
Simulation time 21397044847 ps
CPU time 560.63 seconds
Started Sep 04 01:42:58 PM UTC 24
Finished Sep 04 01:52:27 PM UTC 24
Peak memory 283576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str
ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=817074223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.ale
rt_handler_stress_all_with_rand_reset.817074223
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/6.alert_handler_alert_accum_saturation.3057131631
Short name T241
Test name
Test status
Simulation time 22096118 ps
CPU time 4.37 seconds
Started Sep 04 01:43:48 PM UTC 24
Finished Sep 04 01:43:53 PM UTC 24
Peak memory 263172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057131631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3057131631
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy_stress.2044948646
Short name T21
Test name
Test status
Simulation time 128791326 ps
CPU time 9.89 seconds
Started Sep 04 01:43:35 PM UTC 24
Finished Sep 04 01:43:47 PM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044948646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2044948646
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_alert_accum.2965765931
Short name T405
Test name
Test status
Simulation time 5100099159 ps
CPU time 368.42 seconds
Started Sep 04 01:43:10 PM UTC 24
Finished Sep 04 01:49:23 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965765931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2965765931
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_intr_timeout.3758378342
Short name T108
Test name
Test status
Simulation time 16970916 ps
CPU time 3.52 seconds
Started Sep 04 01:43:09 PM UTC 24
Finished Sep 04 01:43:13 PM UTC 24
Peak memory 263228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758378342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3758378342
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg.4160811641
Short name T362
Test name
Test status
Simulation time 98489962298 ps
CPU time 2442.65 seconds
Started Sep 04 01:43:25 PM UTC 24
Finished Sep 04 02:24:35 PM UTC 24
Peak memory 301876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160811641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.4160811641
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg_stub_clk.3644005540
Short name T133
Test name
Test status
Simulation time 102834021133 ps
CPU time 1808.14 seconds
Started Sep 04 01:43:28 PM UTC 24
Finished Sep 04 02:13:58 PM UTC 24
Peak memory 285892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644005540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3644005540
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/6.alert_handler_ping_timeout.3708648135
Short name T343
Test name
Test status
Simulation time 15329423622 ps
CPU time 623.09 seconds
Started Sep 04 01:43:25 PM UTC 24
Finished Sep 04 01:53:55 PM UTC 24
Peak memory 263044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708648135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3708648135
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_alerts.3810708437
Short name T78
Test name
Test status
Simulation time 3261332903 ps
CPU time 51.28 seconds
Started Sep 04 01:42:59 PM UTC 24
Finished Sep 04 01:43:52 PM UTC 24
Peak memory 269476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810708437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3810708437
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_classes.3843420995
Short name T77
Test name
Test status
Simulation time 3213644055 ps
CPU time 23.83 seconds
Started Sep 04 01:42:59 PM UTC 24
Finished Sep 04 01:43:24 PM UTC 24
Peak memory 263068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843420995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3843420995
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/6.alert_handler_smoke.2618724541
Short name T79
Test name
Test status
Simulation time 870618904 ps
CPU time 65.89 seconds
Started Sep 04 01:42:58 PM UTC 24
Finished Sep 04 01:44:06 PM UTC 24
Peak memory 269116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618724541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2618724541
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all.1361573994
Short name T88
Test name
Test status
Simulation time 848271112 ps
CPU time 28.11 seconds
Started Sep 04 01:43:43 PM UTC 24
Finished Sep 04 01:44:12 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361573994 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all.1361573994
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/6.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/7.alert_handler_alert_accum_saturation.1440921893
Short name T222
Test name
Test status
Simulation time 36936784 ps
CPU time 3.87 seconds
Started Sep 04 01:44:47 PM UTC 24
Finished Sep 04 01:44:52 PM UTC 24
Peak memory 263248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440921893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1440921893
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy.4245439227
Short name T379
Test name
Test status
Simulation time 85720739168 ps
CPU time 2196.44 seconds
Started Sep 04 01:44:13 PM UTC 24
Finished Sep 04 02:21:12 PM UTC 24
Peak memory 295736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245439227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.4245439227
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy_stress.2787079937
Short name T155
Test name
Test status
Simulation time 261790273 ps
CPU time 21.71 seconds
Started Sep 04 01:44:38 PM UTC 24
Finished Sep 04 01:45:01 PM UTC 24
Peak memory 263236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787079937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2787079937
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_alert_accum.3577512430
Short name T400
Test name
Test status
Simulation time 1088572330 ps
CPU time 98.79 seconds
Started Sep 04 01:44:03 PM UTC 24
Finished Sep 04 01:45:43 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577512430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3577512430
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_intr_timeout.2571085197
Short name T80
Test name
Test status
Simulation time 813768630 ps
CPU time 20.67 seconds
Started Sep 04 01:44:01 PM UTC 24
Finished Sep 04 01:44:23 PM UTC 24
Peak memory 262900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571085197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2571085197
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg.2111386348
Short name T330
Test name
Test status
Simulation time 31281400149 ps
CPU time 766.8 seconds
Started Sep 04 01:44:24 PM UTC 24
Finished Sep 04 01:57:21 PM UTC 24
Peak memory 285824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111386348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ale
rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2111386348
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg_stub_clk.774084751
Short name T315
Test name
Test status
Simulation time 94571765909 ps
CPU time 1158.54 seconds
Started Sep 04 01:44:24 PM UTC 24
Finished Sep 04 02:03:56 PM UTC 24
Peak memory 299908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774084751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.774084751
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/7.alert_handler_ping_timeout.558852105
Short name T314
Test name
Test status
Simulation time 8613407897 ps
CPU time 498.54 seconds
Started Sep 04 01:44:17 PM UTC 24
Finished Sep 04 01:52:42 PM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558852105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.558852105
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_alerts.245969632
Short name T220
Test name
Test status
Simulation time 618448333 ps
CPU time 42.29 seconds
Started Sep 04 01:43:54 PM UTC 24
Finished Sep 04 01:44:38 PM UTC 24
Peak memory 269408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245969632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.245969632
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_classes.4193205287
Short name T221
Test name
Test status
Simulation time 455601336 ps
CPU time 40.63 seconds
Started Sep 04 01:43:57 PM UTC 24
Finished Sep 04 01:44:39 PM UTC 24
Peak memory 269148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193205287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.4193205287
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/7.alert_handler_sig_int_fail.2331224562
Short name T136
Test name
Test status
Simulation time 753916893 ps
CPU time 72.39 seconds
Started Sep 04 01:44:07 PM UTC 24
Finished Sep 04 01:45:21 PM UTC 24
Peak memory 269344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331224562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2331224562
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/7.alert_handler_smoke.2752346068
Short name T223
Test name
Test status
Simulation time 4139166338 ps
CPU time 83.71 seconds
Started Sep 04 01:43:53 PM UTC 24
Finished Sep 04 01:45:19 PM UTC 24
Peak memory 269180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752346068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2752346068
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all.3268162555
Short name T515
Test name
Test status
Simulation time 503800523421 ps
CPU time 3182.19 seconds
Started Sep 04 01:44:41 PM UTC 24
Finished Sep 04 02:38:18 PM UTC 24
Peak memory 304992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268162555 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all.3268162555
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/7.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/8.alert_handler_alert_accum_saturation.3129026005
Short name T242
Test name
Test status
Simulation time 15226964 ps
CPU time 3.75 seconds
Started Sep 04 01:46:15 PM UTC 24
Finished Sep 04 01:46:20 PM UTC 24
Peak memory 263500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129026005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert
_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3129026005
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy.4098139906
Short name T470
Test name
Test status
Simulation time 39069071460 ps
CPU time 2441.83 seconds
Started Sep 04 01:45:33 PM UTC 24
Finished Sep 04 02:26:43 PM UTC 24
Peak memory 299832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098139906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03
/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.4098139906
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy_stress.2770036536
Short name T156
Test name
Test status
Simulation time 122367649 ps
CPU time 11.82 seconds
Started Sep 04 01:46:00 PM UTC 24
Finished Sep 04 01:46:12 PM UTC 24
Peak memory 262980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770036536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2770036536
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_alert_accum.1598625405
Short name T403
Test name
Test status
Simulation time 2229869596 ps
CPU time 160.71 seconds
Started Sep 04 01:45:27 PM UTC 24
Finished Sep 04 01:48:10 PM UTC 24
Peak memory 269136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598625405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1598625405
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_intr_timeout.1112881395
Short name T89
Test name
Test status
Simulation time 163441112 ps
CPU time 9.62 seconds
Started Sep 04 01:45:21 PM UTC 24
Finished Sep 04 01:45:32 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112881395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1112881395
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg.568755127
Short name T74
Test name
Test status
Simulation time 68199104417 ps
CPU time 1639.3 seconds
Started Sep 04 01:45:47 PM UTC 24
Finished Sep 04 02:13:24 PM UTC 24
Peak memory 296068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568755127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.568755127
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg_stub_clk.3581495381
Short name T471
Test name
Test status
Simulation time 35239606745 ps
CPU time 2424.05 seconds
Started Sep 04 01:45:57 PM UTC 24
Finished Sep 04 02:26:50 PM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581495381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3581495381
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/8.alert_handler_ping_timeout.3072073268
Short name T339
Test name
Test status
Simulation time 14715513964 ps
CPU time 261.14 seconds
Started Sep 04 01:45:44 PM UTC 24
Finished Sep 04 01:50:09 PM UTC 24
Peak memory 263300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072073268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3072073268
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_alerts.596745482
Short name T224
Test name
Test status
Simulation time 37485572 ps
CPU time 6.29 seconds
Started Sep 04 01:45:18 PM UTC 24
Finished Sep 04 01:45:26 PM UTC 24
Peak memory 263264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596745482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.596745482
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_classes.645920754
Short name T295
Test name
Test status
Simulation time 421889627 ps
CPU time 25.44 seconds
Started Sep 04 01:45:19 PM UTC 24
Finished Sep 04 01:45:46 PM UTC 24
Peak memory 262892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645920754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra
ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.645920754
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/8.alert_handler_sig_int_fail.306738856
Short name T138
Test name
Test status
Simulation time 1220806949 ps
CPU time 61.5 seconds
Started Sep 04 01:45:31 PM UTC 24
Finished Sep 04 01:46:34 PM UTC 24
Peak memory 269048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306738856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si
g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.306738856
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/8.alert_handler_smoke.1928232402
Short name T401
Test name
Test status
Simulation time 1363241578 ps
CPU time 55.42 seconds
Started Sep 04 01:45:02 PM UTC 24
Finished Sep 04 01:45:59 PM UTC 24
Peak memory 269044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928232402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1928232402
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all.2153033589
Short name T91
Test name
Test status
Simulation time 4453026720 ps
CPU time 128.72 seconds
Started Sep 04 01:46:14 PM UTC 24
Finished Sep 04 01:48:25 PM UTC 24
Peak memory 269244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153033589 -assert nopostproc +UVM_T
ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all.2153033589
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/8.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/9.alert_handler_alert_accum_saturation.25024159
Short name T243
Test name
Test status
Simulation time 129027768 ps
CPU time 6.16 seconds
Started Sep 04 01:48:11 PM UTC 24
Finished Sep 04 01:48:19 PM UTC 24
Peak memory 263496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25024159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_h
andler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_h
andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.25024159
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy_stress.2332412886
Short name T157
Test name
Test status
Simulation time 1107931267 ps
CPU time 68.66 seconds
Started Sep 04 01:47:43 PM UTC 24
Finished Sep 04 01:48:53 PM UTC 24
Peak memory 262908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332412886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2332412886
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_alert_accum.4020698266
Short name T322
Test name
Test status
Simulation time 430510386 ps
CPU time 34.2 seconds
Started Sep 04 01:47:05 PM UTC 24
Finished Sep 04 01:47:41 PM UTC 24
Peak memory 269436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020698266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4020698266
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_intr_timeout.3484883709
Short name T93
Test name
Test status
Simulation time 963715999 ps
CPU time 22.93 seconds
Started Sep 04 01:46:59 PM UTC 24
Finished Sep 04 01:47:24 PM UTC 24
Peak memory 263100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484883709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e
sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3484883709
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg.892997033
Short name T331
Test name
Test status
Simulation time 39208945274 ps
CPU time 1403.15 seconds
Started Sep 04 01:47:34 PM UTC 24
Finished Sep 04 02:11:14 PM UTC 24
Peak memory 285572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892997033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/aler
t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.892997033
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg_stub_clk.517217173
Short name T438
Test name
Test status
Simulation time 53287599356 ps
CPU time 1126.71 seconds
Started Sep 04 01:47:42 PM UTC 24
Finished Sep 04 02:06:41 PM UTC 24
Peak memory 285496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517217173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.517217173
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/9.alert_handler_ping_timeout.2467455866
Short name T340
Test name
Test status
Simulation time 14083165375 ps
CPU time 358.33 seconds
Started Sep 04 01:47:31 PM UTC 24
Finished Sep 04 01:53:34 PM UTC 24
Peak memory 269188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467455866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2467455866
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_alerts.1499841446
Short name T32
Test name
Test status
Simulation time 2415577393 ps
CPU time 56.91 seconds
Started Sep 04 01:46:44 PM UTC 24
Finished Sep 04 01:47:43 PM UTC 24
Peak memory 269108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499841446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1499841446
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_classes.2499353663
Short name T90
Test name
Test status
Simulation time 51536671 ps
CPU time 6.81 seconds
Started Sep 04 01:46:50 PM UTC 24
Finished Sep 04 01:46:58 PM UTC 24
Peak memory 252764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499353663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r
andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2499353663
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/9.alert_handler_sig_int_fail.2191245785
Short name T137
Test name
Test status
Simulation time 14342674843 ps
CPU time 58.04 seconds
Started Sep 04 01:47:25 PM UTC 24
Finished Sep 04 01:48:25 PM UTC 24
Peak memory 269472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191245785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2191245785
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/default/9.alert_handler_smoke.1668477880
Short name T402
Test name
Test status
Simulation time 83486757 ps
CPU time 6.97 seconds
Started Sep 04 01:46:35 PM UTC 24
Finished Sep 04 01:46:43 PM UTC 24
Peak memory 262972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668477880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1668477880
Directory /workspaces/repo/scratch/os_regression_2024_09_03/alert_handler-sim-vcs/9.alert_handler_smoke/latest
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