| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.20 | 99.99 | 98.69 | 97.09 | 100.00 | 100.00 | 99.38 | 99.28 |
| T780 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.2730705793 | Oct 15 08:15:01 AM UTC 24 | Oct 15 08:15:11 AM UTC 24 | 73681070 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.2029727541 | Oct 15 08:14:55 AM UTC 24 | Oct 15 08:15:14 AM UTC 24 | 661252778 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3194985295 | Oct 15 08:15:04 AM UTC 24 | Oct 15 08:15:15 AM UTC 24 | 81746229 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2383511417 | Oct 15 08:15:16 AM UTC 24 | Oct 15 08:15:21 AM UTC 24 | 45975093 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.3975170133 | Oct 15 08:15:21 AM UTC 24 | Oct 15 08:15:24 AM UTC 24 | 12252061 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1199212629 | Oct 15 08:15:02 AM UTC 24 | Oct 15 08:15:25 AM UTC 24 | 1074682781 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.81786180 | Oct 15 08:15:26 AM UTC 24 | Oct 15 08:15:33 AM UTC 24 | 210384501 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3352203203 | Oct 15 08:14:22 AM UTC 24 | Oct 15 08:15:37 AM UTC 24 | 7545778347 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.401085264 | Oct 15 08:15:34 AM UTC 24 | Oct 15 08:15:43 AM UTC 24 | 128025460 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.1850532401 | Oct 15 08:15:15 AM UTC 24 | Oct 15 08:15:44 AM UTC 24 | 1310729168 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.2716580626 | Oct 15 08:15:45 AM UTC 24 | Oct 15 08:15:54 AM UTC 24 | 37606681 ps | ||
| T224 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1425313958 | Oct 15 08:15:55 AM UTC 24 | Oct 15 08:15:59 AM UTC 24 | 50575967 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2864312275 | Oct 15 08:15:27 AM UTC 24 | Oct 15 08:16:00 AM UTC 24 | 4062870026 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.790074312 | Oct 15 08:15:59 AM UTC 24 | Oct 15 08:16:02 AM UTC 24 | 23983484 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.1176394418 | Oct 15 08:16:00 AM UTC 24 | Oct 15 08:16:09 AM UTC 24 | 216269802 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3668948159 | Oct 15 08:16:10 AM UTC 24 | Oct 15 08:16:22 AM UTC 24 | 154642364 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.1505877067 | Oct 15 08:16:23 AM UTC 24 | Oct 15 08:16:26 AM UTC 24 | 52364179 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.2107225810 | Oct 15 08:16:27 AM UTC 24 | Oct 15 08:16:30 AM UTC 24 | 12713088 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2440853526 | Oct 15 08:09:23 AM UTC 24 | Oct 15 08:16:31 AM UTC 24 | 11437384393 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2363557397 | Oct 15 08:12:45 AM UTC 24 | Oct 15 08:16:33 AM UTC 24 | 15231591027 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.1663459401 | Oct 15 08:16:31 AM UTC 24 | Oct 15 08:16:34 AM UTC 24 | 6886591 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.3773544918 | Oct 15 08:16:32 AM UTC 24 | Oct 15 08:16:36 AM UTC 24 | 7370648 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.290040470 | Oct 15 08:16:33 AM UTC 24 | Oct 15 08:16:37 AM UTC 24 | 6709113 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.3573354432 | Oct 15 08:16:36 AM UTC 24 | Oct 15 08:16:39 AM UTC 24 | 11557305 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.2357446005 | Oct 15 08:16:37 AM UTC 24 | Oct 15 08:16:40 AM UTC 24 | 9592172 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.3786119969 | Oct 15 08:16:38 AM UTC 24 | Oct 15 08:16:41 AM UTC 24 | 6720662 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.665651600 | Oct 15 08:16:40 AM UTC 24 | Oct 15 08:16:43 AM UTC 24 | 6895139 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.2459978980 | Oct 15 08:16:41 AM UTC 24 | Oct 15 08:16:44 AM UTC 24 | 9624366 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.629784310 | Oct 15 08:16:42 AM UTC 24 | Oct 15 08:16:45 AM UTC 24 | 12154578 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.2238042718 | Oct 15 08:16:44 AM UTC 24 | Oct 15 08:16:48 AM UTC 24 | 8982559 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.1061507686 | Oct 15 08:16:45 AM UTC 24 | Oct 15 08:16:49 AM UTC 24 | 11422142 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.944527985 | Oct 15 08:14:09 AM UTC 24 | Oct 15 08:16:49 AM UTC 24 | 2513258592 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.2990375402 | Oct 15 08:16:46 AM UTC 24 | Oct 15 08:16:50 AM UTC 24 | 20850587 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.1715104804 | Oct 15 08:16:49 AM UTC 24 | Oct 15 08:16:52 AM UTC 24 | 8644094 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.2917068146 | Oct 15 08:16:50 AM UTC 24 | Oct 15 08:16:53 AM UTC 24 | 7824885 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.103145765 | Oct 15 08:16:50 AM UTC 24 | Oct 15 08:16:53 AM UTC 24 | 16936944 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2344469818 | Oct 15 08:14:54 AM UTC 24 | Oct 15 08:16:53 AM UTC 24 | 1337108331 ps | ||
| T209 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3855242678 | Oct 15 08:15:14 AM UTC 24 | Oct 15 08:16:53 AM UTC 24 | 3067126795 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3680164420 | Oct 15 08:16:03 AM UTC 24 | Oct 15 08:16:54 AM UTC 24 | 6124751579 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.2689778773 | Oct 15 08:16:51 AM UTC 24 | Oct 15 08:16:54 AM UTC 24 | 11054443 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.3302118228 | Oct 15 08:16:53 AM UTC 24 | Oct 15 08:16:56 AM UTC 24 | 6910763 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.2963278265 | Oct 15 08:16:54 AM UTC 24 | Oct 15 08:16:57 AM UTC 24 | 8437945 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.1464195190 | Oct 15 08:16:54 AM UTC 24 | Oct 15 08:16:57 AM UTC 24 | 10978392 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.3122599107 | Oct 15 08:16:54 AM UTC 24 | Oct 15 08:16:57 AM UTC 24 | 14380633 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.627144415 | Oct 15 08:16:54 AM UTC 24 | Oct 15 08:16:58 AM UTC 24 | 7522880 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.923081509 | Oct 15 08:16:54 AM UTC 24 | Oct 15 08:16:58 AM UTC 24 | 10564161 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.1708309263 | Oct 15 08:16:56 AM UTC 24 | Oct 15 08:16:59 AM UTC 24 | 11973275 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.1871593081 | Oct 15 08:16:57 AM UTC 24 | Oct 15 08:17:00 AM UTC 24 | 7621204 ps | ||
| T823 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.3411227805 | Oct 15 08:16:58 AM UTC 24 | Oct 15 08:17:01 AM UTC 24 | 43536225 ps | ||
| T824 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.4069093936 | Oct 15 08:16:58 AM UTC 24 | Oct 15 08:17:01 AM UTC 24 | 23438971 ps | ||
| T825 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.889588524 | Oct 15 08:16:58 AM UTC 24 | Oct 15 08:17:02 AM UTC 24 | 10110834 ps | ||
| T826 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.168288419 | Oct 15 08:16:59 AM UTC 24 | Oct 15 08:17:02 AM UTC 24 | 7318412 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3757284396 | Oct 15 08:13:31 AM UTC 24 | Oct 15 08:17:06 AM UTC 24 | 3101204484 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4185642181 | Oct 15 08:12:00 AM UTC 24 | Oct 15 08:17:09 AM UTC 24 | 18131624003 ps | ||
| T196 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2181004439 | Oct 15 08:11:30 AM UTC 24 | Oct 15 08:17:17 AM UTC 24 | 2256328763 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3458141491 | Oct 15 08:14:30 AM UTC 24 | Oct 15 08:17:32 AM UTC 24 | 6173465336 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2875808332 | Oct 15 08:13:07 AM UTC 24 | Oct 15 08:18:02 AM UTC 24 | 3699189804 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3400555299 | Oct 15 08:06:42 AM UTC 24 | Oct 15 08:18:30 AM UTC 24 | 5676440308 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.626736766 | Oct 15 08:15:44 AM UTC 24 | Oct 15 08:19:41 AM UTC 24 | 2391384262 ps | ||
| T211 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2896048792 | Oct 15 08:12:42 AM UTC 24 | Oct 15 08:20:31 AM UTC 24 | 6323142011 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2919810261 | Oct 15 08:15:38 AM UTC 24 | Oct 15 08:21:16 AM UTC 24 | 9229019159 ps | ||
| T390 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1275584027 | Oct 15 08:14:02 AM UTC 24 | Oct 15 08:21:51 AM UTC 24 | 14802455845 ps | ||
| T388 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2656485262 | Oct 15 08:13:00 AM UTC 24 | Oct 15 08:21:51 AM UTC 24 | 18712419802 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1189118177 | Oct 15 08:12:20 AM UTC 24 | Oct 15 08:22:07 AM UTC 24 | 38103062837 ps | ||
| T389 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.381703221 | Oct 15 08:14:28 AM UTC 24 | Oct 15 08:22:40 AM UTC 24 | 25648212088 ps | ||
| T208 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2138034677 | Oct 15 08:10:33 AM UTC 24 | Oct 15 08:22:41 AM UTC 24 | 37898660166 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2787371555 | Oct 15 08:13:14 AM UTC 24 | Oct 15 08:23:36 AM UTC 24 | 9020645674 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.457786815 | Oct 15 08:07:10 AM UTC 24 | Oct 15 08:23:45 AM UTC 24 | 48869083890 ps | ||
| T391 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2219326017 | Oct 15 08:11:59 AM UTC 24 | Oct 15 08:24:22 AM UTC 24 | 20783892705 ps | ||
| T392 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3736065237 | Oct 15 08:11:26 AM UTC 24 | Oct 15 08:24:57 AM UTC 24 | 17493574431 ps | ||
| T210 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1403987717 | Oct 15 08:14:52 AM UTC 24 | Oct 15 08:25:03 AM UTC 24 | 16116591373 ps | ||
| T216 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1944365212 | Oct 15 08:11:10 AM UTC 24 | Oct 15 08:25:48 AM UTC 24 | 17872284750 ps | ||
| T212 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1761685476 | Oct 15 08:08:16 AM UTC 24 | Oct 15 08:26:00 AM UTC 24 | 28729810000 ps | ||
| T215 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3767220035 | Oct 15 08:13:27 AM UTC 24 | Oct 15 08:27:39 AM UTC 24 | 17562335771 ps | ||
| T214 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1366683925 | Oct 15 08:08:58 AM UTC 24 | Oct 15 08:28:33 AM UTC 24 | 69872318064 ps | ||
| T213 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1722758156 | Oct 15 08:09:55 AM UTC 24 | Oct 15 08:29:35 AM UTC 24 | 18007229626 ps | ||
| T827 | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1530484968 | Oct 15 08:15:11 AM UTC 24 | Oct 15 08:36:25 AM UTC 24 | 68288768207 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_classes.683812471 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 273559667 ps |
| CPU time | 32.49 seconds |
| Started | Oct 15 06:20:53 AM UTC 24 |
| Finished | Oct 15 06:21:27 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683812471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.683812471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/1.alert_handler_sec_cm.2465922432 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 761624616 ps |
| CPU time | 23.31 seconds |
| Started | Oct 15 06:21:34 AM UTC 24 |
| Finished | Oct 15 06:21:59 AM UTC 24 |
| Peak memory | 292932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465922432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2465922432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_intr_timeout.3859457186 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 321541468 ps |
| CPU time | 19.48 seconds |
| Started | Oct 15 06:21:42 AM UTC 24 |
| Finished | Oct 15 06:22:03 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859457186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3859457186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all_with_rand_reset.2709436831 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 1406347588 ps |
| CPU time | 194.09 seconds |
| Started | Oct 15 06:22:24 AM UTC 24 |
| Finished | Oct 15 06:25:42 AM UTC 24 |
| Peak memory | 277268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2709436831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.al ert_handler_stress_all_with_rand_reset.2709436831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy_stress.962507457 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 636250252 ps |
| CPU time | 29.92 seconds |
| Started | Oct 15 06:21:32 AM UTC 24 |
| Finished | Oct 15 06:22:04 AM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962507457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.962507457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_rw.3249562881 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 132410419 ps |
| CPU time | 10.12 seconds |
| Started | Oct 15 08:08:36 AM UTC 24 |
| Finished | Oct 15 08:08:48 AM UTC 24 |
| Peak memory | 250308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249562881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3249562881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all.3324451375 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 71010387747 ps |
| CPU time | 1368.41 seconds |
| Started | Oct 15 06:22:15 AM UTC 24 |
| Finished | Oct 15 06:45:19 AM UTC 24 |
| Peak memory | 299892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324451375 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all.3324451375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all_with_rand_reset.732763334 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 17072260629 ps |
| CPU time | 611.51 seconds |
| Started | Oct 15 07:01:37 AM UTC 24 |
| Finished | Oct 15 07:11:57 AM UTC 24 |
| Peak memory | 283552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=732763334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.al ert_handler_stress_all_with_rand_reset.732763334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/23.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_alerts.3057385948 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1159169793 ps |
| CPU time | 32.26 seconds |
| Started | Oct 15 06:21:39 AM UTC 24 |
| Finished | Oct 15 06:22:12 AM UTC 24 |
| Peak memory | 267176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057385948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3057385948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg.2162599299 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 74965435850 ps |
| CPU time | 1162.61 seconds |
| Started | Oct 15 06:29:45 AM UTC 24 |
| Finished | Oct 15 06:49:20 AM UTC 24 |
| Peak memory | 283764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162599299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2162599299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2364032320 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 3144899689 ps |
| CPU time | 106.75 seconds |
| Started | Oct 15 08:06:58 AM UTC 24 |
| Finished | Oct 15 08:08:47 AM UTC 24 |
| Peak memory | 250180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364032320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2364032320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/8.alert_handler_sig_int_fail.2651020374 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1178325941 ps |
| CPU time | 23.83 seconds |
| Started | Oct 15 06:25:36 AM UTC 24 |
| Finished | Oct 15 06:26:01 AM UTC 24 |
| Peak memory | 260792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651020374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2651020374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1633862406 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 3990702343 ps |
| CPU time | 334.83 seconds |
| Started | Oct 15 08:06:54 AM UTC 24 |
| Finished | Oct 15 08:12:34 AM UTC 24 |
| Peak memory | 277396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633862406 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.1633862406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all.796411377 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 33149253243 ps |
| CPU time | 2762.23 seconds |
| Started | Oct 15 06:23:42 AM UTC 24 |
| Finished | Oct 15 07:10:17 AM UTC 24 |
| Peak memory | 300068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796411377 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all.796411377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all_with_rand_reset.2335883350 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 4336750061 ps |
| CPU time | 236.98 seconds |
| Started | Oct 15 06:51:26 AM UTC 24 |
| Finished | Oct 15 06:55:26 AM UTC 24 |
| Peak memory | 279384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2335883350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.a lert_handler_stress_all_with_rand_reset.2335883350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all_with_rand_reset.148712006 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 15439338590 ps |
| CPU time | 468.84 seconds |
| Started | Oct 15 07:29:36 AM UTC 24 |
| Finished | Oct 15 07:37:32 AM UTC 24 |
| Peak memory | 277412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=148712006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.al ert_handler_stress_all_with_rand_reset.148712006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/39.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2181004439 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 2256328763 ps |
| CPU time | 341.72 seconds |
| Started | Oct 15 08:11:30 AM UTC 24 |
| Finished | Oct 15 08:17:17 AM UTC 24 |
| Peak memory | 281224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181004439 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.2181004439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.457786815 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 48869083890 ps |
| CPU time | 983.19 seconds |
| Started | Oct 15 08:07:10 AM UTC 24 |
| Finished | Oct 15 08:23:45 AM UTC 24 |
| Peak memory | 283272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457786815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow _reg_errors_with_csr_rw.457786815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/2.alert_handler_ping_timeout.4293507324 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 29265360069 ps |
| CPU time | 480.97 seconds |
| Started | Oct 15 06:21:48 AM UTC 24 |
| Finished | Oct 15 06:29:55 AM UTC 24 |
| Peak memory | 260900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293507324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.4293507324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg.2047287784 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 33795868614 ps |
| CPU time | 2127.92 seconds |
| Started | Oct 15 06:23:07 AM UTC 24 |
| Finished | Oct 15 06:59:01 AM UTC 24 |
| Peak memory | 299740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047287784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2047287784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1366683925 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 69872318064 ps |
| CPU time | 1161.75 seconds |
| Started | Oct 15 08:08:58 AM UTC 24 |
| Finished | Oct 15 08:28:33 AM UTC 24 |
| Peak memory | 278704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366683925 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shado w_reg_errors_with_csr_rw.1366683925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_rw.1775382261 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 124035981 ps |
| CPU time | 5.37 seconds |
| Started | Oct 15 08:07:03 AM UTC 24 |
| Finished | Oct 15 08:07:09 AM UTC 24 |
| Peak memory | 248060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775382261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1775382261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy.4283143782 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 97624084262 ps |
| CPU time | 1455.03 seconds |
| Started | Oct 15 06:21:03 AM UTC 24 |
| Finished | Oct 15 06:45:36 AM UTC 24 |
| Peak memory | 283376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283143782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.4283143782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_intr_timeout.2634150961 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 612183585 ps |
| CPU time | 26.06 seconds |
| Started | Oct 15 06:22:01 AM UTC 24 |
| Finished | Oct 15 06:22:28 AM UTC 24 |
| Peak memory | 260824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634150961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2634150961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_intr_test.3988542469 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 8574145 ps |
| CPU time | 2.05 seconds |
| Started | Oct 15 08:07:00 AM UTC 24 |
| Finished | Oct 15 08:07:03 AM UTC 24 |
| Peak memory | 248080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988542469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3988542469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg.3383342650 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 47716401515 ps |
| CPU time | 2502.54 seconds |
| Started | Oct 15 06:22:12 AM UTC 24 |
| Finished | Oct 15 07:04:21 AM UTC 24 |
| Peak memory | 295796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383342650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3383342650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3400555299 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 5676440308 ps |
| CPU time | 698.89 seconds |
| Started | Oct 15 08:06:42 AM UTC 24 |
| Finished | Oct 15 08:18:30 AM UTC 24 |
| Peak memory | 277128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400555299 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shado w_reg_errors_with_csr_rw.3400555299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/10.alert_handler_ping_timeout.2464800275 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 18734336404 ps |
| CPU time | 390.74 seconds |
| Started | Oct 15 06:27:40 AM UTC 24 |
| Finished | Oct 15 06:34:16 AM UTC 24 |
| Peak memory | 261100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464800275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2464800275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/15.alert_handler_ping_timeout.81193464 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 11556032647 ps |
| CPU time | 696.87 seconds |
| Started | Oct 15 06:39:56 AM UTC 24 |
| Finished | Oct 15 06:51:42 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81193464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.81193464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_classes.2277374649 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 339195159 ps |
| CPU time | 28.9 seconds |
| Started | Oct 15 06:21:20 AM UTC 24 |
| Finished | Oct 15 06:21:51 AM UTC 24 |
| Peak memory | 267164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277374649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2277374649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2363557397 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 15231591027 ps |
| CPU time | 223.89 seconds |
| Started | Oct 15 08:12:45 AM UTC 24 |
| Finished | Oct 15 08:16:33 AM UTC 24 |
| Peak memory | 283340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363557397 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.2363557397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1403987717 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 16116591373 ps |
| CPU time | 604.34 seconds |
| Started | Oct 15 08:14:52 AM UTC 24 |
| Finished | Oct 15 08:25:03 AM UTC 24 |
| Peak memory | 277128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403987717 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shad ow_reg_errors_with_csr_rw.1403987717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all.1693425391 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 6657802553 ps |
| CPU time | 450.56 seconds |
| Started | Oct 15 06:21:13 AM UTC 24 |
| Finished | Oct 15 06:28:50 AM UTC 24 |
| Peak memory | 267236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693425391 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all.1693425391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg.300796456 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 30782556179 ps |
| CPU time | 2087.76 seconds |
| Started | Oct 15 06:21:04 AM UTC 24 |
| Finished | Oct 15 06:56:16 AM UTC 24 |
| Peak memory | 293668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300796456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.300796456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy.258666477 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 24235692433 ps |
| CPU time | 1440.71 seconds |
| Started | Oct 15 06:37:07 AM UTC 24 |
| Finished | Oct 15 07:01:24 AM UTC 24 |
| Peak memory | 283424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258666477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.258666477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_classes.2017074896 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 786672562 ps |
| CPU time | 56.74 seconds |
| Started | Oct 15 06:21:42 AM UTC 24 |
| Finished | Oct 15 06:22:41 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017074896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2017074896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all.759707829 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 51014064639 ps |
| CPU time | 2566.53 seconds |
| Started | Oct 15 07:13:44 AM UTC 24 |
| Finished | Oct 15 07:56:57 AM UTC 24 |
| Peak memory | 302304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759707829 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all.759707829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/30.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2875808332 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 3699189804 ps |
| CPU time | 290.84 seconds |
| Started | Oct 15 08:13:07 AM UTC 24 |
| Finished | Oct 15 08:18:02 AM UTC 24 |
| Peak memory | 283312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875808332 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.2875808332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all.1378210691 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 11089879416 ps |
| CPU time | 1200.75 seconds |
| Started | Oct 15 06:32:22 AM UTC 24 |
| Finished | Oct 15 06:52:38 AM UTC 24 |
| Peak memory | 300004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378210691 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all.1378210691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg.3410955325 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 27708169498 ps |
| CPU time | 1891.75 seconds |
| Started | Oct 15 06:31:52 AM UTC 24 |
| Finished | Oct 15 07:03:45 AM UTC 24 |
| Peak memory | 283700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410955325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3410955325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/13.alert_handler_ping_timeout.617317307 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 10430545274 ps |
| CPU time | 453.5 seconds |
| Started | Oct 15 06:33:58 AM UTC 24 |
| Finished | Oct 15 06:41:38 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617317307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.617317307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all.1602776810 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 100195915630 ps |
| CPU time | 3395.55 seconds |
| Started | Oct 15 07:29:36 AM UTC 24 |
| Finished | Oct 15 08:26:50 AM UTC 24 |
| Peak memory | 302572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602776810 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all.1602776810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/39.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3767220035 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 17562335771 ps |
| CPU time | 840.64 seconds |
| Started | Oct 15 08:13:27 AM UTC 24 |
| Finished | Oct 15 08:27:39 AM UTC 24 |
| Peak memory | 283268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767220035 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shad ow_reg_errors_with_csr_rw.3767220035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg.1229463687 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 21994641805 ps |
| CPU time | 1191.35 seconds |
| Started | Oct 15 06:37:52 AM UTC 24 |
| Finished | Oct 15 06:57:57 AM UTC 24 |
| Peak memory | 283508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229463687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1229463687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3757284396 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 3101204484 ps |
| CPU time | 210.74 seconds |
| Started | Oct 15 08:13:31 AM UTC 24 |
| Finished | Oct 15 08:17:06 AM UTC 24 |
| Peak memory | 279244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757284396 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.3757284396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_intr_test.1301479100 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 11786394 ps |
| CPU time | 2.2 seconds |
| Started | Oct 15 08:09:18 AM UTC 24 |
| Finished | Oct 15 08:09:21 AM UTC 24 |
| Peak memory | 248004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301479100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1301479100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all.3555677083 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 84742130278 ps |
| CPU time | 2589.76 seconds |
| Started | Oct 15 06:22:41 AM UTC 24 |
| Finished | Oct 15 07:06:18 AM UTC 24 |
| Peak memory | 310052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555677083 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all.3555677083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy.544593810 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 25334653688 ps |
| CPU time | 1044.34 seconds |
| Started | Oct 15 06:21:28 AM UTC 24 |
| Finished | Oct 15 06:39:05 AM UTC 24 |
| Peak memory | 283420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544593810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.544593810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_alert_accum.3685604522 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1507818196 ps |
| CPU time | 76.24 seconds |
| Started | Oct 15 06:24:13 AM UTC 24 |
| Finished | Oct 15 06:25:32 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685604522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3685604522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/0.alert_handler_ping_timeout.1981202128 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 21663016370 ps |
| CPU time | 396.85 seconds |
| Started | Oct 15 06:21:03 AM UTC 24 |
| Finished | Oct 15 06:27:45 AM UTC 24 |
| Peak memory | 266968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981202128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1981202128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all.1158662827 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 249296617383 ps |
| CPU time | 2637.4 seconds |
| Started | Oct 15 07:03:44 AM UTC 24 |
| Finished | Oct 15 07:48:10 AM UTC 24 |
| Peak memory | 300508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158662827 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all.1158662827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/24.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/26.alert_handler_ping_timeout.573901451 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 21179951968 ps |
| CPU time | 501.72 seconds |
| Started | Oct 15 07:06:51 AM UTC 24 |
| Finished | Oct 15 07:15:20 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573901451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.573901451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg.2678968184 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 40372080121 ps |
| CPU time | 2262.01 seconds |
| Started | Oct 15 06:24:45 AM UTC 24 |
| Finished | Oct 15 07:02:52 AM UTC 24 |
| Peak memory | 299740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678968184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2678968184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_intg_err.842205473 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 324104031 ps |
| CPU time | 2.86 seconds |
| Started | Oct 15 08:07:41 AM UTC 24 |
| Finished | Oct 15 08:07:45 AM UTC 24 |
| Peak memory | 248064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842205473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.842205473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3054702554 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 7698095584 ps |
| CPU time | 312.21 seconds |
| Started | Oct 15 08:06:43 AM UTC 24 |
| Finished | Oct 15 08:12:00 AM UTC 24 |
| Peak memory | 283472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054702554 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.3054702554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_alert_accum.436263879 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2819338031 ps |
| CPU time | 92.35 seconds |
| Started | Oct 15 06:20:55 AM UTC 24 |
| Finished | Oct 15 06:22:30 AM UTC 24 |
| Peak memory | 260820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436263879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.436263879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg.549811161 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 61771635271 ps |
| CPU time | 742.98 seconds |
| Started | Oct 15 06:46:20 AM UTC 24 |
| Finished | Oct 15 06:58:51 AM UTC 24 |
| Peak memory | 283444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549811161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.549811161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_alert_accum.1289602488 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2584778813 ps |
| CPU time | 45.35 seconds |
| Started | Oct 15 06:22:33 AM UTC 24 |
| Finished | Oct 15 06:23:20 AM UTC 24 |
| Peak memory | 260824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289602488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1289602488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3736065237 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 17493574431 ps |
| CPU time | 799.46 seconds |
| Started | Oct 15 08:11:26 AM UTC 24 |
| Finished | Oct 15 08:24:57 AM UTC 24 |
| Peak memory | 277196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736065237 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shado w_reg_errors_with_csr_rw.3736065237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/0.alert_handler_alert_accum_saturation.3362302763 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 72223318 ps |
| CPU time | 5.49 seconds |
| Started | Oct 15 06:21:13 AM UTC 24 |
| Finished | Oct 15 06:21:19 AM UTC 24 |
| Peak memory | 261028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362302763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3362302763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/1.alert_handler_alert_accum_saturation.1353531826 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 176967666 ps |
| CPU time | 6.38 seconds |
| Started | Oct 15 06:21:33 AM UTC 24 |
| Finished | Oct 15 06:21:41 AM UTC 24 |
| Peak memory | 261036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353531826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1353531826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/10.alert_handler_alert_accum_saturation.80879761 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 74554723 ps |
| CPU time | 5.68 seconds |
| Started | Oct 15 06:28:24 AM UTC 24 |
| Finished | Oct 15 06:28:31 AM UTC 24 |
| Peak memory | 261232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80879761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_h andler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_h andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.80879761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/12.alert_handler_alert_accum_saturation.2530835478 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 14295581 ps |
| CPU time | 3.72 seconds |
| Started | Oct 15 06:32:30 AM UTC 24 |
| Finished | Oct 15 06:32:34 AM UTC 24 |
| Peak memory | 261296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530835478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2530835478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg.1795553256 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 71253884116 ps |
| CPU time | 2359.21 seconds |
| Started | Oct 15 06:21:30 AM UTC 24 |
| Finished | Oct 15 07:01:17 AM UTC 24 |
| Peak memory | 298032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795553256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1795553256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/12.alert_handler_ping_timeout.2478062667 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 51124084022 ps |
| CPU time | 437.28 seconds |
| Started | Oct 15 06:31:48 AM UTC 24 |
| Finished | Oct 15 06:39:10 AM UTC 24 |
| Peak memory | 260904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478062667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2478062667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all_with_rand_reset.1307205707 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 1498275324 ps |
| CPU time | 142.56 seconds |
| Started | Oct 15 06:32:34 AM UTC 24 |
| Finished | Oct 15 06:34:59 AM UTC 24 |
| Peak memory | 281372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1307205707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.a lert_handler_stress_all_with_rand_reset.1307205707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all.615605902 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 91456690663 ps |
| CPU time | 2737.39 seconds |
| Started | Oct 15 06:38:09 AM UTC 24 |
| Finished | Oct 15 07:24:17 AM UTC 24 |
| Peak memory | 296236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615605902 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all.615605902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/21.alert_handler_sig_int_fail.68574647 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1141367966 ps |
| CPU time | 69.93 seconds |
| Started | Oct 15 06:55:51 AM UTC 24 |
| Finished | Oct 15 06:57:03 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68574647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig _int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.68574647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg_stub_clk.4118412262 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 20718194465 ps |
| CPU time | 2071.48 seconds |
| Started | Oct 15 07:10:11 AM UTC 24 |
| Finished | Oct 15 07:45:05 AM UTC 24 |
| Peak memory | 302516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118412262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.4118412262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg.621923202 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 12917586083 ps |
| CPU time | 826.06 seconds |
| Started | Oct 15 07:35:58 AM UTC 24 |
| Finished | Oct 15 07:49:56 AM UTC 24 |
| Peak memory | 283352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621923202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.621923202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/42.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all.1216085674 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 63408340834 ps |
| CPU time | 3263.05 seconds |
| Started | Oct 15 07:39:13 AM UTC 24 |
| Finished | Oct 15 08:34:11 AM UTC 24 |
| Peak memory | 314516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216085674 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all.1216085674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/43.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2344469818 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1337108331 ps |
| CPU time | 116.83 seconds |
| Started | Oct 15 08:14:54 AM UTC 24 |
| Finished | Oct 15 08:16:53 AM UTC 24 |
| Peak memory | 277064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344469818 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.2344469818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4185642181 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 18131624003 ps |
| CPU time | 304.03 seconds |
| Started | Oct 15 08:12:00 AM UTC 24 |
| Finished | Oct 15 08:17:09 AM UTC 24 |
| Peak memory | 277132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185642181 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.4185642181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.626736766 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 2391384262 ps |
| CPU time | 233.39 seconds |
| Started | Oct 15 08:15:44 AM UTC 24 |
| Finished | Oct 15 08:19:41 AM UTC 24 |
| Peak memory | 277204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626736766 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.626736766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1425313958 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 50575967 ps |
| CPU time | 2.43 seconds |
| Started | Oct 15 08:15:55 AM UTC 24 |
| Finished | Oct 15 08:15:59 AM UTC 24 |
| Peak memory | 248060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425313958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1425313958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1722758156 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 18007229626 ps |
| CPU time | 1165.79 seconds |
| Started | Oct 15 08:09:55 AM UTC 24 |
| Finished | Oct 15 08:29:35 AM UTC 24 |
| Peak memory | 284848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722758156 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shado w_reg_errors_with_csr_rw.1722758156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/5.alert_handler_ping_timeout.1822070673 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 26894977484 ps |
| CPU time | 432.88 seconds |
| Started | Oct 15 06:23:04 AM UTC 24 |
| Finished | Oct 15 06:30:23 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822070673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1822070673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/1.alert_handler_sig_int_fail.151486213 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1512280002 ps |
| CPU time | 30.08 seconds |
| Started | Oct 15 06:21:28 AM UTC 24 |
| Finished | Oct 15 06:22:00 AM UTC 24 |
| Peak memory | 267228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151486213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.151486213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/14.alert_handler_sig_int_fail.1296121160 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 3534193561 ps |
| CPU time | 50.18 seconds |
| Started | Oct 15 06:37:00 AM UTC 24 |
| Finished | Oct 15 06:37:51 AM UTC 24 |
| Peak memory | 260896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296121160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1296121160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/16.alert_handler_ping_timeout.3869819681 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 86568543562 ps |
| CPU time | 438.57 seconds |
| Started | Oct 15 06:43:53 AM UTC 24 |
| Finished | Oct 15 06:51:17 AM UTC 24 |
| Peak memory | 261096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869819681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3869819681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all.2073015520 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 248519362971 ps |
| CPU time | 1820.38 seconds |
| Started | Oct 15 06:21:52 AM UTC 24 |
| Finished | Oct 15 06:52:31 AM UTC 24 |
| Peak memory | 283372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073015520 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all.2073015520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/20.alert_handler_ping_timeout.747236841 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 15540532904 ps |
| CPU time | 769.45 seconds |
| Started | Oct 15 06:53:23 AM UTC 24 |
| Finished | Oct 15 07:06:23 AM UTC 24 |
| Peak memory | 260824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747236841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.747236841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg.2377969665 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 434116380551 ps |
| CPU time | 3292.1 seconds |
| Started | Oct 15 06:56:17 AM UTC 24 |
| Finished | Oct 15 07:51:46 AM UTC 24 |
| Peak memory | 300264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377969665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2377969665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/21.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/27.alert_handler_ping_timeout.1861150788 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 20648274618 ps |
| CPU time | 208.46 seconds |
| Started | Oct 15 07:08:35 AM UTC 24 |
| Finished | Oct 15 07:12:06 AM UTC 24 |
| Peak memory | 260908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861150788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1861150788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all_with_rand_reset.2949765150 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 4298175440 ps |
| CPU time | 172.41 seconds |
| Started | Oct 15 07:13:50 AM UTC 24 |
| Finished | Oct 15 07:16:45 AM UTC 24 |
| Peak memory | 277412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2949765150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.a lert_handler_stress_all_with_rand_reset.2949765150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all.1202448520 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 150479505503 ps |
| CPU time | 4068.5 seconds |
| Started | Oct 15 07:21:15 AM UTC 24 |
| Finished | Oct 15 08:29:49 AM UTC 24 |
| Peak memory | 312548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202448520 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all.1202448520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/34.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all_with_rand_reset.1906078316 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2402095060 ps |
| CPU time | 163.36 seconds |
| Started | Oct 15 07:46:48 AM UTC 24 |
| Finished | Oct 15 07:49:34 AM UTC 24 |
| Peak memory | 277412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1906078316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.a lert_handler_stress_all_with_rand_reset.1906078316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all_with_rand_reset.4271641935 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 4904364043 ps |
| CPU time | 518.61 seconds |
| Started | Oct 15 07:51:32 AM UTC 24 |
| Finished | Oct 15 08:00:17 AM UTC 24 |
| Peak memory | 281436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4271641935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.a lert_handler_stress_all_with_rand_reset.4271641935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all.843858423 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 67534407718 ps |
| CPU time | 1573.89 seconds |
| Started | Oct 15 06:26:32 AM UTC 24 |
| Finished | Oct 15 06:53:03 AM UTC 24 |
| Peak memory | 299880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843858423 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all.843858423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/2.alert_handler_sec_cm.2822875609 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 240284495 ps |
| CPU time | 14.94 seconds |
| Started | Oct 15 06:21:58 AM UTC 24 |
| Finished | Oct 15 06:22:14 AM UTC 24 |
| Peak memory | 292936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822875609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2822875609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3686519254 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 37963669 ps |
| CPU time | 4.81 seconds |
| Started | Oct 15 08:08:27 AM UTC 24 |
| Finished | Oct 15 08:08:33 AM UTC 24 |
| Peak memory | 248068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686519254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3686519254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1620252272 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 234386708 ps |
| CPU time | 6.2 seconds |
| Started | Oct 15 08:11:41 AM UTC 24 |
| Finished | Oct 15 08:11:48 AM UTC 24 |
| Peak memory | 248328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620252272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1620252272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3084379530 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 237494872 ps |
| CPU time | 3.25 seconds |
| Started | Oct 15 08:13:17 AM UTC 24 |
| Finished | Oct 15 08:13:21 AM UTC 24 |
| Peak memory | 248132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084379530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3084379530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2526295958 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 32473225 ps |
| CPU time | 4.09 seconds |
| Started | Oct 15 08:14:55 AM UTC 24 |
| Finished | Oct 15 08:15:00 AM UTC 24 |
| Peak memory | 248324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526295958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2526295958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1196127914 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 142455200 ps |
| CPU time | 11.72 seconds |
| Started | Oct 15 08:09:10 AM UTC 24 |
| Finished | Oct 15 08:09:23 AM UTC 24 |
| Peak memory | 250188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196127914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1196127914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_alerts.1197441377 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3291098791 ps |
| CPU time | 50.88 seconds |
| Started | Oct 15 06:21:18 AM UTC 24 |
| Finished | Oct 15 06:22:11 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197441377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1197441377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3112406979 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 90141234 ps |
| CPU time | 3.46 seconds |
| Started | Oct 15 08:13:08 AM UTC 24 |
| Finished | Oct 15 08:13:13 AM UTC 24 |
| Peak memory | 248256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112406979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3112406979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.288113696 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 150599682 ps |
| CPU time | 2.75 seconds |
| Started | Oct 15 08:14:36 AM UTC 24 |
| Finished | Oct 15 08:14:40 AM UTC 24 |
| Peak memory | 250308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288113696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.288113696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3890215732 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1817979326 ps |
| CPU time | 97.71 seconds |
| Started | Oct 15 08:11:10 AM UTC 24 |
| Finished | Oct 15 08:12:50 AM UTC 24 |
| Peak memory | 279112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890215732 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.3890215732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1100855341 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 57289906 ps |
| CPU time | 3.81 seconds |
| Started | Oct 15 08:06:45 AM UTC 24 |
| Finished | Oct 15 08:06:50 AM UTC 24 |
| Peak memory | 248064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100855341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1100855341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1341905966 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 131497348 ps |
| CPU time | 10.2 seconds |
| Started | Oct 15 08:12:33 AM UTC 24 |
| Finished | Oct 15 08:12:45 AM UTC 24 |
| Peak memory | 248056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341905966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1341905966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2896227722 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 916082054 ps |
| CPU time | 95.64 seconds |
| Started | Oct 15 08:12:50 AM UTC 24 |
| Finished | Oct 15 08:14:28 AM UTC 24 |
| Peak memory | 258292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896227722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2896227722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3492130892 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 387344474 ps |
| CPU time | 6.05 seconds |
| Started | Oct 15 08:14:13 AM UTC 24 |
| Finished | Oct 15 08:14:20 AM UTC 24 |
| Peak memory | 248056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492130892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3492130892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_intg_err.321103887 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 618263111 ps |
| CPU time | 40.62 seconds |
| Started | Oct 15 08:10:15 AM UTC 24 |
| Finished | Oct 15 08:10:57 AM UTC 24 |
| Peak memory | 250108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321103887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.321103887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1830004025 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 34055845 ps |
| CPU time | 3.3 seconds |
| Started | Oct 15 08:10:36 AM UTC 24 |
| Finished | Oct 15 08:10:40 AM UTC 24 |
| Peak memory | 248204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830004025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1830004025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2706616512 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 190659370 ps |
| CPU time | 2.89 seconds |
| Started | Oct 15 08:11:20 AM UTC 24 |
| Finished | Oct 15 08:11:24 AM UTC 24 |
| Peak memory | 248140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706616512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2706616512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg.695618730 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 105267838660 ps |
| CPU time | 2123.7 seconds |
| Started | Oct 15 06:52:14 AM UTC 24 |
| Finished | Oct 15 07:28:02 AM UTC 24 |
| Peak memory | 285860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695618730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.695618730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2611920055 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1101612478 ps |
| CPU time | 128.04 seconds |
| Started | Oct 15 08:06:50 AM UTC 24 |
| Finished | Oct 15 08:09:01 AM UTC 24 |
| Peak memory | 250120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611920055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2611920055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.470018701 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 8922825947 ps |
| CPU time | 218.42 seconds |
| Started | Oct 15 08:06:50 AM UTC 24 |
| Finished | Oct 15 08:10:32 AM UTC 24 |
| Peak memory | 248124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470018701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.470018701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1884165298 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 28693679 ps |
| CPU time | 6.21 seconds |
| Started | Oct 15 08:06:47 AM UTC 24 |
| Finished | Oct 15 08:06:54 AM UTC 24 |
| Peak memory | 260352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884165298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1884165298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3809791851 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 134766820 ps |
| CPU time | 8.23 seconds |
| Started | Oct 15 08:06:54 AM UTC 24 |
| Finished | Oct 15 08:07:04 AM UTC 24 |
| Peak memory | 264512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809791851 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_ rw_with_rand_reset.3809791851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_rw.566439093 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 90581341 ps |
| CPU time | 4.97 seconds |
| Started | Oct 15 08:06:48 AM UTC 24 |
| Finished | Oct 15 08:06:54 AM UTC 24 |
| Peak memory | 248260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566439093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.566439093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_intr_test.3803876576 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 9532518 ps |
| CPU time | 1.78 seconds |
| Started | Oct 15 08:06:46 AM UTC 24 |
| Finished | Oct 15 08:06:49 AM UTC 24 |
| Peak memory | 247500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803876576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3803876576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2595480441 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 711092600 ps |
| CPU time | 46.62 seconds |
| Started | Oct 15 08:06:51 AM UTC 24 |
| Finished | Oct 15 08:07:39 AM UTC 24 |
| Peak memory | 260420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595480441 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.2595480441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_errors.416698056 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 883540086 ps |
| CPU time | 16.53 seconds |
| Started | Oct 15 08:06:44 AM UTC 24 |
| Finished | Oct 15 08:07:02 AM UTC 24 |
| Peak memory | 260552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416698056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.416698056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3571009373 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 3391428401 ps |
| CPU time | 348.93 seconds |
| Started | Oct 15 08:07:05 AM UTC 24 |
| Finished | Oct 15 08:12:59 AM UTC 24 |
| Peak memory | 250184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571009373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3571009373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3307846405 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 2909768926 ps |
| CPU time | 240.79 seconds |
| Started | Oct 15 08:07:04 AM UTC 24 |
| Finished | Oct 15 08:11:08 AM UTC 24 |
| Peak memory | 248396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307846405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3307846405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.493327324 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 224249866 ps |
| CPU time | 15 seconds |
| Started | Oct 15 08:07:00 AM UTC 24 |
| Finished | Oct 15 08:07:16 AM UTC 24 |
| Peak memory | 260556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493327324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.493327324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.4073217060 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 377218925 ps |
| CPU time | 10.99 seconds |
| Started | Oct 15 08:07:08 AM UTC 24 |
| Finished | Oct 15 08:07:20 AM UTC 24 |
| Peak memory | 250180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073217060 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_ rw_with_rand_reset.4073217060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1130909175 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1213628094 ps |
| CPU time | 53.17 seconds |
| Started | Oct 15 08:07:06 AM UTC 24 |
| Finished | Oct 15 08:08:01 AM UTC 24 |
| Peak memory | 260420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130909175 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.1130909175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.257899942 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 24430142969 ps |
| CPU time | 448.12 seconds |
| Started | Oct 15 08:06:54 AM UTC 24 |
| Finished | Oct 15 08:14:28 AM UTC 24 |
| Peak memory | 281224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257899942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow _reg_errors_with_csr_rw.257899942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_errors.1093017658 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 996406008 ps |
| CPU time | 10.24 seconds |
| Started | Oct 15 08:06:56 AM UTC 24 |
| Finished | Oct 15 08:07:07 AM UTC 24 |
| Peak memory | 266580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093017658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1093017658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3705365784 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 123939056 ps |
| CPU time | 7.76 seconds |
| Started | Oct 15 08:12:40 AM UTC 24 |
| Finished | Oct 15 08:12:49 AM UTC 24 |
| Peak memory | 266632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705365784 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_mem _rw_with_rand_reset.3705365784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_rw.485705454 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 33680303 ps |
| CPU time | 4.81 seconds |
| Started | Oct 15 08:12:36 AM UTC 24 |
| Finished | Oct 15 08:12:42 AM UTC 24 |
| Peak memory | 248056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485705454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.485705454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_intr_test.4133091871 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 28164046 ps |
| CPU time | 2.43 seconds |
| Started | Oct 15 08:12:36 AM UTC 24 |
| Finished | Oct 15 08:12:39 AM UTC 24 |
| Peak memory | 248016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133091871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.4133091871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1344901059 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 719930222 ps |
| CPU time | 28.44 seconds |
| Started | Oct 15 08:12:37 AM UTC 24 |
| Finished | Oct 15 08:13:07 AM UTC 24 |
| Peak memory | 258304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344901059 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outstanding.1344901059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.224344242 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 15003411879 ps |
| CPU time | 91.5 seconds |
| Started | Oct 15 08:12:25 AM UTC 24 |
| Finished | Oct 15 08:13:59 AM UTC 24 |
| Peak memory | 279252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224344242 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.224344242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1189118177 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 38103062837 ps |
| CPU time | 579.81 seconds |
| Started | Oct 15 08:12:20 AM UTC 24 |
| Finished | Oct 15 08:22:07 AM UTC 24 |
| Peak memory | 277128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189118177 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shad ow_reg_errors_with_csr_rw.1189118177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_errors.1233316985 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 849245871 ps |
| CPU time | 19.97 seconds |
| Started | Oct 15 08:12:29 AM UTC 24 |
| Finished | Oct 15 08:12:51 AM UTC 24 |
| Peak memory | 260432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233316985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1233316985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3580697090 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 141144059 ps |
| CPU time | 7.86 seconds |
| Started | Oct 15 08:12:59 AM UTC 24 |
| Finished | Oct 15 08:13:08 AM UTC 24 |
| Peak memory | 266564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580697090 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_mem _rw_with_rand_reset.3580697090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_rw.1208979852 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 636442302 ps |
| CPU time | 12.57 seconds |
| Started | Oct 15 08:12:53 AM UTC 24 |
| Finished | Oct 15 08:13:06 AM UTC 24 |
| Peak memory | 250108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208979852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1208979852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_intr_test.1665929610 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 13064230 ps |
| CPU time | 2.29 seconds |
| Started | Oct 15 08:12:53 AM UTC 24 |
| Finished | Oct 15 08:12:56 AM UTC 24 |
| Peak memory | 248208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665929610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1665929610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3311216036 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 182938981 ps |
| CPU time | 18.12 seconds |
| Started | Oct 15 08:12:57 AM UTC 24 |
| Finished | Oct 15 08:13:16 AM UTC 24 |
| Peak memory | 258444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311216036 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outstanding.3311216036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2896048792 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 6323142011 ps |
| CPU time | 462.79 seconds |
| Started | Oct 15 08:12:42 AM UTC 24 |
| Finished | Oct 15 08:20:31 AM UTC 24 |
| Peak memory | 277200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896048792 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shad ow_reg_errors_with_csr_rw.2896048792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_errors.1796008980 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 747924195 ps |
| CPU time | 19.48 seconds |
| Started | Oct 15 08:12:49 AM UTC 24 |
| Finished | Oct 15 08:13:10 AM UTC 24 |
| Peak memory | 264656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796008980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1796008980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1221811193 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 29465982 ps |
| CPU time | 7 seconds |
| Started | Oct 15 08:13:13 AM UTC 24 |
| Finished | Oct 15 08:13:21 AM UTC 24 |
| Peak memory | 250248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221811193 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_mem _rw_with_rand_reset.1221811193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_rw.4095774274 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 93757098 ps |
| CPU time | 11.96 seconds |
| Started | Oct 15 08:13:10 AM UTC 24 |
| Finished | Oct 15 08:13:24 AM UTC 24 |
| Peak memory | 250108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095774274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.4095774274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_intr_test.1102272335 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 17073311 ps |
| CPU time | 2.07 seconds |
| Started | Oct 15 08:13:09 AM UTC 24 |
| Finished | Oct 15 08:13:12 AM UTC 24 |
| Peak memory | 248208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102272335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1102272335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2397394085 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 978336917 ps |
| CPU time | 59.93 seconds |
| Started | Oct 15 08:13:10 AM UTC 24 |
| Finished | Oct 15 08:14:13 AM UTC 24 |
| Peak memory | 258504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397394085 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outstanding.2397394085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2656485262 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 18712419802 ps |
| CPU time | 523.98 seconds |
| Started | Oct 15 08:13:00 AM UTC 24 |
| Finished | Oct 15 08:21:51 AM UTC 24 |
| Peak memory | 281220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656485262 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shad ow_reg_errors_with_csr_rw.2656485262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_errors.924138071 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 129501533 ps |
| CPU time | 8.24 seconds |
| Started | Oct 15 08:13:07 AM UTC 24 |
| Finished | Oct 15 08:13:16 AM UTC 24 |
| Peak memory | 260540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924138071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.924138071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2853666917 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 691542084 ps |
| CPU time | 11.27 seconds |
| Started | Oct 15 08:13:26 AM UTC 24 |
| Finished | Oct 15 08:13:39 AM UTC 24 |
| Peak memory | 250380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853666917 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_mem _rw_with_rand_reset.2853666917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_rw.3500424814 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 52996559 ps |
| CPU time | 7.12 seconds |
| Started | Oct 15 08:13:22 AM UTC 24 |
| Finished | Oct 15 08:13:30 AM UTC 24 |
| Peak memory | 250108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500424814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3500424814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_intr_test.2577094524 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 14041603 ps |
| CPU time | 2.03 seconds |
| Started | Oct 15 08:13:22 AM UTC 24 |
| Finished | Oct 15 08:13:25 AM UTC 24 |
| Peak memory | 248080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577094524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2577094524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.188237245 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 331419126 ps |
| CPU time | 34.03 seconds |
| Started | Oct 15 08:13:25 AM UTC 24 |
| Finished | Oct 15 08:14:01 AM UTC 24 |
| Peak memory | 260348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188237245 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outstanding.188237245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1491081175 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 3486253593 ps |
| CPU time | 105.53 seconds |
| Started | Oct 15 08:13:14 AM UTC 24 |
| Finished | Oct 15 08:15:02 AM UTC 24 |
| Peak memory | 277124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491081175 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.1491081175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2787371555 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 9020645674 ps |
| CPU time | 614.56 seconds |
| Started | Oct 15 08:13:14 AM UTC 24 |
| Finished | Oct 15 08:23:36 AM UTC 24 |
| Peak memory | 277124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787371555 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shad ow_reg_errors_with_csr_rw.2787371555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_errors.3495021097 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 109824692 ps |
| CPU time | 8.37 seconds |
| Started | Oct 15 08:13:17 AM UTC 24 |
| Finished | Oct 15 08:13:26 AM UTC 24 |
| Peak memory | 260360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495021097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3495021097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3088258149 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 33279145 ps |
| CPU time | 7.2 seconds |
| Started | Oct 15 08:14:02 AM UTC 24 |
| Finished | Oct 15 08:14:10 AM UTC 24 |
| Peak memory | 252296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088258149 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_mem _rw_with_rand_reset.3088258149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_rw.3824200377 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 64102926 ps |
| CPU time | 7.85 seconds |
| Started | Oct 15 08:13:52 AM UTC 24 |
| Finished | Oct 15 08:14:01 AM UTC 24 |
| Peak memory | 250108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824200377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3824200377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_intr_test.1274712212 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 6499112 ps |
| CPU time | 2.18 seconds |
| Started | Oct 15 08:13:48 AM UTC 24 |
| Finished | Oct 15 08:13:51 AM UTC 24 |
| Peak memory | 245956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274712212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1274712212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2472846698 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 630124103 ps |
| CPU time | 51.83 seconds |
| Started | Oct 15 08:14:00 AM UTC 24 |
| Finished | Oct 15 08:14:53 AM UTC 24 |
| Peak memory | 258380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472846698 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outstanding.2472846698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_errors.2393325229 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 1422390710 ps |
| CPU time | 32.67 seconds |
| Started | Oct 15 08:13:35 AM UTC 24 |
| Finished | Oct 15 08:14:09 AM UTC 24 |
| Peak memory | 266500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393325229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2393325229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3251664632 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 225669244 ps |
| CPU time | 5.84 seconds |
| Started | Oct 15 08:13:40 AM UTC 24 |
| Finished | Oct 15 08:13:47 AM UTC 24 |
| Peak memory | 248060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251664632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3251664632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4224670847 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 570265821 ps |
| CPU time | 8.69 seconds |
| Started | Oct 15 08:14:25 AM UTC 24 |
| Finished | Oct 15 08:14:35 AM UTC 24 |
| Peak memory | 266560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224670847 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_mem _rw_with_rand_reset.4224670847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_rw.20347596 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 95880863 ps |
| CPU time | 7.02 seconds |
| Started | Oct 15 08:14:19 AM UTC 24 |
| Finished | Oct 15 08:14:27 AM UTC 24 |
| Peak memory | 250308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20347596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_han dler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.20347596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_intr_test.894174428 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 8856803 ps |
| CPU time | 2.26 seconds |
| Started | Oct 15 08:14:14 AM UTC 24 |
| Finished | Oct 15 08:14:18 AM UTC 24 |
| Peak memory | 248208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894174428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.894174428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3352203203 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 7545778347 ps |
| CPU time | 73.36 seconds |
| Started | Oct 15 08:14:22 AM UTC 24 |
| Finished | Oct 15 08:15:37 AM UTC 24 |
| Peak memory | 258376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352203203 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outstanding.3352203203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.944527985 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2513258592 ps |
| CPU time | 157.03 seconds |
| Started | Oct 15 08:14:09 AM UTC 24 |
| Finished | Oct 15 08:16:49 AM UTC 24 |
| Peak memory | 267156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944527985 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.944527985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1275584027 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 14802455845 ps |
| CPU time | 462.14 seconds |
| Started | Oct 15 08:14:02 AM UTC 24 |
| Finished | Oct 15 08:21:51 AM UTC 24 |
| Peak memory | 277328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275584027 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shad ow_reg_errors_with_csr_rw.1275584027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_errors.1324262449 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 304973117 ps |
| CPU time | 9.07 seconds |
| Started | Oct 15 08:14:13 AM UTC 24 |
| Finished | Oct 15 08:14:23 AM UTC 24 |
| Peak memory | 260560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324262449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1324262449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1973051900 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 37243850 ps |
| CPU time | 7.43 seconds |
| Started | Oct 15 08:14:44 AM UTC 24 |
| Finished | Oct 15 08:14:53 AM UTC 24 |
| Peak memory | 264716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973051900 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_mem _rw_with_rand_reset.1973051900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.2571107787 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 189448126 ps |
| CPU time | 7.73 seconds |
| Started | Oct 15 08:14:41 AM UTC 24 |
| Finished | Oct 15 08:14:50 AM UTC 24 |
| Peak memory | 248132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571107787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2571107787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.1507705653 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 19951532 ps |
| CPU time | 2.11 seconds |
| Started | Oct 15 08:14:40 AM UTC 24 |
| Finished | Oct 15 08:14:43 AM UTC 24 |
| Peak memory | 248008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507705653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1507705653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3263622101 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 166524875 ps |
| CPU time | 14.33 seconds |
| Started | Oct 15 08:14:43 AM UTC 24 |
| Finished | Oct 15 08:14:59 AM UTC 24 |
| Peak memory | 250184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263622101 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outstanding.3263622101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3458141491 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 6173465336 ps |
| CPU time | 179.24 seconds |
| Started | Oct 15 08:14:30 AM UTC 24 |
| Finished | Oct 15 08:17:32 AM UTC 24 |
| Peak memory | 277124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458141491 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.3458141491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.381703221 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 25648212088 ps |
| CPU time | 485.99 seconds |
| Started | Oct 15 08:14:28 AM UTC 24 |
| Finished | Oct 15 08:22:40 AM UTC 24 |
| Peak memory | 279172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381703221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shado w_reg_errors_with_csr_rw.381703221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.3621657391 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 785031193 ps |
| CPU time | 21.87 seconds |
| Started | Oct 15 08:14:30 AM UTC 24 |
| Finished | Oct 15 08:14:53 AM UTC 24 |
| Peak memory | 260432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621657391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3621657391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3194985295 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 81746229 ps |
| CPU time | 9.78 seconds |
| Started | Oct 15 08:15:04 AM UTC 24 |
| Finished | Oct 15 08:15:15 AM UTC 24 |
| Peak memory | 250176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194985295 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_mem _rw_with_rand_reset.3194985295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.2730705793 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 73681070 ps |
| CPU time | 8.39 seconds |
| Started | Oct 15 08:15:01 AM UTC 24 |
| Finished | Oct 15 08:15:11 AM UTC 24 |
| Peak memory | 248060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730705793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2730705793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.2270882287 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 6773256 ps |
| CPU time | 2.31 seconds |
| Started | Oct 15 08:15:00 AM UTC 24 |
| Finished | Oct 15 08:15:03 AM UTC 24 |
| Peak memory | 248084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270882287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2270882287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1199212629 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 1074682781 ps |
| CPU time | 21.84 seconds |
| Started | Oct 15 08:15:02 AM UTC 24 |
| Finished | Oct 15 08:15:25 AM UTC 24 |
| Peak memory | 258308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199212629 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outstanding.1199212629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.2029727541 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 661252778 ps |
| CPU time | 18 seconds |
| Started | Oct 15 08:14:55 AM UTC 24 |
| Finished | Oct 15 08:15:14 AM UTC 24 |
| Peak memory | 260560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029727541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2029727541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.401085264 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 128025460 ps |
| CPU time | 7.99 seconds |
| Started | Oct 15 08:15:34 AM UTC 24 |
| Finished | Oct 15 08:15:43 AM UTC 24 |
| Peak memory | 250180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401085264 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_mem_ rw_with_rand_reset.401085264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.81786180 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 210384501 ps |
| CPU time | 6.63 seconds |
| Started | Oct 15 08:15:26 AM UTC 24 |
| Finished | Oct 15 08:15:33 AM UTC 24 |
| Peak memory | 248264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81786180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_han dler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.81786180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.3975170133 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 12252061 ps |
| CPU time | 1.97 seconds |
| Started | Oct 15 08:15:21 AM UTC 24 |
| Finished | Oct 15 08:15:24 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975170133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3975170133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2864312275 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 4062870026 ps |
| CPU time | 31.54 seconds |
| Started | Oct 15 08:15:27 AM UTC 24 |
| Finished | Oct 15 08:16:00 AM UTC 24 |
| Peak memory | 260416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864312275 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outstanding.2864312275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3855242678 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3067126795 ps |
| CPU time | 97.35 seconds |
| Started | Oct 15 08:15:14 AM UTC 24 |
| Finished | Oct 15 08:16:53 AM UTC 24 |
| Peak memory | 279168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855242678 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.3855242678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1530484968 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 68288768207 ps |
| CPU time | 1258.82 seconds |
| Started | Oct 15 08:15:11 AM UTC 24 |
| Finished | Oct 15 08:36:25 AM UTC 24 |
| Peak memory | 279688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530484968 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shad ow_reg_errors_with_csr_rw.1530484968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.1850532401 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 1310729168 ps |
| CPU time | 27.53 seconds |
| Started | Oct 15 08:15:15 AM UTC 24 |
| Finished | Oct 15 08:15:44 AM UTC 24 |
| Peak memory | 266500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850532401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1850532401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2383511417 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 45975093 ps |
| CPU time | 3.64 seconds |
| Started | Oct 15 08:15:16 AM UTC 24 |
| Finished | Oct 15 08:15:21 AM UTC 24 |
| Peak memory | 248256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383511417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2383511417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3668948159 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 154642364 ps |
| CPU time | 11.11 seconds |
| Started | Oct 15 08:16:10 AM UTC 24 |
| Finished | Oct 15 08:16:22 AM UTC 24 |
| Peak memory | 250180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668948159 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_mem _rw_with_rand_reset.3668948159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.1176394418 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 216269802 ps |
| CPU time | 7.46 seconds |
| Started | Oct 15 08:16:00 AM UTC 24 |
| Finished | Oct 15 08:16:09 AM UTC 24 |
| Peak memory | 250180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176394418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1176394418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.790074312 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 23983484 ps |
| CPU time | 1.88 seconds |
| Started | Oct 15 08:15:59 AM UTC 24 |
| Finished | Oct 15 08:16:02 AM UTC 24 |
| Peak memory | 244740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790074312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.790074312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3680164420 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 6124751579 ps |
| CPU time | 49.36 seconds |
| Started | Oct 15 08:16:03 AM UTC 24 |
| Finished | Oct 15 08:16:54 AM UTC 24 |
| Peak memory | 258372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680164420 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outstanding.3680164420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2919810261 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 9229019159 ps |
| CPU time | 333.62 seconds |
| Started | Oct 15 08:15:38 AM UTC 24 |
| Finished | Oct 15 08:21:16 AM UTC 24 |
| Peak memory | 277124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919810261 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shad ow_reg_errors_with_csr_rw.2919810261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.2716580626 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 37606681 ps |
| CPU time | 7.78 seconds |
| Started | Oct 15 08:15:45 AM UTC 24 |
| Finished | Oct 15 08:15:54 AM UTC 24 |
| Peak memory | 264528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716580626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2716580626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1556913588 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 5472521997 ps |
| CPU time | 105.61 seconds |
| Started | Oct 15 08:07:56 AM UTC 24 |
| Finished | Oct 15 08:09:43 AM UTC 24 |
| Peak memory | 250440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556913588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1556913588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2827361872 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 848423843 ps |
| CPU time | 122.96 seconds |
| Started | Oct 15 08:07:49 AM UTC 24 |
| Finished | Oct 15 08:09:55 AM UTC 24 |
| Peak memory | 248268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827361872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2827361872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2621476981 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 56161917 ps |
| CPU time | 8.13 seconds |
| Started | Oct 15 08:07:46 AM UTC 24 |
| Finished | Oct 15 08:07:55 AM UTC 24 |
| Peak memory | 262400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621476981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2621476981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1028670695 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 506872526 ps |
| CPU time | 15.24 seconds |
| Started | Oct 15 08:08:03 AM UTC 24 |
| Finished | Oct 15 08:08:19 AM UTC 24 |
| Peak memory | 266564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028670695 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_ rw_with_rand_reset.1028670695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_rw.2189572616 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 183290245 ps |
| CPU time | 10.98 seconds |
| Started | Oct 15 08:07:49 AM UTC 24 |
| Finished | Oct 15 08:08:02 AM UTC 24 |
| Peak memory | 250180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189572616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2189572616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_intr_test.2628723196 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 10764270 ps |
| CPU time | 2.26 seconds |
| Started | Oct 15 08:07:45 AM UTC 24 |
| Finished | Oct 15 08:07:48 AM UTC 24 |
| Peak memory | 248084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628723196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2628723196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3807774938 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 368028669 ps |
| CPU time | 12.61 seconds |
| Started | Oct 15 08:08:02 AM UTC 24 |
| Finished | Oct 15 08:08:15 AM UTC 24 |
| Peak memory | 260420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807774938 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.3807774938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.337227630 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 12091730258 ps |
| CPU time | 162.29 seconds |
| Started | Oct 15 08:07:16 AM UTC 24 |
| Finished | Oct 15 08:10:01 AM UTC 24 |
| Peak memory | 277128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337227630 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.337227630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_errors.1502943476 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1019813237 ps |
| CPU time | 21.12 seconds |
| Started | Oct 15 08:07:22 AM UTC 24 |
| Finished | Oct 15 08:07:44 AM UTC 24 |
| Peak memory | 264452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502943476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1502943476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.1505877067 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 52364179 ps |
| CPU time | 2.37 seconds |
| Started | Oct 15 08:16:23 AM UTC 24 |
| Finished | Oct 15 08:16:26 AM UTC 24 |
| Peak memory | 248008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505877067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1505877067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/20.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.2107225810 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 12713088 ps |
| CPU time | 2.12 seconds |
| Started | Oct 15 08:16:27 AM UTC 24 |
| Finished | Oct 15 08:16:30 AM UTC 24 |
| Peak memory | 248008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107225810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2107225810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/21.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.1663459401 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 6886591 ps |
| CPU time | 2.14 seconds |
| Started | Oct 15 08:16:31 AM UTC 24 |
| Finished | Oct 15 08:16:34 AM UTC 24 |
| Peak memory | 248008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663459401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1663459401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/22.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.3773544918 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 7370648 ps |
| CPU time | 1.99 seconds |
| Started | Oct 15 08:16:32 AM UTC 24 |
| Finished | Oct 15 08:16:36 AM UTC 24 |
| Peak memory | 244744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773544918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3773544918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/23.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.290040470 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 6709113 ps |
| CPU time | 2.11 seconds |
| Started | Oct 15 08:16:33 AM UTC 24 |
| Finished | Oct 15 08:16:37 AM UTC 24 |
| Peak memory | 248008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290040470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.290040470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/24.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.3573354432 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 11557305 ps |
| CPU time | 2.54 seconds |
| Started | Oct 15 08:16:36 AM UTC 24 |
| Finished | Oct 15 08:16:39 AM UTC 24 |
| Peak memory | 248008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573354432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3573354432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/25.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.2357446005 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 9592172 ps |
| CPU time | 2.15 seconds |
| Started | Oct 15 08:16:37 AM UTC 24 |
| Finished | Oct 15 08:16:40 AM UTC 24 |
| Peak memory | 245960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357446005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2357446005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/26.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.3786119969 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 6720662 ps |
| CPU time | 2.07 seconds |
| Started | Oct 15 08:16:38 AM UTC 24 |
| Finished | Oct 15 08:16:41 AM UTC 24 |
| Peak memory | 248080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786119969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3786119969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/27.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.665651600 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 6895139 ps |
| CPU time | 2.35 seconds |
| Started | Oct 15 08:16:40 AM UTC 24 |
| Finished | Oct 15 08:16:43 AM UTC 24 |
| Peak memory | 248076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665651600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.665651600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/28.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.2459978980 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 9624366 ps |
| CPU time | 2.36 seconds |
| Started | Oct 15 08:16:41 AM UTC 24 |
| Finished | Oct 15 08:16:44 AM UTC 24 |
| Peak memory | 248016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459978980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2459978980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/29.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3155111222 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 1390257238 ps |
| CPU time | 189.49 seconds |
| Started | Oct 15 08:08:46 AM UTC 24 |
| Finished | Oct 15 08:11:58 AM UTC 24 |
| Peak memory | 250316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155111222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3155111222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3486987107 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 5820903392 ps |
| CPU time | 355.16 seconds |
| Started | Oct 15 08:08:40 AM UTC 24 |
| Finished | Oct 15 08:14:39 AM UTC 24 |
| Peak memory | 248132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486987107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3486987107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2279477222 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 66035073 ps |
| CPU time | 9.48 seconds |
| Started | Oct 15 08:08:34 AM UTC 24 |
| Finished | Oct 15 08:08:45 AM UTC 24 |
| Peak memory | 260556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279477222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2279477222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1256365760 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 103281257 ps |
| CPU time | 7.59 seconds |
| Started | Oct 15 08:08:49 AM UTC 24 |
| Finished | Oct 15 08:08:58 AM UTC 24 |
| Peak memory | 250176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256365760 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_ rw_with_rand_reset.1256365760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_intr_test.1629672826 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 8736033 ps |
| CPU time | 2.41 seconds |
| Started | Oct 15 08:08:32 AM UTC 24 |
| Finished | Oct 15 08:08:36 AM UTC 24 |
| Peak memory | 248080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629672826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1629672826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2231606331 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 264289608 ps |
| CPU time | 33.19 seconds |
| Started | Oct 15 08:08:48 AM UTC 24 |
| Finished | Oct 15 08:09:22 AM UTC 24 |
| Peak memory | 258564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231606331 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.2231606331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.987207162 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 7998919561 ps |
| CPU time | 273.99 seconds |
| Started | Oct 15 08:08:20 AM UTC 24 |
| Finished | Oct 15 08:12:58 AM UTC 24 |
| Peak memory | 277128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987207162 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.987207162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1761685476 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 28729810000 ps |
| CPU time | 1050.94 seconds |
| Started | Oct 15 08:08:16 AM UTC 24 |
| Finished | Oct 15 08:26:00 AM UTC 24 |
| Peak memory | 277200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761685476 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shado w_reg_errors_with_csr_rw.1761685476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_errors.2806158345 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 211987461 ps |
| CPU time | 12.08 seconds |
| Started | Oct 15 08:08:25 AM UTC 24 |
| Finished | Oct 15 08:08:38 AM UTC 24 |
| Peak memory | 260556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806158345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2806158345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.629784310 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 12154578 ps |
| CPU time | 2.15 seconds |
| Started | Oct 15 08:16:42 AM UTC 24 |
| Finished | Oct 15 08:16:45 AM UTC 24 |
| Peak memory | 248008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629784310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.629784310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/30.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.2238042718 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 8982559 ps |
| CPU time | 2.36 seconds |
| Started | Oct 15 08:16:44 AM UTC 24 |
| Finished | Oct 15 08:16:48 AM UTC 24 |
| Peak memory | 246160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238042718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2238042718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/31.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.1061507686 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 11422142 ps |
| CPU time | 2.15 seconds |
| Started | Oct 15 08:16:45 AM UTC 24 |
| Finished | Oct 15 08:16:49 AM UTC 24 |
| Peak memory | 248012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061507686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1061507686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/32.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.2990375402 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 20850587 ps |
| CPU time | 2.05 seconds |
| Started | Oct 15 08:16:46 AM UTC 24 |
| Finished | Oct 15 08:16:50 AM UTC 24 |
| Peak memory | 246160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990375402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2990375402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/33.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.1715104804 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 8644094 ps |
| CPU time | 2.68 seconds |
| Started | Oct 15 08:16:49 AM UTC 24 |
| Finished | Oct 15 08:16:52 AM UTC 24 |
| Peak memory | 248004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715104804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1715104804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/34.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.103145765 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 16936944 ps |
| CPU time | 2 seconds |
| Started | Oct 15 08:16:50 AM UTC 24 |
| Finished | Oct 15 08:16:53 AM UTC 24 |
| Peak memory | 244744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103145765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.103145765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/35.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.2917068146 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 7824885 ps |
| CPU time | 1.98 seconds |
| Started | Oct 15 08:16:50 AM UTC 24 |
| Finished | Oct 15 08:16:53 AM UTC 24 |
| Peak memory | 244744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917068146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2917068146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/36.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.2689778773 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 11054443 ps |
| CPU time | 2.14 seconds |
| Started | Oct 15 08:16:51 AM UTC 24 |
| Finished | Oct 15 08:16:54 AM UTC 24 |
| Peak memory | 246160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689778773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2689778773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/37.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.3302118228 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 6910763 ps |
| CPU time | 2.25 seconds |
| Started | Oct 15 08:16:53 AM UTC 24 |
| Finished | Oct 15 08:16:56 AM UTC 24 |
| Peak memory | 248084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302118228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3302118228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/38.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.627144415 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 7522880 ps |
| CPU time | 2.45 seconds |
| Started | Oct 15 08:16:54 AM UTC 24 |
| Finished | Oct 15 08:16:58 AM UTC 24 |
| Peak memory | 248208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627144415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.627144415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/39.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.953776615 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 4090651762 ps |
| CPU time | 237.45 seconds |
| Started | Oct 15 08:09:32 AM UTC 24 |
| Finished | Oct 15 08:13:34 AM UTC 24 |
| Peak memory | 250176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953776615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/al ert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.953776615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2440853526 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 11437384393 ps |
| CPU time | 422.48 seconds |
| Started | Oct 15 08:09:23 AM UTC 24 |
| Finished | Oct 15 08:16:31 AM UTC 24 |
| Peak memory | 248136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440853526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2440853526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3214468326 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 115680591 ps |
| CPU time | 8.46 seconds |
| Started | Oct 15 08:09:22 AM UTC 24 |
| Finished | Oct 15 08:09:32 AM UTC 24 |
| Peak memory | 250320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214468326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3214468326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.41261335 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 65470799 ps |
| CPU time | 8.13 seconds |
| Started | Oct 15 08:09:45 AM UTC 24 |
| Finished | Oct 15 08:09:54 AM UTC 24 |
| Peak memory | 250180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41261335 -assert nop ostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_rw _with_rand_reset.41261335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_rw.2535596515 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 124795183 ps |
| CPU time | 8.09 seconds |
| Started | Oct 15 08:09:23 AM UTC 24 |
| Finished | Oct 15 08:09:32 AM UTC 24 |
| Peak memory | 250108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535596515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2535596515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1937644893 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2147376715 ps |
| CPU time | 58.62 seconds |
| Started | Oct 15 08:09:34 AM UTC 24 |
| Finished | Oct 15 08:10:34 AM UTC 24 |
| Peak memory | 258504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937644893 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.1937644893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.669152675 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 2668670711 ps |
| CPU time | 246.44 seconds |
| Started | Oct 15 08:09:02 AM UTC 24 |
| Finished | Oct 15 08:13:12 AM UTC 24 |
| Peak memory | 277332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669152675 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.669152675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_errors.1904561868 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 280474416 ps |
| CPU time | 14.38 seconds |
| Started | Oct 15 08:09:02 AM UTC 24 |
| Finished | Oct 15 08:09:17 AM UTC 24 |
| Peak memory | 260360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904561868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1904561868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.2963278265 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 8437945 ps |
| CPU time | 2.01 seconds |
| Started | Oct 15 08:16:54 AM UTC 24 |
| Finished | Oct 15 08:16:57 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963278265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2963278265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/40.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.1464195190 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 10978392 ps |
| CPU time | 1.98 seconds |
| Started | Oct 15 08:16:54 AM UTC 24 |
| Finished | Oct 15 08:16:57 AM UTC 24 |
| Peak memory | 244744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464195190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1464195190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/41.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.3122599107 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 14380633 ps |
| CPU time | 1.99 seconds |
| Started | Oct 15 08:16:54 AM UTC 24 |
| Finished | Oct 15 08:16:57 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122599107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3122599107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/42.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.923081509 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 10564161 ps |
| CPU time | 2.37 seconds |
| Started | Oct 15 08:16:54 AM UTC 24 |
| Finished | Oct 15 08:16:58 AM UTC 24 |
| Peak memory | 248208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923081509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.923081509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/43.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.1708309263 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 11973275 ps |
| CPU time | 2.25 seconds |
| Started | Oct 15 08:16:56 AM UTC 24 |
| Finished | Oct 15 08:16:59 AM UTC 24 |
| Peak memory | 246032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708309263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1708309263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/44.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.1871593081 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 7621204 ps |
| CPU time | 2.42 seconds |
| Started | Oct 15 08:16:57 AM UTC 24 |
| Finished | Oct 15 08:17:00 AM UTC 24 |
| Peak memory | 248208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871593081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1871593081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/45.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.889588524 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 10110834 ps |
| CPU time | 2.46 seconds |
| Started | Oct 15 08:16:58 AM UTC 24 |
| Finished | Oct 15 08:17:02 AM UTC 24 |
| Peak memory | 247648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889588524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.889588524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/46.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.3411227805 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 43536225 ps |
| CPU time | 2.09 seconds |
| Started | Oct 15 08:16:58 AM UTC 24 |
| Finished | Oct 15 08:17:01 AM UTC 24 |
| Peak memory | 247888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411227805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3411227805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/47.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.4069093936 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 23438971 ps |
| CPU time | 2.14 seconds |
| Started | Oct 15 08:16:58 AM UTC 24 |
| Finished | Oct 15 08:17:01 AM UTC 24 |
| Peak memory | 248008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069093936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.4069093936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/48.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.168288419 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 7318412 ps |
| CPU time | 1.98 seconds |
| Started | Oct 15 08:16:59 AM UTC 24 |
| Finished | Oct 15 08:17:02 AM UTC 24 |
| Peak memory | 246724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168288419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.168288419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/49.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.94826387 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 265133629 ps |
| CPU time | 7.4 seconds |
| Started | Oct 15 08:10:25 AM UTC 24 |
| Finished | Oct 15 08:10:34 AM UTC 24 |
| Peak memory | 260488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94826387 -assert nop ostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_mem_rw _with_rand_reset.94826387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_rw.2438087972 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 50595191 ps |
| CPU time | 7.36 seconds |
| Started | Oct 15 08:10:16 AM UTC 24 |
| Finished | Oct 15 08:10:25 AM UTC 24 |
| Peak memory | 248064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438087972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2438087972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_intr_test.2805485303 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 24129035 ps |
| CPU time | 2.33 seconds |
| Started | Oct 15 08:10:15 AM UTC 24 |
| Finished | Oct 15 08:10:18 AM UTC 24 |
| Peak memory | 248008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805485303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2805485303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1004192000 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3570541887 ps |
| CPU time | 58.52 seconds |
| Started | Oct 15 08:10:19 AM UTC 24 |
| Finished | Oct 15 08:11:20 AM UTC 24 |
| Peak memory | 258436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004192000 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outstanding.1004192000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2015562286 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 7823782947 ps |
| CPU time | 131.69 seconds |
| Started | Oct 15 08:09:56 AM UTC 24 |
| Finished | Oct 15 08:12:10 AM UTC 24 |
| Peak memory | 266888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015562286 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.2015562286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_errors.3786711901 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 202638836 ps |
| CPU time | 12.46 seconds |
| Started | Oct 15 08:10:02 AM UTC 24 |
| Finished | Oct 15 08:10:16 AM UTC 24 |
| Peak memory | 260360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786711901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3786711901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3046432976 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 76868513 ps |
| CPU time | 10.47 seconds |
| Started | Oct 15 08:11:00 AM UTC 24 |
| Finished | Oct 15 08:11:11 AM UTC 24 |
| Peak memory | 266764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046432976 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_mem_ rw_with_rand_reset.3046432976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_rw.2297115276 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 96790001 ps |
| CPU time | 10.6 seconds |
| Started | Oct 15 08:10:46 AM UTC 24 |
| Finished | Oct 15 08:10:58 AM UTC 24 |
| Peak memory | 248264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297115276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2297115276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_intr_test.2634542049 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 19606867 ps |
| CPU time | 3.02 seconds |
| Started | Oct 15 08:10:41 AM UTC 24 |
| Finished | Oct 15 08:10:45 AM UTC 24 |
| Peak memory | 248272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634542049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2634542049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1907798926 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 340732751 ps |
| CPU time | 30.59 seconds |
| Started | Oct 15 08:10:58 AM UTC 24 |
| Finished | Oct 15 08:11:30 AM UTC 24 |
| Peak memory | 258372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907798926 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outstanding.1907798926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.154378830 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 3581283797 ps |
| CPU time | 114.04 seconds |
| Started | Oct 15 08:10:36 AM UTC 24 |
| Finished | Oct 15 08:12:32 AM UTC 24 |
| Peak memory | 277128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154378830 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.154378830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2138034677 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 37898660166 ps |
| CPU time | 718.66 seconds |
| Started | Oct 15 08:10:33 AM UTC 24 |
| Finished | Oct 15 08:22:41 AM UTC 24 |
| Peak memory | 283276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138034677 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shado w_reg_errors_with_csr_rw.2138034677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_errors.175406030 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 415780928 ps |
| CPU time | 31.76 seconds |
| Started | Oct 15 08:10:36 AM UTC 24 |
| Finished | Oct 15 08:11:09 AM UTC 24 |
| Peak memory | 266496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175406030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.175406030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3131263054 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 1329133583 ps |
| CPU time | 11.57 seconds |
| Started | Oct 15 08:11:26 AM UTC 24 |
| Finished | Oct 15 08:11:39 AM UTC 24 |
| Peak memory | 250176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131263054 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_mem_ rw_with_rand_reset.3131263054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_rw.831041081 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 907792777 ps |
| CPU time | 6.97 seconds |
| Started | Oct 15 08:11:25 AM UTC 24 |
| Finished | Oct 15 08:11:34 AM UTC 24 |
| Peak memory | 250304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831041081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.831041081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_intr_test.2985963791 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 6462905 ps |
| CPU time | 1.82 seconds |
| Started | Oct 15 08:11:23 AM UTC 24 |
| Finished | Oct 15 08:11:25 AM UTC 24 |
| Peak memory | 246856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985963791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2985963791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1618142415 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 255495713 ps |
| CPU time | 29.67 seconds |
| Started | Oct 15 08:11:26 AM UTC 24 |
| Finished | Oct 15 08:11:58 AM UTC 24 |
| Peak memory | 260348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618142415 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outstanding.1618142415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1944365212 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 17872284750 ps |
| CPU time | 866.94 seconds |
| Started | Oct 15 08:11:10 AM UTC 24 |
| Finished | Oct 15 08:25:48 AM UTC 24 |
| Peak memory | 277128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944365212 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shado w_reg_errors_with_csr_rw.1944365212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_errors.103587748 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 242821010 ps |
| CPU time | 11.35 seconds |
| Started | Oct 15 08:11:12 AM UTC 24 |
| Finished | Oct 15 08:11:25 AM UTC 24 |
| Peak memory | 260356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103587748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.103587748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2791684074 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 91287840 ps |
| CPU time | 8.59 seconds |
| Started | Oct 15 08:11:59 AM UTC 24 |
| Finished | Oct 15 08:12:09 AM UTC 24 |
| Peak memory | 250180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791684074 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_mem_ rw_with_rand_reset.2791684074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_rw.958120361 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 178507550 ps |
| CPU time | 7.17 seconds |
| Started | Oct 15 08:11:53 AM UTC 24 |
| Finished | Oct 15 08:12:01 AM UTC 24 |
| Peak memory | 248060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958120361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.958120361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_intr_test.3138884847 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 17897120 ps |
| CPU time | 2.24 seconds |
| Started | Oct 15 08:11:49 AM UTC 24 |
| Finished | Oct 15 08:11:52 AM UTC 24 |
| Peak memory | 248140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138884847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3138884847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2775353308 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 423763674 ps |
| CPU time | 35.48 seconds |
| Started | Oct 15 08:11:58 AM UTC 24 |
| Finished | Oct 15 08:12:35 AM UTC 24 |
| Peak memory | 260348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775353308 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outstanding.2775353308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_errors.2575877717 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 791291410 ps |
| CPU time | 21.56 seconds |
| Started | Oct 15 08:11:35 AM UTC 24 |
| Finished | Oct 15 08:11:58 AM UTC 24 |
| Peak memory | 260360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575877717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2575877717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1442912861 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 168064975 ps |
| CPU time | 13.73 seconds |
| Started | Oct 15 08:12:14 AM UTC 24 |
| Finished | Oct 15 08:12:29 AM UTC 24 |
| Peak memory | 262540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442912861 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_mem_ rw_with_rand_reset.1442912861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_rw.313670451 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 128701049 ps |
| CPU time | 12.14 seconds |
| Started | Oct 15 08:12:11 AM UTC 24 |
| Finished | Oct 15 08:12:24 AM UTC 24 |
| Peak memory | 250104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313670451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.313670451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_intr_test.1023194010 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 12327500 ps |
| CPU time | 2.03 seconds |
| Started | Oct 15 08:12:10 AM UTC 24 |
| Finished | Oct 15 08:12:13 AM UTC 24 |
| Peak memory | 248272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023194010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1023194010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1869188555 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 919856536 ps |
| CPU time | 54.29 seconds |
| Started | Oct 15 08:12:14 AM UTC 24 |
| Finished | Oct 15 08:13:10 AM UTC 24 |
| Peak memory | 260348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869188555 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outstanding.1869188555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2219326017 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 20783892705 ps |
| CPU time | 733.34 seconds |
| Started | Oct 15 08:11:59 AM UTC 24 |
| Finished | Oct 15 08:24:22 AM UTC 24 |
| Peak memory | 277124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219326017 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shado w_reg_errors_with_csr_rw.2219326017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_errors.1268173588 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 578551244 ps |
| CPU time | 15.25 seconds |
| Started | Oct 15 08:12:02 AM UTC 24 |
| Finished | Oct 15 08:12:19 AM UTC 24 |
| Peak memory | 260360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268173588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1268173588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_intg_err.757246286 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 87642220 ps |
| CPU time | 3.87 seconds |
| Started | Oct 15 08:12:09 AM UTC 24 |
| Finished | Oct 15 08:12:14 AM UTC 24 |
| Peak memory | 248260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757246286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.757246286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy_stress.591965658 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1163651659 ps |
| CPU time | 20.99 seconds |
| Started | Oct 15 06:21:12 AM UTC 24 |
| Finished | Oct 15 06:21:34 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591965658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.591965658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_intr_timeout.1904541799 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 762200445 ps |
| CPU time | 46.26 seconds |
| Started | Oct 15 06:20:53 AM UTC 24 |
| Finished | Oct 15 06:21:41 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904541799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1904541799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg_stub_clk.2998780521 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 31643195730 ps |
| CPU time | 2536.22 seconds |
| Started | Oct 15 06:21:06 AM UTC 24 |
| Finished | Oct 15 07:03:51 AM UTC 24 |
| Peak memory | 293600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998780521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2998780521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_alerts.1467529730 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2468321389 ps |
| CPU time | 44.29 seconds |
| Started | Oct 15 06:20:52 AM UTC 24 |
| Finished | Oct 15 06:21:38 AM UTC 24 |
| Peak memory | 260824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467529730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1467529730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/0.alert_handler_sec_cm.2923623465 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 699874945 ps |
| CPU time | 22.72 seconds |
| Started | Oct 15 06:21:17 AM UTC 24 |
| Finished | Oct 15 06:21:41 AM UTC 24 |
| Peak memory | 292944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923623465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2923623465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/0.alert_handler_sig_int_fail.813647848 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 901316886 ps |
| CPU time | 29.87 seconds |
| Started | Oct 15 06:21:00 AM UTC 24 |
| Finished | Oct 15 06:21:31 AM UTC 24 |
| Peak memory | 266896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813647848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.813647848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/0.alert_handler_smoke.1322745681 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1088742350 ps |
| CPU time | 40.82 seconds |
| Started | Oct 15 06:20:52 AM UTC 24 |
| Finished | Oct 15 06:21:34 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322745681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1322745681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/0.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_alert_accum.564939730 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 10617195694 ps |
| CPU time | 244.74 seconds |
| Started | Oct 15 06:21:25 AM UTC 24 |
| Finished | Oct 15 06:25:33 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564939730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.564939730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_intr_timeout.1202481822 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 495599899 ps |
| CPU time | 34.41 seconds |
| Started | Oct 15 06:21:21 AM UTC 24 |
| Finished | Oct 15 06:21:57 AM UTC 24 |
| Peak memory | 266896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202481822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1202481822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg_stub_clk.3085920017 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 8700823783 ps |
| CPU time | 686.05 seconds |
| Started | Oct 15 06:21:31 AM UTC 24 |
| Finished | Oct 15 06:33:06 AM UTC 24 |
| Peak memory | 277552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085920017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3085920017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/1.alert_handler_ping_timeout.3496092459 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 6822483194 ps |
| CPU time | 140.36 seconds |
| Started | Oct 15 06:21:29 AM UTC 24 |
| Finished | Oct 15 06:23:53 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496092459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3496092459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/1.alert_handler_smoke.1869521476 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 597376879 ps |
| CPU time | 29.93 seconds |
| Started | Oct 15 06:21:17 AM UTC 24 |
| Finished | Oct 15 06:21:48 AM UTC 24 |
| Peak memory | 266916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869521476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1869521476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all.3590348013 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 54918806678 ps |
| CPU time | 1497.23 seconds |
| Started | Oct 15 06:21:32 AM UTC 24 |
| Finished | Oct 15 06:46:47 AM UTC 24 |
| Peak memory | 300020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590348013 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all.3590348013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/1.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy.51368018 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 94701172224 ps |
| CPU time | 2143.73 seconds |
| Started | Oct 15 06:27:33 AM UTC 24 |
| Finished | Oct 15 07:03:42 AM UTC 24 |
| Peak memory | 283688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51368018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/a lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.51368018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy_stress.3437479892 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2529726052 ps |
| CPU time | 30.77 seconds |
| Started | Oct 15 06:27:51 AM UTC 24 |
| Finished | Oct 15 06:28:23 AM UTC 24 |
| Peak memory | 260900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437479892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3437479892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_alert_accum.3203569357 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 15806920203 ps |
| CPU time | 172.45 seconds |
| Started | Oct 15 06:27:26 AM UTC 24 |
| Finished | Oct 15 06:30:21 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203569357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3203569357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_intr_timeout.883165586 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 6585910204 ps |
| CPU time | 67.76 seconds |
| Started | Oct 15 06:27:14 AM UTC 24 |
| Finished | Oct 15 06:28:23 AM UTC 24 |
| Peak memory | 260928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883165586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.883165586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg.3086645713 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 77648315455 ps |
| CPU time | 2357.2 seconds |
| Started | Oct 15 06:27:42 AM UTC 24 |
| Finished | Oct 15 07:07:26 AM UTC 24 |
| Peak memory | 283624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086645713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3086645713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg_stub_clk.1158228342 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 19708606143 ps |
| CPU time | 915.77 seconds |
| Started | Oct 15 06:27:46 AM UTC 24 |
| Finished | Oct 15 06:43:12 AM UTC 24 |
| Peak memory | 283380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158228342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1158228342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_alerts.2570309437 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2305126770 ps |
| CPU time | 23.41 seconds |
| Started | Oct 15 06:27:07 AM UTC 24 |
| Finished | Oct 15 06:27:32 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570309437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2570309437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_classes.716963528 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 942490360 ps |
| CPU time | 28.31 seconds |
| Started | Oct 15 06:27:11 AM UTC 24 |
| Finished | Oct 15 06:27:41 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716963528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.716963528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/10.alert_handler_sig_int_fail.3101849655 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 630300995 ps |
| CPU time | 15.32 seconds |
| Started | Oct 15 06:27:33 AM UTC 24 |
| Finished | Oct 15 06:27:50 AM UTC 24 |
| Peak memory | 264856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101849655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3101849655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/10.alert_handler_smoke.593578345 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 444345676 ps |
| CPU time | 9.27 seconds |
| Started | Oct 15 06:26:56 AM UTC 24 |
| Finished | Oct 15 06:27:06 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593578345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.593578345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all.3916710843 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 1508064815 ps |
| CPU time | 55.53 seconds |
| Started | Oct 15 06:28:21 AM UTC 24 |
| Finished | Oct 15 06:29:18 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916710843 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all.3916710843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/10.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/11.alert_handler_alert_accum_saturation.966320432 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 401058810 ps |
| CPU time | 5.17 seconds |
| Started | Oct 15 06:30:22 AM UTC 24 |
| Finished | Oct 15 06:30:28 AM UTC 24 |
| Peak memory | 260972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966320432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.966320432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy.270246957 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 7982881658 ps |
| CPU time | 1100.48 seconds |
| Started | Oct 15 06:29:29 AM UTC 24 |
| Finished | Oct 15 06:48:02 AM UTC 24 |
| Peak memory | 283624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270246957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.270246957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy_stress.3309392474 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 187843212 ps |
| CPU time | 16.81 seconds |
| Started | Oct 15 06:30:08 AM UTC 24 |
| Finished | Oct 15 06:30:26 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309392474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3309392474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_alert_accum.1342126165 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 10014002487 ps |
| CPU time | 186.24 seconds |
| Started | Oct 15 06:29:19 AM UTC 24 |
| Finished | Oct 15 06:32:29 AM UTC 24 |
| Peak memory | 263132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342126165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1342126165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_intr_timeout.1243792568 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 405451061 ps |
| CPU time | 47.1 seconds |
| Started | Oct 15 06:29:19 AM UTC 24 |
| Finished | Oct 15 06:30:08 AM UTC 24 |
| Peak memory | 267168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243792568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1243792568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg_stub_clk.3580544697 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 44733240249 ps |
| CPU time | 1104.02 seconds |
| Started | Oct 15 06:29:56 AM UTC 24 |
| Finished | Oct 15 06:48:32 AM UTC 24 |
| Peak memory | 283436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580544697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3580544697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/11.alert_handler_ping_timeout.2807883160 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 36108637586 ps |
| CPU time | 96.54 seconds |
| Started | Oct 15 06:29:37 AM UTC 24 |
| Finished | Oct 15 06:31:16 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807883160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2807883160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_alerts.489049428 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3108353796 ps |
| CPU time | 25.48 seconds |
| Started | Oct 15 06:28:52 AM UTC 24 |
| Finished | Oct 15 06:29:19 AM UTC 24 |
| Peak memory | 267076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489049428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.489049428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_classes.1480706849 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2348845961 ps |
| CPU time | 15.05 seconds |
| Started | Oct 15 06:29:19 AM UTC 24 |
| Finished | Oct 15 06:29:35 AM UTC 24 |
| Peak memory | 260892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480706849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1480706849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/11.alert_handler_sig_int_fail.2940419376 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 2088074446 ps |
| CPU time | 41.36 seconds |
| Started | Oct 15 06:29:28 AM UTC 24 |
| Finished | Oct 15 06:30:10 AM UTC 24 |
| Peak memory | 260896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940419376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2940419376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/11.alert_handler_smoke.3399291742 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1679563980 ps |
| CPU time | 45.32 seconds |
| Started | Oct 15 06:28:31 AM UTC 24 |
| Finished | Oct 15 06:29:18 AM UTC 24 |
| Peak memory | 266916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399291742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3399291742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all.1854330249 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 64067563510 ps |
| CPU time | 453.54 seconds |
| Started | Oct 15 06:30:11 AM UTC 24 |
| Finished | Oct 15 06:37:51 AM UTC 24 |
| Peak memory | 266968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854330249 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all.1854330249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/11.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy.1241103628 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 40673964991 ps |
| CPU time | 2272.24 seconds |
| Started | Oct 15 06:31:44 AM UTC 24 |
| Finished | Oct 15 07:10:00 AM UTC 24 |
| Peak memory | 293596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241103628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1241103628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy_stress.1102329853 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 385024466 ps |
| CPU time | 16.96 seconds |
| Started | Oct 15 06:32:03 AM UTC 24 |
| Finished | Oct 15 06:32:21 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102329853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1102329853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_alert_accum.2234186109 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 9627725375 ps |
| CPU time | 113.92 seconds |
| Started | Oct 15 06:31:17 AM UTC 24 |
| Finished | Oct 15 06:33:13 AM UTC 24 |
| Peak memory | 267292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234186109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2234186109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_intr_timeout.1283885545 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 470231345 ps |
| CPU time | 34.86 seconds |
| Started | Oct 15 06:31:17 AM UTC 24 |
| Finished | Oct 15 06:31:53 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283885545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1283885545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg_stub_clk.2316072280 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 41779025332 ps |
| CPU time | 1640.15 seconds |
| Started | Oct 15 06:31:54 AM UTC 24 |
| Finished | Oct 15 06:59:32 AM UTC 24 |
| Peak memory | 283708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316072280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2316072280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_alerts.3809085231 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 643697746 ps |
| CPU time | 47.29 seconds |
| Started | Oct 15 06:30:27 AM UTC 24 |
| Finished | Oct 15 06:31:16 AM UTC 24 |
| Peak memory | 267228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809085231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3809085231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_classes.3524483432 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1125893961 ps |
| CPU time | 75.75 seconds |
| Started | Oct 15 06:30:29 AM UTC 24 |
| Finished | Oct 15 06:31:47 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524483432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3524483432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/12.alert_handler_sig_int_fail.4050930083 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 788758276 ps |
| CPU time | 32.77 seconds |
| Started | Oct 15 06:31:17 AM UTC 24 |
| Finished | Oct 15 06:31:51 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050930083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.4050930083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/12.alert_handler_smoke.1483208400 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 4812138331 ps |
| CPU time | 76.53 seconds |
| Started | Oct 15 06:30:25 AM UTC 24 |
| Finished | Oct 15 06:31:43 AM UTC 24 |
| Peak memory | 267048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483208400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1483208400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/12.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/13.alert_handler_alert_accum_saturation.3455421224 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 37199119 ps |
| CPU time | 5.51 seconds |
| Started | Oct 15 06:35:25 AM UTC 24 |
| Finished | Oct 15 06:35:31 AM UTC 24 |
| Peak memory | 260968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455421224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3455421224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy.361941669 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 15301750061 ps |
| CPU time | 944.53 seconds |
| Started | Oct 15 06:33:58 AM UTC 24 |
| Finished | Oct 15 06:49:54 AM UTC 24 |
| Peak memory | 293604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361941669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.361941669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy_stress.1503926197 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 3334715395 ps |
| CPU time | 34.31 seconds |
| Started | Oct 15 06:34:51 AM UTC 24 |
| Finished | Oct 15 06:35:27 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503926197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1503926197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_alert_accum.2529952713 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 16635212123 ps |
| CPU time | 252.77 seconds |
| Started | Oct 15 06:33:51 AM UTC 24 |
| Finished | Oct 15 06:38:08 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529952713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2529952713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_intr_timeout.3993058359 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 242278999 ps |
| CPU time | 21.82 seconds |
| Started | Oct 15 06:33:34 AM UTC 24 |
| Finished | Oct 15 06:33:57 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993058359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3993058359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg.3989998450 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 68484981903 ps |
| CPU time | 2287.48 seconds |
| Started | Oct 15 06:34:17 AM UTC 24 |
| Finished | Oct 15 07:12:50 AM UTC 24 |
| Peak memory | 284856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989998450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3989998450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg_stub_clk.3264339180 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 101942996587 ps |
| CPU time | 2717.52 seconds |
| Started | Oct 15 06:34:29 AM UTC 24 |
| Finished | Oct 15 07:20:16 AM UTC 24 |
| Peak memory | 302232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264339180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3264339180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_alerts.2571123076 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 371004654 ps |
| CPU time | 46.9 seconds |
| Started | Oct 15 06:33:08 AM UTC 24 |
| Finished | Oct 15 06:33:56 AM UTC 24 |
| Peak memory | 267164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571123076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2571123076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_classes.1104337432 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1824608068 ps |
| CPU time | 72.23 seconds |
| Started | Oct 15 06:33:14 AM UTC 24 |
| Finished | Oct 15 06:34:28 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104337432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1104337432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/13.alert_handler_sig_int_fail.4093503753 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 3887030912 ps |
| CPU time | 84.92 seconds |
| Started | Oct 15 06:33:57 AM UTC 24 |
| Finished | Oct 15 06:35:24 AM UTC 24 |
| Peak memory | 267296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093503753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.4093503753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/13.alert_handler_smoke.4231902903 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 3312157636 ps |
| CPU time | 73.85 seconds |
| Started | Oct 15 06:32:35 AM UTC 24 |
| Finished | Oct 15 06:33:50 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231902903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.4231902903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all.2295124039 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 153924769242 ps |
| CPU time | 1654.8 seconds |
| Started | Oct 15 06:35:00 AM UTC 24 |
| Finished | Oct 15 07:02:54 AM UTC 24 |
| Peak memory | 300020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295124039 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all.2295124039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/13.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/14.alert_handler_alert_accum_saturation.3580169912 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 159497438 ps |
| CPU time | 5.53 seconds |
| Started | Oct 15 06:38:17 AM UTC 24 |
| Finished | Oct 15 06:38:23 AM UTC 24 |
| Peak memory | 261040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580169912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3580169912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy_stress.1265678866 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 262551206 ps |
| CPU time | 14.43 seconds |
| Started | Oct 15 06:38:00 AM UTC 24 |
| Finished | Oct 15 06:38:16 AM UTC 24 |
| Peak memory | 261028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265678866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1265678866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_alert_accum.2338591279 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 6112568464 ps |
| CPU time | 179.95 seconds |
| Started | Oct 15 06:36:28 AM UTC 24 |
| Finished | Oct 15 06:39:31 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338591279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2338591279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_intr_timeout.742056527 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1052658523 ps |
| CPU time | 90.19 seconds |
| Started | Oct 15 06:36:27 AM UTC 24 |
| Finished | Oct 15 06:38:00 AM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742056527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.742056527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg_stub_clk.3604356735 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 11487618764 ps |
| CPU time | 794.39 seconds |
| Started | Oct 15 06:37:52 AM UTC 24 |
| Finished | Oct 15 06:51:17 AM UTC 24 |
| Peak memory | 277500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604356735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3604356735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/14.alert_handler_ping_timeout.3302607789 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 9166015428 ps |
| CPU time | 535.45 seconds |
| Started | Oct 15 06:37:17 AM UTC 24 |
| Finished | Oct 15 06:46:19 AM UTC 24 |
| Peak memory | 260908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302607789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3302607789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_alerts.1420803653 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 235006824 ps |
| CPU time | 17.81 seconds |
| Started | Oct 15 06:35:50 AM UTC 24 |
| Finished | Oct 15 06:36:10 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420803653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1420803653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_classes.1622764405 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 533134344 ps |
| CPU time | 46.74 seconds |
| Started | Oct 15 06:36:10 AM UTC 24 |
| Finished | Oct 15 06:36:59 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622764405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1622764405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/14.alert_handler_smoke.878289180 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2751167720 ps |
| CPU time | 53.24 seconds |
| Started | Oct 15 06:35:32 AM UTC 24 |
| Finished | Oct 15 06:36:27 AM UTC 24 |
| Peak memory | 267296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878289180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.878289180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/14.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/15.alert_handler_alert_accum_saturation.644520337 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 32411903 ps |
| CPU time | 4.74 seconds |
| Started | Oct 15 06:42:08 AM UTC 24 |
| Finished | Oct 15 06:42:13 AM UTC 24 |
| Peak memory | 260972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644520337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.644520337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy.2635472203 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 113301035708 ps |
| CPU time | 1918.09 seconds |
| Started | Oct 15 06:39:55 AM UTC 24 |
| Finished | Oct 15 07:12:14 AM UTC 24 |
| Peak memory | 299816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635472203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2635472203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy_stress.4049040554 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 298394835 ps |
| CPU time | 24.72 seconds |
| Started | Oct 15 06:41:39 AM UTC 24 |
| Finished | Oct 15 06:42:05 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049040554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.4049040554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_alert_accum.3099988063 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 4978579288 ps |
| CPU time | 148.49 seconds |
| Started | Oct 15 06:39:36 AM UTC 24 |
| Finished | Oct 15 06:42:07 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099988063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3099988063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_intr_timeout.3135170986 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 566909620 ps |
| CPU time | 20.92 seconds |
| Started | Oct 15 06:39:33 AM UTC 24 |
| Finished | Oct 15 06:39:55 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135170986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3135170986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg.1360387556 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 35802914653 ps |
| CPU time | 2006.93 seconds |
| Started | Oct 15 06:40:01 AM UTC 24 |
| Finished | Oct 15 07:13:51 AM UTC 24 |
| Peak memory | 299760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360387556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1360387556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg_stub_clk.3982935486 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 37173792097 ps |
| CPU time | 2011.75 seconds |
| Started | Oct 15 06:40:30 AM UTC 24 |
| Finished | Oct 15 07:14:25 AM UTC 24 |
| Peak memory | 283436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982935486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3982935486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_alerts.2666180792 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 153586149 ps |
| CPU time | 22.48 seconds |
| Started | Oct 15 06:39:11 AM UTC 24 |
| Finished | Oct 15 06:39:35 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666180792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2666180792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_classes.2908642220 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 540571764 ps |
| CPU time | 27.67 seconds |
| Started | Oct 15 06:39:24 AM UTC 24 |
| Finished | Oct 15 06:39:52 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908642220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2908642220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/15.alert_handler_sig_int_fail.3936566892 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1351306268 ps |
| CPU time | 34.56 seconds |
| Started | Oct 15 06:39:53 AM UTC 24 |
| Finished | Oct 15 06:40:29 AM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936566892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3936566892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/15.alert_handler_smoke.1686105944 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1278004040 ps |
| CPU time | 45.56 seconds |
| Started | Oct 15 06:39:07 AM UTC 24 |
| Finished | Oct 15 06:39:54 AM UTC 24 |
| Peak memory | 266912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686105944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1686105944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all.3243914864 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 2501858377 ps |
| CPU time | 142.3 seconds |
| Started | Oct 15 06:42:06 AM UTC 24 |
| Finished | Oct 15 06:44:31 AM UTC 24 |
| Peak memory | 267044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243914864 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all.3243914864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/15.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/16.alert_handler_alert_accum_saturation.2069961645 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 35564981 ps |
| CPU time | 3.56 seconds |
| Started | Oct 15 06:45:21 AM UTC 24 |
| Finished | Oct 15 06:45:26 AM UTC 24 |
| Peak memory | 260968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069961645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2069961645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy.4085426769 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 57030781443 ps |
| CPU time | 1501.45 seconds |
| Started | Oct 15 06:43:29 AM UTC 24 |
| Finished | Oct 15 07:08:47 AM UTC 24 |
| Peak memory | 283432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085426769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.4085426769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy_stress.3350238418 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 615196142 ps |
| CPU time | 41.75 seconds |
| Started | Oct 15 06:44:44 AM UTC 24 |
| Finished | Oct 15 06:45:27 AM UTC 24 |
| Peak memory | 260964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350238418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3350238418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_alert_accum.2989470166 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 403272234 ps |
| CPU time | 34.38 seconds |
| Started | Oct 15 06:43:17 AM UTC 24 |
| Finished | Oct 15 06:43:53 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989470166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2989470166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_intr_timeout.1868346751 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 3124353253 ps |
| CPU time | 38.76 seconds |
| Started | Oct 15 06:43:14 AM UTC 24 |
| Finished | Oct 15 06:43:54 AM UTC 24 |
| Peak memory | 260892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868346751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1868346751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg.35236950 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 211451203506 ps |
| CPU time | 1358.51 seconds |
| Started | Oct 15 06:43:55 AM UTC 24 |
| Finished | Oct 15 07:06:49 AM UTC 24 |
| Peak memory | 283424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35236950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.35236950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg_stub_clk.3884503181 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 243511827302 ps |
| CPU time | 1434.43 seconds |
| Started | Oct 15 06:44:32 AM UTC 24 |
| Finished | Oct 15 07:08:41 AM UTC 24 |
| Peak memory | 283628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884503181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3884503181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_alerts.2393085296 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 359270472 ps |
| CPU time | 32.21 seconds |
| Started | Oct 15 06:42:42 AM UTC 24 |
| Finished | Oct 15 06:43:16 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393085296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2393085296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_classes.772128387 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 854742174 ps |
| CPU time | 18.82 seconds |
| Started | Oct 15 06:43:09 AM UTC 24 |
| Finished | Oct 15 06:43:29 AM UTC 24 |
| Peak memory | 267164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772128387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.772128387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/16.alert_handler_sig_int_fail.3959027354 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1533492157 ps |
| CPU time | 72.82 seconds |
| Started | Oct 15 06:43:28 AM UTC 24 |
| Finished | Oct 15 06:44:43 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959027354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3959027354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/16.alert_handler_smoke.952896785 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 163529468 ps |
| CPU time | 19.89 seconds |
| Started | Oct 15 06:42:20 AM UTC 24 |
| Finished | Oct 15 06:42:41 AM UTC 24 |
| Peak memory | 267168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952896785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.952896785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all.4128041281 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 33760456756 ps |
| CPU time | 1663.35 seconds |
| Started | Oct 15 06:44:59 AM UTC 24 |
| Finished | Oct 15 07:13:02 AM UTC 24 |
| Peak memory | 299756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128041281 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all.4128041281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all_with_rand_reset.10490883 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 949515248 ps |
| CPU time | 32.96 seconds |
| Started | Oct 15 06:45:26 AM UTC 24 |
| Finished | Oct 15 06:46:01 AM UTC 24 |
| Peak memory | 277272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=10490883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.ale rt_handler_stress_all_with_rand_reset.10490883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/17.alert_handler_alert_accum_saturation.365845134 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 13476415 ps |
| CPU time | 3.75 seconds |
| Started | Oct 15 06:47:13 AM UTC 24 |
| Finished | Oct 15 06:47:17 AM UTC 24 |
| Peak memory | 260964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365845134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.365845134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy.2350856865 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 33837938576 ps |
| CPU time | 2459.64 seconds |
| Started | Oct 15 06:46:17 AM UTC 24 |
| Finished | Oct 15 07:27:44 AM UTC 24 |
| Peak memory | 296088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350856865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2350856865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy_stress.224814369 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 752703035 ps |
| CPU time | 21.03 seconds |
| Started | Oct 15 06:46:49 AM UTC 24 |
| Finished | Oct 15 06:47:12 AM UTC 24 |
| Peak memory | 260776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224814369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.224814369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_alert_accum.3475643907 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 128874965 ps |
| CPU time | 16.65 seconds |
| Started | Oct 15 06:46:02 AM UTC 24 |
| Finished | Oct 15 06:46:20 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475643907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3475643907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_intr_timeout.3735383960 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 204398395 ps |
| CPU time | 13.84 seconds |
| Started | Oct 15 06:45:55 AM UTC 24 |
| Finished | Oct 15 06:46:10 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735383960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3735383960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg_stub_clk.3960024012 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 184556912026 ps |
| CPU time | 2360.61 seconds |
| Started | Oct 15 06:46:29 AM UTC 24 |
| Finished | Oct 15 07:26:14 AM UTC 24 |
| Peak memory | 300276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960024012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3960024012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/17.alert_handler_ping_timeout.3167082247 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 8656139679 ps |
| CPU time | 345.16 seconds |
| Started | Oct 15 06:46:20 AM UTC 24 |
| Finished | Oct 15 06:52:10 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167082247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3167082247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_alerts.2360717043 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 598618884 ps |
| CPU time | 15.26 seconds |
| Started | Oct 15 06:45:38 AM UTC 24 |
| Finished | Oct 15 06:45:54 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360717043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2360717043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_classes.572478865 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1985746877 ps |
| CPU time | 72.91 seconds |
| Started | Oct 15 06:45:51 AM UTC 24 |
| Finished | Oct 15 06:47:05 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572478865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.572478865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/17.alert_handler_sig_int_fail.4293532340 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 674243336 ps |
| CPU time | 15.6 seconds |
| Started | Oct 15 06:46:11 AM UTC 24 |
| Finished | Oct 15 06:46:28 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293532340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.4293532340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/17.alert_handler_smoke.3321382608 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 210193032 ps |
| CPU time | 21.35 seconds |
| Started | Oct 15 06:45:27 AM UTC 24 |
| Finished | Oct 15 06:45:50 AM UTC 24 |
| Peak memory | 266984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321382608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3321382608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all.3586529508 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 13837901411 ps |
| CPU time | 1219.72 seconds |
| Started | Oct 15 06:47:06 AM UTC 24 |
| Finished | Oct 15 07:07:40 AM UTC 24 |
| Peak memory | 293672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586529508 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all.3586529508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all_with_rand_reset.2015758077 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 10232113575 ps |
| CPU time | 257.56 seconds |
| Started | Oct 15 06:47:19 AM UTC 24 |
| Finished | Oct 15 06:51:41 AM UTC 24 |
| Peak memory | 277412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2015758077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.a lert_handler_stress_all_with_rand_reset.2015758077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/17.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/18.alert_handler_alert_accum_saturation.2646759983 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 41044203 ps |
| CPU time | 5.58 seconds |
| Started | Oct 15 06:51:22 AM UTC 24 |
| Finished | Oct 15 06:51:29 AM UTC 24 |
| Peak memory | 260968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646759983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2646759983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy.1746232284 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 11006555221 ps |
| CPU time | 1325.1 seconds |
| Started | Oct 15 06:49:22 AM UTC 24 |
| Finished | Oct 15 07:11:44 AM UTC 24 |
| Peak memory | 299812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746232284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1746232284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy_stress.1714568824 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 9648687604 ps |
| CPU time | 41.99 seconds |
| Started | Oct 15 06:51:18 AM UTC 24 |
| Finished | Oct 15 06:52:02 AM UTC 24 |
| Peak memory | 261092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714568824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1714568824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_alert_accum.3594350415 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2415384664 ps |
| CPU time | 142.69 seconds |
| Started | Oct 15 06:48:56 AM UTC 24 |
| Finished | Oct 15 06:51:21 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594350415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3594350415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_intr_timeout.3969321864 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 285414102 ps |
| CPU time | 6.28 seconds |
| Started | Oct 15 06:48:48 AM UTC 24 |
| Finished | Oct 15 06:48:55 AM UTC 24 |
| Peak memory | 263068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969321864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3969321864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg.3505940211 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 62776344828 ps |
| CPU time | 1580.62 seconds |
| Started | Oct 15 06:49:56 AM UTC 24 |
| Finished | Oct 15 07:16:34 AM UTC 24 |
| Peak memory | 300144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505940211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3505940211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg_stub_clk.1932441435 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 41258573812 ps |
| CPU time | 1075.96 seconds |
| Started | Oct 15 06:50:03 AM UTC 24 |
| Finished | Oct 15 07:08:12 AM UTC 24 |
| Peak memory | 281312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932441435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1932441435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/18.alert_handler_ping_timeout.81930571 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 1761435086 ps |
| CPU time | 104.61 seconds |
| Started | Oct 15 06:49:38 AM UTC 24 |
| Finished | Oct 15 06:51:25 AM UTC 24 |
| Peak memory | 260844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81930571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.81930571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_alerts.626249588 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 342064798 ps |
| CPU time | 42.02 seconds |
| Started | Oct 15 06:48:34 AM UTC 24 |
| Finished | Oct 15 06:49:18 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626249588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.626249588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_classes.2373514664 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 5005268087 ps |
| CPU time | 50.85 seconds |
| Started | Oct 15 06:48:44 AM UTC 24 |
| Finished | Oct 15 06:49:37 AM UTC 24 |
| Peak memory | 260956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373514664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2373514664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/18.alert_handler_sig_int_fail.2384188668 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 441225378 ps |
| CPU time | 41.41 seconds |
| Started | Oct 15 06:49:19 AM UTC 24 |
| Finished | Oct 15 06:50:02 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384188668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2384188668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/18.alert_handler_smoke.1777740555 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 315437778 ps |
| CPU time | 38.37 seconds |
| Started | Oct 15 06:48:04 AM UTC 24 |
| Finished | Oct 15 06:48:44 AM UTC 24 |
| Peak memory | 267176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777740555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1777740555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all.2176452114 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 3067721688 ps |
| CPU time | 72.54 seconds |
| Started | Oct 15 06:51:18 AM UTC 24 |
| Finished | Oct 15 06:52:33 AM UTC 24 |
| Peak memory | 267044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176452114 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all.2176452114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/18.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/19.alert_handler_alert_accum_saturation.2472410339 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 45246817 ps |
| CPU time | 3.78 seconds |
| Started | Oct 15 06:52:41 AM UTC 24 |
| Finished | Oct 15 06:52:45 AM UTC 24 |
| Peak memory | 261296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472410339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2472410339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy.1165421700 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 292735852929 ps |
| CPU time | 1566.36 seconds |
| Started | Oct 15 06:52:10 AM UTC 24 |
| Finished | Oct 15 07:18:35 AM UTC 24 |
| Peak memory | 299816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165421700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1165421700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy_stress.1153815292 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 677557698 ps |
| CPU time | 13.57 seconds |
| Started | Oct 15 06:52:34 AM UTC 24 |
| Finished | Oct 15 06:52:49 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153815292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1153815292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_alert_accum.3511014067 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 8610642885 ps |
| CPU time | 333.07 seconds |
| Started | Oct 15 06:52:02 AM UTC 24 |
| Finished | Oct 15 06:57:40 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511014067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3511014067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_intr_timeout.2927485721 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 839321376 ps |
| CPU time | 76.61 seconds |
| Started | Oct 15 06:51:51 AM UTC 24 |
| Finished | Oct 15 06:53:10 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927485721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2927485721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg_stub_clk.1058296727 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 18108844765 ps |
| CPU time | 1847.81 seconds |
| Started | Oct 15 06:52:32 AM UTC 24 |
| Finished | Oct 15 07:23:42 AM UTC 24 |
| Peak memory | 302248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058296727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1058296727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/19.alert_handler_ping_timeout.3103145751 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 36871287957 ps |
| CPU time | 623.47 seconds |
| Started | Oct 15 06:52:13 AM UTC 24 |
| Finished | Oct 15 07:02:45 AM UTC 24 |
| Peak memory | 261164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103145751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3103145751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_alerts.1352772939 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 702786329 ps |
| CPU time | 30.69 seconds |
| Started | Oct 15 06:51:42 AM UTC 24 |
| Finished | Oct 15 06:52:14 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352772939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1352772939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_classes.2134422400 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1589710027 ps |
| CPU time | 54.75 seconds |
| Started | Oct 15 06:51:43 AM UTC 24 |
| Finished | Oct 15 06:52:39 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134422400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2134422400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/19.alert_handler_sig_int_fail.2538553472 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 329897290 ps |
| CPU time | 9.68 seconds |
| Started | Oct 15 06:52:02 AM UTC 24 |
| Finished | Oct 15 06:52:13 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538553472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2538553472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/19.alert_handler_smoke.3203332578 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 112548929 ps |
| CPU time | 19.26 seconds |
| Started | Oct 15 06:51:30 AM UTC 24 |
| Finished | Oct 15 06:51:50 AM UTC 24 |
| Peak memory | 266912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203332578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3203332578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all.3200262065 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 21408936876 ps |
| CPU time | 1458.78 seconds |
| Started | Oct 15 06:52:37 AM UTC 24 |
| Finished | Oct 15 07:17:12 AM UTC 24 |
| Peak memory | 283504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200262065 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all.3200262065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/19.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/2.alert_handler_alert_accum_saturation.738905127 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 42701059 ps |
| CPU time | 5.19 seconds |
| Started | Oct 15 06:21:54 AM UTC 24 |
| Finished | Oct 15 06:22:00 AM UTC 24 |
| Peak memory | 260968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738905127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.738905127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy.2800777201 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 34296784536 ps |
| CPU time | 2360.05 seconds |
| Started | Oct 15 06:21:47 AM UTC 24 |
| Finished | Oct 15 07:01:34 AM UTC 24 |
| Peak memory | 283624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800777201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2800777201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy_stress.2965687505 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 490309324 ps |
| CPU time | 31.87 seconds |
| Started | Oct 15 06:21:50 AM UTC 24 |
| Finished | Oct 15 06:22:24 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965687505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2965687505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_alert_accum.1313346863 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1048745962 ps |
| CPU time | 58.98 seconds |
| Started | Oct 15 06:21:42 AM UTC 24 |
| Finished | Oct 15 06:22:43 AM UTC 24 |
| Peak memory | 266896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313346863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1313346863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg.4034288406 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 19485659269 ps |
| CPU time | 1449.33 seconds |
| Started | Oct 15 06:21:49 AM UTC 24 |
| Finished | Oct 15 06:46:16 AM UTC 24 |
| Peak memory | 283356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034288406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.4034288406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg_stub_clk.444030839 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 75385330278 ps |
| CPU time | 1263.95 seconds |
| Started | Oct 15 06:21:49 AM UTC 24 |
| Finished | Oct 15 06:43:07 AM UTC 24 |
| Peak memory | 283428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444030839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.444030839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/2.alert_handler_sig_int_fail.3669259004 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2884733439 ps |
| CPU time | 75.68 seconds |
| Started | Oct 15 06:21:46 AM UTC 24 |
| Finished | Oct 15 06:23:04 AM UTC 24 |
| Peak memory | 260928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669259004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3669259004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/2.alert_handler_smoke.164518384 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9334491430 ps |
| CPU time | 79.24 seconds |
| Started | Oct 15 06:21:39 AM UTC 24 |
| Finished | Oct 15 06:23:00 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164518384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.164518384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all_with_rand_reset.2188909576 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3144482008 ps |
| CPU time | 333.9 seconds |
| Started | Oct 15 06:21:54 AM UTC 24 |
| Finished | Oct 15 06:27:32 AM UTC 24 |
| Peak memory | 279520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2188909576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.al ert_handler_stress_all_with_rand_reset.2188909576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/20.alert_handler_entropy.717499525 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 151470798486 ps |
| CPU time | 1296.85 seconds |
| Started | Oct 15 06:53:22 AM UTC 24 |
| Finished | Oct 15 07:15:14 AM UTC 24 |
| Peak memory | 283432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717499525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.717499525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/20.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_alert_accum.159986415 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 287661248 ps |
| CPU time | 9.62 seconds |
| Started | Oct 15 06:53:10 AM UTC 24 |
| Finished | Oct 15 06:53:21 AM UTC 24 |
| Peak memory | 262804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159986415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.159986415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_intr_timeout.3035832586 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 4038820604 ps |
| CPU time | 94.64 seconds |
| Started | Oct 15 06:53:06 AM UTC 24 |
| Finished | Oct 15 06:54:42 AM UTC 24 |
| Peak memory | 260816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035832586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3035832586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg.3391363884 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 38130336015 ps |
| CPU time | 787.44 seconds |
| Started | Oct 15 06:53:31 AM UTC 24 |
| Finished | Oct 15 07:06:47 AM UTC 24 |
| Peak memory | 283436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391363884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3391363884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/20.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg_stub_clk.2551758375 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 7434851466 ps |
| CPU time | 908.7 seconds |
| Started | Oct 15 06:53:36 AM UTC 24 |
| Finished | Oct 15 07:08:56 AM UTC 24 |
| Peak memory | 283436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551758375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2551758375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_alerts.3391785622 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 786726851 ps |
| CPU time | 31.62 seconds |
| Started | Oct 15 06:52:50 AM UTC 24 |
| Finished | Oct 15 06:53:23 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391785622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3391785622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/20.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_classes.3446757042 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 4813755214 ps |
| CPU time | 43.81 seconds |
| Started | Oct 15 06:52:56 AM UTC 24 |
| Finished | Oct 15 06:53:41 AM UTC 24 |
| Peak memory | 260892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446757042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3446757042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/20.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/20.alert_handler_sig_int_fail.981953240 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 76003712 ps |
| CPU time | 6.24 seconds |
| Started | Oct 15 06:53:22 AM UTC 24 |
| Finished | Oct 15 06:53:30 AM UTC 24 |
| Peak memory | 260864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981953240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.981953240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/20.alert_handler_smoke.1598304832 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1130140210 ps |
| CPU time | 47.06 seconds |
| Started | Oct 15 06:52:47 AM UTC 24 |
| Finished | Oct 15 06:53:35 AM UTC 24 |
| Peak memory | 266984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598304832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1598304832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/20.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all.561829422 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 80036275970 ps |
| CPU time | 1202.3 seconds |
| Started | Oct 15 06:53:42 AM UTC 24 |
| Finished | Oct 15 07:13:58 AM UTC 24 |
| Peak memory | 299756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561829422 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all.561829422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/20.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all_with_rand_reset.4133975312 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 14711786520 ps |
| CPU time | 385.36 seconds |
| Started | Oct 15 06:54:43 AM UTC 24 |
| Finished | Oct 15 07:01:14 AM UTC 24 |
| Peak memory | 283748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4133975312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.a lert_handler_stress_all_with_rand_reset.4133975312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/21.alert_handler_entropy.1050165248 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 33868527894 ps |
| CPU time | 2136.65 seconds |
| Started | Oct 15 06:56:04 AM UTC 24 |
| Finished | Oct 15 07:32:05 AM UTC 24 |
| Peak memory | 298148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050165248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1050165248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/21.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_alert_accum.1566427054 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 5634704832 ps |
| CPU time | 126.47 seconds |
| Started | Oct 15 06:55:43 AM UTC 24 |
| Finished | Oct 15 06:57:52 AM UTC 24 |
| Peak memory | 267100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566427054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1566427054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_intr_timeout.424021811 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 295426782 ps |
| CPU time | 17.72 seconds |
| Started | Oct 15 06:55:31 AM UTC 24 |
| Finished | Oct 15 06:55:51 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424021811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.424021811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg_stub_clk.3178806241 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 5967429504 ps |
| CPU time | 637.82 seconds |
| Started | Oct 15 06:56:19 AM UTC 24 |
| Finished | Oct 15 07:07:04 AM UTC 24 |
| Peak memory | 283376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178806241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3178806241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/21.alert_handler_ping_timeout.434301623 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 22774792340 ps |
| CPU time | 276.9 seconds |
| Started | Oct 15 06:56:08 AM UTC 24 |
| Finished | Oct 15 07:00:49 AM UTC 24 |
| Peak memory | 260904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434301623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.434301623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_alerts.239159426 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 382835346 ps |
| CPU time | 24.64 seconds |
| Started | Oct 15 06:55:16 AM UTC 24 |
| Finished | Oct 15 06:55:43 AM UTC 24 |
| Peak memory | 266940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239159426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.239159426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/21.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_classes.3008836155 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 1179174884 ps |
| CPU time | 47.77 seconds |
| Started | Oct 15 06:55:27 AM UTC 24 |
| Finished | Oct 15 06:56:17 AM UTC 24 |
| Peak memory | 267164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008836155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3008836155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/21.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/21.alert_handler_smoke.1290500219 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 1159154907 ps |
| CPU time | 52.61 seconds |
| Started | Oct 15 06:55:13 AM UTC 24 |
| Finished | Oct 15 06:56:07 AM UTC 24 |
| Peak memory | 267176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290500219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1290500219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/21.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all.861820353 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 24018895790 ps |
| CPU time | 1718.56 seconds |
| Started | Oct 15 06:57:04 AM UTC 24 |
| Finished | Oct 15 07:26:02 AM UTC 24 |
| Peak memory | 285932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861820353 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all.861820353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/21.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all_with_rand_reset.2064997887 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 2758866039 ps |
| CPU time | 130.75 seconds |
| Started | Oct 15 06:57:41 AM UTC 24 |
| Finished | Oct 15 06:59:54 AM UTC 24 |
| Peak memory | 277340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2064997887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.a lert_handler_stress_all_with_rand_reset.2064997887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/22.alert_handler_entropy.3985593062 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 22999130032 ps |
| CPU time | 1516.06 seconds |
| Started | Oct 15 06:59:11 AM UTC 24 |
| Finished | Oct 15 07:24:45 AM UTC 24 |
| Peak memory | 283428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985593062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3985593062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/22.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_alert_accum.3345867085 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 13651375719 ps |
| CPU time | 183.42 seconds |
| Started | Oct 15 06:59:03 AM UTC 24 |
| Finished | Oct 15 07:02:10 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345867085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3345867085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_intr_timeout.263350257 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1931532014 ps |
| CPU time | 32.25 seconds |
| Started | Oct 15 06:58:54 AM UTC 24 |
| Finished | Oct 15 06:59:28 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263350257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.263350257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg.75864451 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 121939776763 ps |
| CPU time | 1590.53 seconds |
| Started | Oct 15 06:59:28 AM UTC 24 |
| Finished | Oct 15 07:26:16 AM UTC 24 |
| Peak memory | 299756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75864451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.75864451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/22.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg_stub_clk.2729887222 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 98650997185 ps |
| CPU time | 1233.11 seconds |
| Started | Oct 15 06:59:28 AM UTC 24 |
| Finished | Oct 15 07:20:15 AM UTC 24 |
| Peak memory | 277368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729887222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2729887222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/22.alert_handler_ping_timeout.689185890 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 8996872899 ps |
| CPU time | 317.95 seconds |
| Started | Oct 15 06:59:27 AM UTC 24 |
| Finished | Oct 15 07:04:49 AM UTC 24 |
| Peak memory | 260904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689185890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.689185890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_alerts.3760131228 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 152509798 ps |
| CPU time | 15.67 seconds |
| Started | Oct 15 06:57:58 AM UTC 24 |
| Finished | Oct 15 06:58:15 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760131228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3760131228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/22.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_classes.1052069906 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1079709146 ps |
| CPU time | 68.13 seconds |
| Started | Oct 15 06:58:16 AM UTC 24 |
| Finished | Oct 15 06:59:27 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052069906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1052069906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/22.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/22.alert_handler_sig_int_fail.2002987601 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 107892792 ps |
| CPU time | 16.9 seconds |
| Started | Oct 15 06:59:07 AM UTC 24 |
| Finished | Oct 15 06:59:25 AM UTC 24 |
| Peak memory | 261028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002987601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2002987601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/22.alert_handler_smoke.3586803208 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1143602451 ps |
| CPU time | 71.52 seconds |
| Started | Oct 15 06:57:53 AM UTC 24 |
| Finished | Oct 15 06:59:07 AM UTC 24 |
| Peak memory | 266912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586803208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3586803208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/22.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all.1264589495 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 18127562581 ps |
| CPU time | 1517.11 seconds |
| Started | Oct 15 06:59:34 AM UTC 24 |
| Finished | Oct 15 07:25:08 AM UTC 24 |
| Peak memory | 299740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264589495 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all.1264589495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/22.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/23.alert_handler_entropy.3212478489 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 150980326394 ps |
| CPU time | 2371.95 seconds |
| Started | Oct 15 07:01:20 AM UTC 24 |
| Finished | Oct 15 07:41:20 AM UTC 24 |
| Peak memory | 302244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212478489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3212478489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/23.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_alert_accum.1853071901 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 30931652240 ps |
| CPU time | 303.81 seconds |
| Started | Oct 15 07:01:14 AM UTC 24 |
| Finished | Oct 15 07:06:22 AM UTC 24 |
| Peak memory | 267228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853071901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1853071901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_intr_timeout.498922640 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 255502337 ps |
| CPU time | 23.34 seconds |
| Started | Oct 15 07:01:06 AM UTC 24 |
| Finished | Oct 15 07:01:31 AM UTC 24 |
| Peak memory | 261056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498922640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.498922640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg.2423973039 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 259191892634 ps |
| CPU time | 1103.84 seconds |
| Started | Oct 15 07:01:25 AM UTC 24 |
| Finished | Oct 15 07:20:01 AM UTC 24 |
| Peak memory | 283640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423973039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2423973039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/23.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg_stub_clk.2943109117 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 13832728140 ps |
| CPU time | 1504.11 seconds |
| Started | Oct 15 07:01:31 AM UTC 24 |
| Finished | Oct 15 07:26:52 AM UTC 24 |
| Peak memory | 299896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943109117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2943109117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/23.alert_handler_ping_timeout.3433031989 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 78540292196 ps |
| CPU time | 565.6 seconds |
| Started | Oct 15 07:01:20 AM UTC 24 |
| Finished | Oct 15 07:10:53 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433031989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3433031989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_alerts.4189028172 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 488033726 ps |
| CPU time | 22.38 seconds |
| Started | Oct 15 07:00:50 AM UTC 24 |
| Finished | Oct 15 07:01:13 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189028172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.4189028172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/23.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_classes.2841750160 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1414684461 ps |
| CPU time | 13.58 seconds |
| Started | Oct 15 07:00:50 AM UTC 24 |
| Finished | Oct 15 07:01:04 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841750160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2841750160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/23.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/23.alert_handler_sig_int_fail.830264439 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 730279290 ps |
| CPU time | 34 seconds |
| Started | Oct 15 07:01:15 AM UTC 24 |
| Finished | Oct 15 07:01:51 AM UTC 24 |
| Peak memory | 267008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830264439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.830264439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/23.alert_handler_smoke.3651759305 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 1034312565 ps |
| CPU time | 51.67 seconds |
| Started | Oct 15 06:59:55 AM UTC 24 |
| Finished | Oct 15 07:00:49 AM UTC 24 |
| Peak memory | 267176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651759305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3651759305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/23.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all.1597822832 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 389717028132 ps |
| CPU time | 2621.07 seconds |
| Started | Oct 15 07:01:32 AM UTC 24 |
| Finished | Oct 15 07:45:42 AM UTC 24 |
| Peak memory | 302304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597822832 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all.1597822832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/23.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/24.alert_handler_entropy.3072706340 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 38734230860 ps |
| CPU time | 2591.94 seconds |
| Started | Oct 15 07:02:58 AM UTC 24 |
| Finished | Oct 15 07:46:40 AM UTC 24 |
| Peak memory | 302320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072706340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3072706340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/24.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_alert_accum.3438724141 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 7005483809 ps |
| CPU time | 186.57 seconds |
| Started | Oct 15 07:02:54 AM UTC 24 |
| Finished | Oct 15 07:06:04 AM UTC 24 |
| Peak memory | 262868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438724141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3438724141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_intr_timeout.3302711444 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 1440351132 ps |
| CPU time | 41.97 seconds |
| Started | Oct 15 07:02:46 AM UTC 24 |
| Finished | Oct 15 07:03:29 AM UTC 24 |
| Peak memory | 261084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302711444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3302711444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg.1680594540 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 11333500843 ps |
| CPU time | 1282.64 seconds |
| Started | Oct 15 07:03:26 AM UTC 24 |
| Finished | Oct 15 07:25:05 AM UTC 24 |
| Peak memory | 293744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680594540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1680594540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/24.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg_stub_clk.3234815472 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 239167376223 ps |
| CPU time | 2707.94 seconds |
| Started | Oct 15 07:03:31 AM UTC 24 |
| Finished | Oct 15 07:49:07 AM UTC 24 |
| Peak memory | 302232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234815472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3234815472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/24.alert_handler_ping_timeout.1625487265 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 2967110498 ps |
| CPU time | 143.32 seconds |
| Started | Oct 15 07:03:19 AM UTC 24 |
| Finished | Oct 15 07:05:45 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625487265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1625487265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_alerts.2954945445 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 639779483 ps |
| CPU time | 19.93 seconds |
| Started | Oct 15 07:02:10 AM UTC 24 |
| Finished | Oct 15 07:02:31 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954945445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2954945445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/24.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_classes.2631710890 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1262646316 ps |
| CPU time | 44.14 seconds |
| Started | Oct 15 07:02:32 AM UTC 24 |
| Finished | Oct 15 07:03:18 AM UTC 24 |
| Peak memory | 267228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631710890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2631710890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/24.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/24.alert_handler_sig_int_fail.3381781881 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 656965094 ps |
| CPU time | 27.5 seconds |
| Started | Oct 15 07:02:57 AM UTC 24 |
| Finished | Oct 15 07:03:26 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381781881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3381781881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/24.alert_handler_smoke.31724522 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 651747449 ps |
| CPU time | 63.63 seconds |
| Started | Oct 15 07:01:52 AM UTC 24 |
| Finished | Oct 15 07:02:57 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31724522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smo ke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/def ault.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.31724522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/24.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all_with_rand_reset.3673433711 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 15329025630 ps |
| CPU time | 299.77 seconds |
| Started | Oct 15 07:03:47 AM UTC 24 |
| Finished | Oct 15 07:08:51 AM UTC 24 |
| Peak memory | 279460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3673433711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.a lert_handler_stress_all_with_rand_reset.3673433711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/25.alert_handler_entropy.3715430079 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 10155961847 ps |
| CPU time | 700.7 seconds |
| Started | Oct 15 07:05:18 AM UTC 24 |
| Finished | Oct 15 07:17:07 AM UTC 24 |
| Peak memory | 283352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715430079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3715430079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/25.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_alert_accum.1625276028 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 3620002009 ps |
| CPU time | 258.21 seconds |
| Started | Oct 15 07:04:50 AM UTC 24 |
| Finished | Oct 15 07:09:12 AM UTC 24 |
| Peak memory | 262940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625276028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1625276028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/25.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_intr_timeout.1295181293 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2993302440 ps |
| CPU time | 62 seconds |
| Started | Oct 15 07:04:26 AM UTC 24 |
| Finished | Oct 15 07:05:29 AM UTC 24 |
| Peak memory | 260816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295181293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1295181293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg.1295588347 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 72690370106 ps |
| CPU time | 2979.13 seconds |
| Started | Oct 15 07:05:37 AM UTC 24 |
| Finished | Oct 15 07:55:50 AM UTC 24 |
| Peak memory | 302304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295588347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1295588347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/25.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg_stub_clk.504468536 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 44170985786 ps |
| CPU time | 844.85 seconds |
| Started | Oct 15 07:05:40 AM UTC 24 |
| Finished | Oct 15 07:19:55 AM UTC 24 |
| Peak memory | 283432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504468536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.504468536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/25.alert_handler_ping_timeout.2304524946 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 12469878645 ps |
| CPU time | 413.12 seconds |
| Started | Oct 15 07:05:30 AM UTC 24 |
| Finished | Oct 15 07:12:29 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304524946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2304524946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_alerts.2346629761 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 844147416 ps |
| CPU time | 66.1 seconds |
| Started | Oct 15 07:04:09 AM UTC 24 |
| Finished | Oct 15 07:05:17 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346629761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2346629761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/25.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_classes.3018517957 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1560217948 ps |
| CPU time | 73.93 seconds |
| Started | Oct 15 07:04:23 AM UTC 24 |
| Finished | Oct 15 07:05:39 AM UTC 24 |
| Peak memory | 267164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018517957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3018517957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/25.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/25.alert_handler_sig_int_fail.494000480 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 690365037 ps |
| CPU time | 35.56 seconds |
| Started | Oct 15 07:05:00 AM UTC 24 |
| Finished | Oct 15 07:05:37 AM UTC 24 |
| Peak memory | 261056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494000480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.494000480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/25.alert_handler_smoke.3182608288 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 312760057 ps |
| CPU time | 30.18 seconds |
| Started | Oct 15 07:03:53 AM UTC 24 |
| Finished | Oct 15 07:04:25 AM UTC 24 |
| Peak memory | 266984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182608288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3182608288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/25.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all.698461307 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 78256864969 ps |
| CPU time | 1981.79 seconds |
| Started | Oct 15 07:05:46 AM UTC 24 |
| Finished | Oct 15 07:39:09 AM UTC 24 |
| Peak memory | 316624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698461307 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all.698461307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/25.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/26.alert_handler_entropy.540387302 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 122974659337 ps |
| CPU time | 1056 seconds |
| Started | Oct 15 07:06:48 AM UTC 24 |
| Finished | Oct 15 07:24:36 AM UTC 24 |
| Peak memory | 300076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540387302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.540387302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/26.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_alert_accum.2963779830 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2391825161 ps |
| CPU time | 186.84 seconds |
| Started | Oct 15 07:06:46 AM UTC 24 |
| Finished | Oct 15 07:09:56 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963779830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2963779830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/26.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_intr_timeout.264758017 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2849238033 ps |
| CPU time | 66.64 seconds |
| Started | Oct 15 07:06:42 AM UTC 24 |
| Finished | Oct 15 07:07:51 AM UTC 24 |
| Peak memory | 267000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264758017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.264758017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg.863690413 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 68300608240 ps |
| CPU time | 1896.72 seconds |
| Started | Oct 15 07:06:52 AM UTC 24 |
| Finished | Oct 15 07:38:51 AM UTC 24 |
| Peak memory | 302568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863690413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.863690413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/26.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg_stub_clk.3180397452 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 205006592347 ps |
| CPU time | 2726.69 seconds |
| Started | Oct 15 07:07:07 AM UTC 24 |
| Finished | Oct 15 07:53:05 AM UTC 24 |
| Peak memory | 302312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180397452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3180397452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_alerts.3905841491 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 241843758 ps |
| CPU time | 19.15 seconds |
| Started | Oct 15 07:06:24 AM UTC 24 |
| Finished | Oct 15 07:06:44 AM UTC 24 |
| Peak memory | 267152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905841491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3905841491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/26.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_classes.2297443280 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 365114565 ps |
| CPU time | 16 seconds |
| Started | Oct 15 07:06:24 AM UTC 24 |
| Finished | Oct 15 07:06:41 AM UTC 24 |
| Peak memory | 266928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297443280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2297443280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/26.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/26.alert_handler_sig_int_fail.3218532104 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 640172275 ps |
| CPU time | 24.21 seconds |
| Started | Oct 15 07:06:48 AM UTC 24 |
| Finished | Oct 15 07:07:14 AM UTC 24 |
| Peak memory | 261076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218532104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3218532104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/26.alert_handler_smoke.1303040944 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 320340958 ps |
| CPU time | 25.36 seconds |
| Started | Oct 15 07:06:21 AM UTC 24 |
| Finished | Oct 15 07:06:47 AM UTC 24 |
| Peak memory | 267176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303040944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1303040944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/26.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all.3793785082 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 129812506548 ps |
| CPU time | 880.01 seconds |
| Started | Oct 15 07:07:15 AM UTC 24 |
| Finished | Oct 15 07:22:05 AM UTC 24 |
| Peak memory | 283428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793785082 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all.3793785082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/26.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all_with_rand_reset.2896156402 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 4712966427 ps |
| CPU time | 135.46 seconds |
| Started | Oct 15 07:07:28 AM UTC 24 |
| Finished | Oct 15 07:09:46 AM UTC 24 |
| Peak memory | 281764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2896156402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.a lert_handler_stress_all_with_rand_reset.2896156402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/27.alert_handler_entropy.3666521237 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 121261748473 ps |
| CPU time | 1251.09 seconds |
| Started | Oct 15 07:08:29 AM UTC 24 |
| Finished | Oct 15 07:29:34 AM UTC 24 |
| Peak memory | 283412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666521237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3666521237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/27.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_alert_accum.742964383 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 4779309943 ps |
| CPU time | 206.51 seconds |
| Started | Oct 15 07:08:23 AM UTC 24 |
| Finished | Oct 15 07:11:52 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742964383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.742964383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/27.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_intr_timeout.2773478022 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 4825747246 ps |
| CPU time | 52.42 seconds |
| Started | Oct 15 07:08:14 AM UTC 24 |
| Finished | Oct 15 07:09:08 AM UTC 24 |
| Peak memory | 260816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773478022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2773478022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg.3654788112 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 96132697888 ps |
| CPU time | 1354.8 seconds |
| Started | Oct 15 07:08:44 AM UTC 24 |
| Finished | Oct 15 07:31:34 AM UTC 24 |
| Peak memory | 277228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654788112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3654788112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/27.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg_stub_clk.4245497677 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 24130469388 ps |
| CPU time | 1227.38 seconds |
| Started | Oct 15 07:08:49 AM UTC 24 |
| Finished | Oct 15 07:29:30 AM UTC 24 |
| Peak memory | 277540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245497677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.4245497677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_alerts.1928859136 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1387531294 ps |
| CPU time | 33.24 seconds |
| Started | Oct 15 07:07:50 AM UTC 24 |
| Finished | Oct 15 07:08:25 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928859136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1928859136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/27.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_classes.2200984780 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 1036479298 ps |
| CPU time | 29.43 seconds |
| Started | Oct 15 07:07:51 AM UTC 24 |
| Finished | Oct 15 07:08:22 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200984780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2200984780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/27.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/27.alert_handler_sig_int_fail.3662003992 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2346963966 ps |
| CPU time | 47.78 seconds |
| Started | Oct 15 07:08:26 AM UTC 24 |
| Finished | Oct 15 07:09:15 AM UTC 24 |
| Peak memory | 267232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662003992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3662003992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/27.alert_handler_smoke.3879935756 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1395363991 ps |
| CPU time | 44.09 seconds |
| Started | Oct 15 07:07:42 AM UTC 24 |
| Finished | Oct 15 07:08:28 AM UTC 24 |
| Peak memory | 266912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879935756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3879935756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/27.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all.2776700529 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 156694611408 ps |
| CPU time | 1350.14 seconds |
| Started | Oct 15 07:08:52 AM UTC 24 |
| Finished | Oct 15 07:31:37 AM UTC 24 |
| Peak memory | 277288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776700529 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all.2776700529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/27.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all_with_rand_reset.1672224026 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 5911503706 ps |
| CPU time | 378.71 seconds |
| Started | Oct 15 07:08:58 AM UTC 24 |
| Finished | Oct 15 07:15:22 AM UTC 24 |
| Peak memory | 281432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1672224026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.a lert_handler_stress_all_with_rand_reset.1672224026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/28.alert_handler_entropy.1631438841 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 14947874476 ps |
| CPU time | 1068.07 seconds |
| Started | Oct 15 07:09:57 AM UTC 24 |
| Finished | Oct 15 07:27:57 AM UTC 24 |
| Peak memory | 277212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631438841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1631438841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/28.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_alert_accum.3817897441 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 5755677457 ps |
| CPU time | 308.3 seconds |
| Started | Oct 15 07:09:46 AM UTC 24 |
| Finished | Oct 15 07:14:59 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817897441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3817897441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/28.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_intr_timeout.3843810594 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 332098201 ps |
| CPU time | 33.32 seconds |
| Started | Oct 15 07:09:16 AM UTC 24 |
| Finished | Oct 15 07:09:51 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843810594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3843810594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg.447804773 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 65101126831 ps |
| CPU time | 918.99 seconds |
| Started | Oct 15 07:10:02 AM UTC 24 |
| Finished | Oct 15 07:25:33 AM UTC 24 |
| Peak memory | 283676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447804773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.447804773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/28.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/28.alert_handler_ping_timeout.252375406 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 49943387826 ps |
| CPU time | 490.77 seconds |
| Started | Oct 15 07:09:58 AM UTC 24 |
| Finished | Oct 15 07:18:15 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252375406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.252375406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_alerts.927093696 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2491756071 ps |
| CPU time | 68.95 seconds |
| Started | Oct 15 07:09:09 AM UTC 24 |
| Finished | Oct 15 07:10:20 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927093696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.927093696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/28.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_classes.3422858780 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 722431028 ps |
| CPU time | 54.88 seconds |
| Started | Oct 15 07:09:13 AM UTC 24 |
| Finished | Oct 15 07:10:10 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422858780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3422858780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/28.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/28.alert_handler_sig_int_fail.2869757655 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 630405034 ps |
| CPU time | 23.79 seconds |
| Started | Oct 15 07:09:52 AM UTC 24 |
| Finished | Oct 15 07:10:17 AM UTC 24 |
| Peak memory | 267168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869757655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2869757655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/28.alert_handler_smoke.3265284211 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 599941600 ps |
| CPU time | 55.61 seconds |
| Started | Oct 15 07:09:00 AM UTC 24 |
| Finished | Oct 15 07:09:57 AM UTC 24 |
| Peak memory | 266912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265284211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3265284211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/28.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all.2685394960 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 20386787744 ps |
| CPU time | 1329.75 seconds |
| Started | Oct 15 07:10:19 AM UTC 24 |
| Finished | Oct 15 07:32:46 AM UTC 24 |
| Peak memory | 299740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685394960 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all.2685394960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/28.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all_with_rand_reset.2524230962 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 4118455952 ps |
| CPU time | 200.25 seconds |
| Started | Oct 15 07:10:19 AM UTC 24 |
| Finished | Oct 15 07:13:43 AM UTC 24 |
| Peak memory | 277604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2524230962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.a lert_handler_stress_all_with_rand_reset.2524230962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/28.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/29.alert_handler_entropy.1756302595 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 213859522087 ps |
| CPU time | 3404.2 seconds |
| Started | Oct 15 07:11:47 AM UTC 24 |
| Finished | Oct 15 08:09:07 AM UTC 24 |
| Peak memory | 302244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756302595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1756302595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/29.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_alert_accum.3687448884 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 6715535924 ps |
| CPU time | 140.09 seconds |
| Started | Oct 15 07:11:27 AM UTC 24 |
| Finished | Oct 15 07:13:49 AM UTC 24 |
| Peak memory | 267228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687448884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3687448884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/29.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_intr_timeout.331694698 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 376948043 ps |
| CPU time | 45.46 seconds |
| Started | Oct 15 07:10:54 AM UTC 24 |
| Finished | Oct 15 07:11:41 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331694698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.331694698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg.1190382287 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 142296991811 ps |
| CPU time | 1624.56 seconds |
| Started | Oct 15 07:11:56 AM UTC 24 |
| Finished | Oct 15 07:39:18 AM UTC 24 |
| Peak memory | 299812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190382287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1190382287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/29.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg_stub_clk.1727450358 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 40468234138 ps |
| CPU time | 2359.59 seconds |
| Started | Oct 15 07:11:56 AM UTC 24 |
| Finished | Oct 15 07:51:41 AM UTC 24 |
| Peak memory | 296088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727450358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1727450358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/29.alert_handler_ping_timeout.1158906274 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3403627247 ps |
| CPU time | 151.04 seconds |
| Started | Oct 15 07:11:47 AM UTC 24 |
| Finished | Oct 15 07:14:20 AM UTC 24 |
| Peak memory | 261096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158906274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1158906274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_alerts.2691549982 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 152248850 ps |
| CPU time | 6.02 seconds |
| Started | Oct 15 07:10:34 AM UTC 24 |
| Finished | Oct 15 07:10:41 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691549982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2691549982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/29.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_classes.3449181597 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 948765245 ps |
| CPU time | 61.31 seconds |
| Started | Oct 15 07:10:42 AM UTC 24 |
| Finished | Oct 15 07:11:45 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449181597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3449181597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/29.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/29.alert_handler_sig_int_fail.773593738 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 86703974 ps |
| CPU time | 11.69 seconds |
| Started | Oct 15 07:11:42 AM UTC 24 |
| Finished | Oct 15 07:11:54 AM UTC 24 |
| Peak memory | 264960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773593738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.773593738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/29.alert_handler_smoke.1590955668 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 417469708 ps |
| CPU time | 11.28 seconds |
| Started | Oct 15 07:10:21 AM UTC 24 |
| Finished | Oct 15 07:10:33 AM UTC 24 |
| Peak memory | 260768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590955668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1590955668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/29.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all.4063361345 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 6568397971 ps |
| CPU time | 796.43 seconds |
| Started | Oct 15 07:11:57 AM UTC 24 |
| Finished | Oct 15 07:25:23 AM UTC 24 |
| Peak memory | 281364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063361345 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all.4063361345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/29.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all_with_rand_reset.3821136178 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 7140316909 ps |
| CPU time | 262.14 seconds |
| Started | Oct 15 07:11:58 AM UTC 24 |
| Finished | Oct 15 07:16:24 AM UTC 24 |
| Peak memory | 279652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3821136178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.a lert_handler_stress_all_with_rand_reset.3821136178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/3.alert_handler_alert_accum_saturation.1228238294 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 76829058 ps |
| CPU time | 4.06 seconds |
| Started | Oct 15 06:22:19 AM UTC 24 |
| Finished | Oct 15 06:22:25 AM UTC 24 |
| Peak memory | 260960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228238294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1228238294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy.3740052567 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 29655040180 ps |
| CPU time | 1964.54 seconds |
| Started | Oct 15 06:22:04 AM UTC 24 |
| Finished | Oct 15 06:55:10 AM UTC 24 |
| Peak memory | 299832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740052567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3740052567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy_stress.1357203542 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 214076062 ps |
| CPU time | 17.59 seconds |
| Started | Oct 15 06:22:13 AM UTC 24 |
| Finished | Oct 15 06:22:32 AM UTC 24 |
| Peak memory | 261028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357203542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1357203542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_alert_accum.3067810657 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 1751295728 ps |
| CPU time | 220.47 seconds |
| Started | Oct 15 06:22:01 AM UTC 24 |
| Finished | Oct 15 06:25:45 AM UTC 24 |
| Peak memory | 266896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067810657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3067810657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg_stub_clk.2942780253 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 162040197871 ps |
| CPU time | 2229.47 seconds |
| Started | Oct 15 06:22:12 AM UTC 24 |
| Finished | Oct 15 06:59:45 AM UTC 24 |
| Peak memory | 300004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942780253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2942780253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/3.alert_handler_ping_timeout.29906117 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 5583170723 ps |
| CPU time | 212.04 seconds |
| Started | Oct 15 06:22:05 AM UTC 24 |
| Finished | Oct 15 06:25:40 AM UTC 24 |
| Peak memory | 261092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29906117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.29906117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_alerts.543193767 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 470771535 ps |
| CPU time | 32.66 seconds |
| Started | Oct 15 06:21:59 AM UTC 24 |
| Finished | Oct 15 06:22:33 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543193767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.543193767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_classes.3824196983 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 373035488 ps |
| CPU time | 35.86 seconds |
| Started | Oct 15 06:22:01 AM UTC 24 |
| Finished | Oct 15 06:22:38 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824196983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3824196983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/3.alert_handler_sec_cm.1271830225 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 621004167 ps |
| CPU time | 13.97 seconds |
| Started | Oct 15 06:22:25 AM UTC 24 |
| Finished | Oct 15 06:22:41 AM UTC 24 |
| Peak memory | 293004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271830225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1271830225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/3.alert_handler_sig_int_fail.2811743956 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 179139852 ps |
| CPU time | 16.3 seconds |
| Started | Oct 15 06:22:01 AM UTC 24 |
| Finished | Oct 15 06:22:18 AM UTC 24 |
| Peak memory | 261120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811743956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2811743956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/3.alert_handler_smoke.1576743149 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 204967696 ps |
| CPU time | 12.18 seconds |
| Started | Oct 15 06:21:58 AM UTC 24 |
| Finished | Oct 15 06:22:12 AM UTC 24 |
| Peak memory | 261028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576743149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1576743149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/3.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/30.alert_handler_entropy.139770691 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 60630280276 ps |
| CPU time | 1294.99 seconds |
| Started | Oct 15 07:13:05 AM UTC 24 |
| Finished | Oct 15 07:34:56 AM UTC 24 |
| Peak memory | 297844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139770691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.139770691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/30.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_alert_accum.553841758 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2472952646 ps |
| CPU time | 131.37 seconds |
| Started | Oct 15 07:12:38 AM UTC 24 |
| Finished | Oct 15 07:14:52 AM UTC 24 |
| Peak memory | 266968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553841758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.553841758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/30.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_intr_timeout.2809980564 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 503894323 ps |
| CPU time | 42.61 seconds |
| Started | Oct 15 07:12:29 AM UTC 24 |
| Finished | Oct 15 07:13:14 AM UTC 24 |
| Peak memory | 260752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809980564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2809980564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg.4029531965 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 67367419906 ps |
| CPU time | 1605.12 seconds |
| Started | Oct 15 07:13:14 AM UTC 24 |
| Finished | Oct 15 07:40:18 AM UTC 24 |
| Peak memory | 299876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029531965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.4029531965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/30.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg_stub_clk.1934664393 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 188237338193 ps |
| CPU time | 2735.1 seconds |
| Started | Oct 15 07:13:18 AM UTC 24 |
| Finished | Oct 15 07:59:24 AM UTC 24 |
| Peak memory | 302388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934664393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1934664393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/30.alert_handler_ping_timeout.3934056878 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 13187887710 ps |
| CPU time | 622.23 seconds |
| Started | Oct 15 07:13:07 AM UTC 24 |
| Finished | Oct 15 07:23:37 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934056878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3934056878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_alerts.1890803310 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 3315157947 ps |
| CPU time | 48.28 seconds |
| Started | Oct 15 07:12:16 AM UTC 24 |
| Finished | Oct 15 07:13:07 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890803310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1890803310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/30.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_classes.3512782803 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1250853197 ps |
| CPU time | 17.2 seconds |
| Started | Oct 15 07:12:19 AM UTC 24 |
| Finished | Oct 15 07:12:37 AM UTC 24 |
| Peak memory | 260768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512782803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3512782803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/30.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/30.alert_handler_sig_int_fail.3735392912 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 905467516 ps |
| CPU time | 24.67 seconds |
| Started | Oct 15 07:12:51 AM UTC 24 |
| Finished | Oct 15 07:13:17 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735392912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3735392912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/30.alert_handler_smoke.3200267846 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 101495097 ps |
| CPU time | 9.17 seconds |
| Started | Oct 15 07:12:07 AM UTC 24 |
| Finished | Oct 15 07:12:18 AM UTC 24 |
| Peak memory | 261096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200267846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3200267846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/30.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/31.alert_handler_entropy.423474166 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 50807338202 ps |
| CPU time | 1090.48 seconds |
| Started | Oct 15 07:14:55 AM UTC 24 |
| Finished | Oct 15 07:33:18 AM UTC 24 |
| Peak memory | 293924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423474166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.423474166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/31.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_alert_accum.3736403825 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 447016532 ps |
| CPU time | 47.53 seconds |
| Started | Oct 15 07:14:34 AM UTC 24 |
| Finished | Oct 15 07:15:23 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736403825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3736403825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/31.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_intr_timeout.2120781221 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 291681423 ps |
| CPU time | 44.48 seconds |
| Started | Oct 15 07:14:27 AM UTC 24 |
| Finished | Oct 15 07:15:13 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120781221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2120781221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg.1371480217 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 67274386635 ps |
| CPU time | 1360.51 seconds |
| Started | Oct 15 07:15:00 AM UTC 24 |
| Finished | Oct 15 07:37:56 AM UTC 24 |
| Peak memory | 299872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371480217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1371480217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/31.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg_stub_clk.4082578400 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 80555834587 ps |
| CPU time | 2130.32 seconds |
| Started | Oct 15 07:15:10 AM UTC 24 |
| Finished | Oct 15 07:51:03 AM UTC 24 |
| Peak memory | 302512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082578400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.4082578400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/31.alert_handler_ping_timeout.2399498342 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 12981198186 ps |
| CPU time | 318.55 seconds |
| Started | Oct 15 07:14:57 AM UTC 24 |
| Finished | Oct 15 07:20:19 AM UTC 24 |
| Peak memory | 261036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399498342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2399498342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_alerts.2164740493 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 487689986 ps |
| CPU time | 31.56 seconds |
| Started | Oct 15 07:14:01 AM UTC 24 |
| Finished | Oct 15 07:14:34 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164740493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2164740493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/31.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_classes.2397938472 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 3093439501 ps |
| CPU time | 46.73 seconds |
| Started | Oct 15 07:14:21 AM UTC 24 |
| Finished | Oct 15 07:15:09 AM UTC 24 |
| Peak memory | 260892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397938472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2397938472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/31.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/31.alert_handler_sig_int_fail.4110464071 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 368464936 ps |
| CPU time | 28.75 seconds |
| Started | Oct 15 07:14:54 AM UTC 24 |
| Finished | Oct 15 07:15:24 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110464071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.4110464071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/31.alert_handler_smoke.1503870865 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1324224759 ps |
| CPU time | 60.36 seconds |
| Started | Oct 15 07:13:54 AM UTC 24 |
| Finished | Oct 15 07:14:56 AM UTC 24 |
| Peak memory | 266984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503870865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1503870865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/31.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all.3257498699 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 23838360618 ps |
| CPU time | 1196.54 seconds |
| Started | Oct 15 07:15:14 AM UTC 24 |
| Finished | Oct 15 07:35:25 AM UTC 24 |
| Peak memory | 299812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257498699 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all.3257498699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/31.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all_with_rand_reset.105861692 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 16595268792 ps |
| CPU time | 392.77 seconds |
| Started | Oct 15 07:15:16 AM UTC 24 |
| Finished | Oct 15 07:21:55 AM UTC 24 |
| Peak memory | 277476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=105861692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.al ert_handler_stress_all_with_rand_reset.105861692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/32.alert_handler_entropy.1963062372 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 125712365671 ps |
| CPU time | 2144.53 seconds |
| Started | Oct 15 07:16:30 AM UTC 24 |
| Finished | Oct 15 07:52:38 AM UTC 24 |
| Peak memory | 285936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963062372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1963062372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/32.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_alert_accum.3797865954 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 2690525112 ps |
| CPU time | 115.99 seconds |
| Started | Oct 15 07:15:54 AM UTC 24 |
| Finished | Oct 15 07:17:53 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797865954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3797865954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/32.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_intr_timeout.3333814695 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 4138613196 ps |
| CPU time | 78.09 seconds |
| Started | Oct 15 07:15:25 AM UTC 24 |
| Finished | Oct 15 07:16:45 AM UTC 24 |
| Peak memory | 260816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333814695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3333814695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg.1251940923 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 84034084389 ps |
| CPU time | 2239.71 seconds |
| Started | Oct 15 07:16:42 AM UTC 24 |
| Finished | Oct 15 07:54:25 AM UTC 24 |
| Peak memory | 302308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251940923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1251940923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/32.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg_stub_clk.211700238 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 57168477890 ps |
| CPU time | 3239.79 seconds |
| Started | Oct 15 07:16:47 AM UTC 24 |
| Finished | Oct 15 08:11:22 AM UTC 24 |
| Peak memory | 302304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211700238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.211700238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/32.alert_handler_ping_timeout.1648125287 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 24580540416 ps |
| CPU time | 692.55 seconds |
| Started | Oct 15 07:16:37 AM UTC 24 |
| Finished | Oct 15 07:28:18 AM UTC 24 |
| Peak memory | 260904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648125287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1648125287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_alerts.707492285 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 568743489 ps |
| CPU time | 64.32 seconds |
| Started | Oct 15 07:15:23 AM UTC 24 |
| Finished | Oct 15 07:16:29 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707492285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.707492285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/32.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_classes.3160634732 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 3428935037 ps |
| CPU time | 74.79 seconds |
| Started | Oct 15 07:15:24 AM UTC 24 |
| Finished | Oct 15 07:16:41 AM UTC 24 |
| Peak memory | 266968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160634732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3160634732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/32.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/32.alert_handler_sig_int_fail.1498262748 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 667380979 ps |
| CPU time | 58.24 seconds |
| Started | Oct 15 07:16:26 AM UTC 24 |
| Finished | Oct 15 07:17:26 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498262748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1498262748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/32.alert_handler_smoke.3748977254 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 2593840463 ps |
| CPU time | 31.66 seconds |
| Started | Oct 15 07:15:21 AM UTC 24 |
| Finished | Oct 15 07:15:54 AM UTC 24 |
| Peak memory | 267048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748977254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3748977254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/32.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all.272808601 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 16954416677 ps |
| CPU time | 1774.1 seconds |
| Started | Oct 15 07:16:49 AM UTC 24 |
| Finished | Oct 15 07:46:44 AM UTC 24 |
| Peak memory | 299732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272808601 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all.272808601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/32.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all_with_rand_reset.847001995 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2772900846 ps |
| CPU time | 387.95 seconds |
| Started | Oct 15 07:16:49 AM UTC 24 |
| Finished | Oct 15 07:23:22 AM UTC 24 |
| Peak memory | 279368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=847001995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.al ert_handler_stress_all_with_rand_reset.847001995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/33.alert_handler_entropy.1819668519 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 13162563624 ps |
| CPU time | 1413.82 seconds |
| Started | Oct 15 07:18:16 AM UTC 24 |
| Finished | Oct 15 07:42:05 AM UTC 24 |
| Peak memory | 299812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819668519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1819668519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/33.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_alert_accum.1691315190 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 3250976982 ps |
| CPU time | 107.45 seconds |
| Started | Oct 15 07:17:54 AM UTC 24 |
| Finished | Oct 15 07:19:44 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691315190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1691315190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/33.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_intr_timeout.616832744 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 3801458467 ps |
| CPU time | 34.49 seconds |
| Started | Oct 15 07:17:35 AM UTC 24 |
| Finished | Oct 15 07:18:11 AM UTC 24 |
| Peak memory | 267072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616832744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.616832744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg.4290112974 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 18789906427 ps |
| CPU time | 1132.22 seconds |
| Started | Oct 15 07:18:24 AM UTC 24 |
| Finished | Oct 15 07:37:29 AM UTC 24 |
| Peak memory | 283504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290112974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.4290112974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/33.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg_stub_clk.2085511923 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 48259249628 ps |
| CPU time | 2831.05 seconds |
| Started | Oct 15 07:18:38 AM UTC 24 |
| Finished | Oct 15 08:06:21 AM UTC 24 |
| Peak memory | 302504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085511923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2085511923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/33.alert_handler_ping_timeout.3260258539 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 5621774820 ps |
| CPU time | 146.19 seconds |
| Started | Oct 15 07:18:17 AM UTC 24 |
| Finished | Oct 15 07:20:46 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260258539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3260258539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_alerts.1625219402 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 3122602887 ps |
| CPU time | 60.11 seconds |
| Started | Oct 15 07:17:14 AM UTC 24 |
| Finished | Oct 15 07:18:16 AM UTC 24 |
| Peak memory | 267228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625219402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1625219402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/33.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_classes.2416943578 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 698111530 ps |
| CPU time | 54 seconds |
| Started | Oct 15 07:17:27 AM UTC 24 |
| Finished | Oct 15 07:18:23 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416943578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2416943578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/33.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/33.alert_handler_sig_int_fail.719882539 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 824967221 ps |
| CPU time | 37.71 seconds |
| Started | Oct 15 07:18:11 AM UTC 24 |
| Finished | Oct 15 07:18:51 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719882539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.719882539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/33.alert_handler_smoke.2719709252 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 584640245 ps |
| CPU time | 23.54 seconds |
| Started | Oct 15 07:17:09 AM UTC 24 |
| Finished | Oct 15 07:17:34 AM UTC 24 |
| Peak memory | 266912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719709252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2719709252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/33.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all.120606253 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 53872083468 ps |
| CPU time | 1389.3 seconds |
| Started | Oct 15 07:18:52 AM UTC 24 |
| Finished | Oct 15 07:42:18 AM UTC 24 |
| Peak memory | 299888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120606253 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all.120606253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/33.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/34.alert_handler_entropy.2911400521 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 12165084300 ps |
| CPU time | 1395.67 seconds |
| Started | Oct 15 07:20:27 AM UTC 24 |
| Finished | Oct 15 07:44:00 AM UTC 24 |
| Peak memory | 293728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911400521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2911400521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/34.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_alert_accum.1607958766 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 11680433785 ps |
| CPU time | 188.13 seconds |
| Started | Oct 15 07:20:20 AM UTC 24 |
| Finished | Oct 15 07:23:31 AM UTC 24 |
| Peak memory | 266960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607958766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1607958766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/34.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_intr_timeout.1049350124 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 661755393 ps |
| CPU time | 53.51 seconds |
| Started | Oct 15 07:20:19 AM UTC 24 |
| Finished | Oct 15 07:21:14 AM UTC 24 |
| Peak memory | 260732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049350124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1049350124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg.1303133080 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 18891494882 ps |
| CPU time | 852.39 seconds |
| Started | Oct 15 07:20:39 AM UTC 24 |
| Finished | Oct 15 07:35:02 AM UTC 24 |
| Peak memory | 283508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303133080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1303133080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/34.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg_stub_clk.2315114814 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 164820034806 ps |
| CPU time | 2617.64 seconds |
| Started | Oct 15 07:20:47 AM UTC 24 |
| Finished | Oct 15 08:04:54 AM UTC 24 |
| Peak memory | 302292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315114814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2315114814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/34.alert_handler_ping_timeout.1394595628 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 5364740398 ps |
| CPU time | 334.86 seconds |
| Started | Oct 15 07:20:29 AM UTC 24 |
| Finished | Oct 15 07:26:08 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394595628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1394595628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_alerts.1865027236 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 330507468 ps |
| CPU time | 17.17 seconds |
| Started | Oct 15 07:20:02 AM UTC 24 |
| Finished | Oct 15 07:20:21 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865027236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1865027236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/34.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_classes.2759339483 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 473524455 ps |
| CPU time | 7.44 seconds |
| Started | Oct 15 07:20:19 AM UTC 24 |
| Finished | Oct 15 07:20:28 AM UTC 24 |
| Peak memory | 250508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759339483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2759339483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/34.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/34.alert_handler_sig_int_fail.2805938238 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 82812914 ps |
| CPU time | 3.96 seconds |
| Started | Oct 15 07:20:21 AM UTC 24 |
| Finished | Oct 15 07:20:26 AM UTC 24 |
| Peak memory | 250592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805938238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2805938238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/34.alert_handler_smoke.3374918940 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 1268364537 ps |
| CPU time | 39.46 seconds |
| Started | Oct 15 07:19:57 AM UTC 24 |
| Finished | Oct 15 07:20:38 AM UTC 24 |
| Peak memory | 266912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374918940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3374918940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/34.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/35.alert_handler_entropy.2989322307 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 7017242347 ps |
| CPU time | 689.64 seconds |
| Started | Oct 15 07:23:23 AM UTC 24 |
| Finished | Oct 15 07:35:00 AM UTC 24 |
| Peak memory | 283416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989322307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2989322307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/35.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_alert_accum.396668615 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 300510303 ps |
| CPU time | 22.7 seconds |
| Started | Oct 15 07:23:13 AM UTC 24 |
| Finished | Oct 15 07:23:37 AM UTC 24 |
| Peak memory | 267100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396668615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.396668615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/35.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_intr_timeout.3565474782 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 334210687 ps |
| CPU time | 34.09 seconds |
| Started | Oct 15 07:23:08 AM UTC 24 |
| Finished | Oct 15 07:23:44 AM UTC 24 |
| Peak memory | 261084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565474782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3565474782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg.1651348469 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 101761180871 ps |
| CPU time | 1679.47 seconds |
| Started | Oct 15 07:23:38 AM UTC 24 |
| Finished | Oct 15 07:51:58 AM UTC 24 |
| Peak memory | 283352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651348469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1651348469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/35.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg_stub_clk.1674923524 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 22133606407 ps |
| CPU time | 1491.62 seconds |
| Started | Oct 15 07:23:38 AM UTC 24 |
| Finished | Oct 15 07:48:48 AM UTC 24 |
| Peak memory | 281380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674923524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1674923524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/35.alert_handler_ping_timeout.2118478822 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 12784668820 ps |
| CPU time | 261.75 seconds |
| Started | Oct 15 07:23:32 AM UTC 24 |
| Finished | Oct 15 07:27:57 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118478822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2118478822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_alerts.1871776705 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1101081262 ps |
| CPU time | 51.44 seconds |
| Started | Oct 15 07:22:20 AM UTC 24 |
| Finished | Oct 15 07:23:13 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871776705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1871776705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/35.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_classes.1146329631 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 493675386 ps |
| CPU time | 9.89 seconds |
| Started | Oct 15 07:23:02 AM UTC 24 |
| Finished | Oct 15 07:23:13 AM UTC 24 |
| Peak memory | 260892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146329631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1146329631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/35.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/35.alert_handler_sig_int_fail.21219292 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2000072193 ps |
| CPU time | 29.52 seconds |
| Started | Oct 15 07:23:14 AM UTC 24 |
| Finished | Oct 15 07:23:45 AM UTC 24 |
| Peak memory | 267168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21219292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig _int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.21219292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/35.alert_handler_smoke.551053298 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 755915606 ps |
| CPU time | 58.92 seconds |
| Started | Oct 15 07:22:06 AM UTC 24 |
| Finished | Oct 15 07:23:07 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551053298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.551053298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/35.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all.3361796651 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 20660493305 ps |
| CPU time | 255.93 seconds |
| Started | Oct 15 07:23:45 AM UTC 24 |
| Finished | Oct 15 07:28:05 AM UTC 24 |
| Peak memory | 267236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361796651 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all.3361796651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/35.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all_with_rand_reset.2984051222 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1518531120 ps |
| CPU time | 104.91 seconds |
| Started | Oct 15 07:23:45 AM UTC 24 |
| Finished | Oct 15 07:25:33 AM UTC 24 |
| Peak memory | 277272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2984051222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.a lert_handler_stress_all_with_rand_reset.2984051222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/36.alert_handler_entropy.550214980 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 29440457874 ps |
| CPU time | 2192.4 seconds |
| Started | Oct 15 07:25:03 AM UTC 24 |
| Finished | Oct 15 08:02:00 AM UTC 24 |
| Peak memory | 296292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550214980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.550214980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/36.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_alert_accum.325269314 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1435078708 ps |
| CPU time | 189.1 seconds |
| Started | Oct 15 07:24:54 AM UTC 24 |
| Finished | Oct 15 07:28:07 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325269314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.325269314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/36.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_intr_timeout.88641508 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 123193586 ps |
| CPU time | 13.19 seconds |
| Started | Oct 15 07:24:47 AM UTC 24 |
| Finished | Oct 15 07:25:02 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88641508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc _intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.88641508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg.4022920103 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 55309752263 ps |
| CPU time | 1299.06 seconds |
| Started | Oct 15 07:25:10 AM UTC 24 |
| Finished | Oct 15 07:47:05 AM UTC 24 |
| Peak memory | 283684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022920103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.4022920103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/36.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg_stub_clk.683533204 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 42595087462 ps |
| CPU time | 2467.25 seconds |
| Started | Oct 15 07:25:14 AM UTC 24 |
| Finished | Oct 15 08:06:48 AM UTC 24 |
| Peak memory | 298196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683533204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.683533204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/36.alert_handler_ping_timeout.82528434 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 5497632944 ps |
| CPU time | 197.37 seconds |
| Started | Oct 15 07:25:07 AM UTC 24 |
| Finished | Oct 15 07:28:28 AM UTC 24 |
| Peak memory | 260904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82528434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.82528434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_alerts.1667692869 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 554446225 ps |
| CPU time | 52.56 seconds |
| Started | Oct 15 07:24:19 AM UTC 24 |
| Finished | Oct 15 07:25:13 AM UTC 24 |
| Peak memory | 260956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667692869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1667692869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/36.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_classes.3305554483 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1009562313 ps |
| CPU time | 22.01 seconds |
| Started | Oct 15 07:24:38 AM UTC 24 |
| Finished | Oct 15 07:25:01 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305554483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3305554483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/36.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/36.alert_handler_sig_int_fail.3971329393 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 712955751 ps |
| CPU time | 53.39 seconds |
| Started | Oct 15 07:25:03 AM UTC 24 |
| Finished | Oct 15 07:25:58 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971329393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3971329393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/36.alert_handler_smoke.1620055629 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 1280373673 ps |
| CPU time | 65.08 seconds |
| Started | Oct 15 07:23:47 AM UTC 24 |
| Finished | Oct 15 07:24:53 AM UTC 24 |
| Peak memory | 266912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620055629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1620055629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/36.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all.1497207078 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 315295431 ps |
| CPU time | 27.68 seconds |
| Started | Oct 15 07:25:25 AM UTC 24 |
| Finished | Oct 15 07:25:54 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497207078 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all.1497207078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/36.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/37.alert_handler_entropy.1435151450 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 502237331785 ps |
| CPU time | 2342.63 seconds |
| Started | Oct 15 07:26:05 AM UTC 24 |
| Finished | Oct 15 08:05:34 AM UTC 24 |
| Peak memory | 300180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435151450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1435151450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/37.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_alert_accum.1670111863 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 20461033738 ps |
| CPU time | 70.97 seconds |
| Started | Oct 15 07:25:59 AM UTC 24 |
| Finished | Oct 15 07:27:11 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670111863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1670111863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/37.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_intr_timeout.1558412323 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 1821964664 ps |
| CPU time | 35.21 seconds |
| Started | Oct 15 07:25:54 AM UTC 24 |
| Finished | Oct 15 07:26:31 AM UTC 24 |
| Peak memory | 266896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558412323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1558412323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg.2899457723 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 25145424704 ps |
| CPU time | 2026.98 seconds |
| Started | Oct 15 07:26:19 AM UTC 24 |
| Finished | Oct 15 08:00:29 AM UTC 24 |
| Peak memory | 283700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899457723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2899457723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/37.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg_stub_clk.3184931814 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 52350855245 ps |
| CPU time | 2899.94 seconds |
| Started | Oct 15 07:26:19 AM UTC 24 |
| Finished | Oct 15 08:15:11 AM UTC 24 |
| Peak memory | 302500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184931814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3184931814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/37.alert_handler_ping_timeout.2901699847 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 8006533785 ps |
| CPU time | 309.43 seconds |
| Started | Oct 15 07:26:09 AM UTC 24 |
| Finished | Oct 15 07:31:22 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901699847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2901699847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_alerts.109137716 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 1355247204 ps |
| CPU time | 16.1 seconds |
| Started | Oct 15 07:25:47 AM UTC 24 |
| Finished | Oct 15 07:26:04 AM UTC 24 |
| Peak memory | 261028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109137716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.109137716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/37.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_classes.2691392466 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 2147796736 ps |
| CPU time | 38.24 seconds |
| Started | Oct 15 07:25:48 AM UTC 24 |
| Finished | Oct 15 07:26:28 AM UTC 24 |
| Peak memory | 260824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691392466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2691392466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/37.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/37.alert_handler_sig_int_fail.230924587 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 328363821 ps |
| CPU time | 36.07 seconds |
| Started | Oct 15 07:26:04 AM UTC 24 |
| Finished | Oct 15 07:26:41 AM UTC 24 |
| Peak memory | 267008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230924587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.230924587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/37.alert_handler_smoke.3212805518 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 78468084 ps |
| CPU time | 9.92 seconds |
| Started | Oct 15 07:25:35 AM UTC 24 |
| Finished | Oct 15 07:25:46 AM UTC 24 |
| Peak memory | 266984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212805518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3212805518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/37.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all.4065858988 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 6740090615 ps |
| CPU time | 407.49 seconds |
| Started | Oct 15 07:26:29 AM UTC 24 |
| Finished | Oct 15 07:33:22 AM UTC 24 |
| Peak memory | 266968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065858988 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all.4065858988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/37.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/38.alert_handler_entropy.3242914635 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 189559577694 ps |
| CPU time | 2434.5 seconds |
| Started | Oct 15 07:27:59 AM UTC 24 |
| Finished | Oct 15 08:08:59 AM UTC 24 |
| Peak memory | 302312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242914635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3242914635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/38.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_alert_accum.2601582237 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 2304398325 ps |
| CPU time | 194.39 seconds |
| Started | Oct 15 07:27:21 AM UTC 24 |
| Finished | Oct 15 07:30:38 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601582237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2601582237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/38.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_intr_timeout.3134177942 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 879720791 ps |
| CPU time | 79.61 seconds |
| Started | Oct 15 07:27:16 AM UTC 24 |
| Finished | Oct 15 07:28:38 AM UTC 24 |
| Peak memory | 266896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134177942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3134177942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg.2037313151 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 14527131758 ps |
| CPU time | 1386.7 seconds |
| Started | Oct 15 07:28:04 AM UTC 24 |
| Finished | Oct 15 07:51:29 AM UTC 24 |
| Peak memory | 299892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037313151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2037313151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/38.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg_stub_clk.3510722851 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 16946591794 ps |
| CPU time | 1528.69 seconds |
| Started | Oct 15 07:28:06 AM UTC 24 |
| Finished | Oct 15 07:53:52 AM UTC 24 |
| Peak memory | 300012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510722851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3510722851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/38.alert_handler_ping_timeout.2389332945 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 3224809394 ps |
| CPU time | 131.19 seconds |
| Started | Oct 15 07:27:59 AM UTC 24 |
| Finished | Oct 15 07:30:12 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389332945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2389332945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_alerts.2455499803 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 336163577 ps |
| CPU time | 23.89 seconds |
| Started | Oct 15 07:26:55 AM UTC 24 |
| Finished | Oct 15 07:27:20 AM UTC 24 |
| Peak memory | 261084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455499803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2455499803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/38.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_classes.1807702282 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 418921063 ps |
| CPU time | 51.78 seconds |
| Started | Oct 15 07:27:12 AM UTC 24 |
| Finished | Oct 15 07:28:06 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807702282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1807702282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/38.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/38.alert_handler_sig_int_fail.145544682 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1128334309 ps |
| CPU time | 57.65 seconds |
| Started | Oct 15 07:27:46 AM UTC 24 |
| Finished | Oct 15 07:28:45 AM UTC 24 |
| Peak memory | 267200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145544682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.145544682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/38.alert_handler_smoke.3295655255 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 518642646 ps |
| CPU time | 32.18 seconds |
| Started | Oct 15 07:26:42 AM UTC 24 |
| Finished | Oct 15 07:27:16 AM UTC 24 |
| Peak memory | 267176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295655255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3295655255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/38.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all.2759651100 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 31658875793 ps |
| CPU time | 1953.31 seconds |
| Started | Oct 15 07:28:07 AM UTC 24 |
| Finished | Oct 15 08:01:03 AM UTC 24 |
| Peak memory | 299812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759651100 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all.2759651100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/38.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/39.alert_handler_entropy.786684311 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 71152005353 ps |
| CPU time | 1815.94 seconds |
| Started | Oct 15 07:29:01 AM UTC 24 |
| Finished | Oct 15 07:59:39 AM UTC 24 |
| Peak memory | 299832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786684311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.786684311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/39.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_alert_accum.2681149905 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1949331122 ps |
| CPU time | 108.17 seconds |
| Started | Oct 15 07:28:47 AM UTC 24 |
| Finished | Oct 15 07:30:37 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681149905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2681149905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/39.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_intr_timeout.4038496414 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 200294708 ps |
| CPU time | 20.44 seconds |
| Started | Oct 15 07:28:39 AM UTC 24 |
| Finished | Oct 15 07:29:00 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038496414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.4038496414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg.1572707214 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 23854936355 ps |
| CPU time | 1615.36 seconds |
| Started | Oct 15 07:29:21 AM UTC 24 |
| Finished | Oct 15 07:56:36 AM UTC 24 |
| Peak memory | 283420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572707214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1572707214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/39.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg_stub_clk.2595266863 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 17150352126 ps |
| CPU time | 1461.3 seconds |
| Started | Oct 15 07:29:32 AM UTC 24 |
| Finished | Oct 15 07:54:11 AM UTC 24 |
| Peak memory | 297772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595266863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2595266863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/39.alert_handler_ping_timeout.3317680134 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 12692993777 ps |
| CPU time | 132.66 seconds |
| Started | Oct 15 07:29:10 AM UTC 24 |
| Finished | Oct 15 07:31:25 AM UTC 24 |
| Peak memory | 260904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317680134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3317680134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_alerts.1414017539 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 608798740 ps |
| CPU time | 58.7 seconds |
| Started | Oct 15 07:28:20 AM UTC 24 |
| Finished | Oct 15 07:29:21 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414017539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1414017539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/39.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_classes.2564949191 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 2788476933 ps |
| CPU time | 39.08 seconds |
| Started | Oct 15 07:28:29 AM UTC 24 |
| Finished | Oct 15 07:29:09 AM UTC 24 |
| Peak memory | 266968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564949191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2564949191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/39.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/39.alert_handler_sig_int_fail.4110892954 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 553319198 ps |
| CPU time | 48.24 seconds |
| Started | Oct 15 07:28:48 AM UTC 24 |
| Finished | Oct 15 07:29:38 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110892954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.4110892954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/39.alert_handler_smoke.2998879306 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 850479256 ps |
| CPU time | 26.11 seconds |
| Started | Oct 15 07:28:19 AM UTC 24 |
| Finished | Oct 15 07:28:47 AM UTC 24 |
| Peak memory | 260768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998879306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2998879306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/39.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/4.alert_handler_alert_accum_saturation.3434266172 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 26949626 ps |
| CPU time | 3.23 seconds |
| Started | Oct 15 06:22:41 AM UTC 24 |
| Finished | Oct 15 06:22:45 AM UTC 24 |
| Peak memory | 260960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434266172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3434266172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy.3740831592 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 50304985779 ps |
| CPU time | 2925.86 seconds |
| Started | Oct 15 06:22:35 AM UTC 24 |
| Finished | Oct 15 07:11:52 AM UTC 24 |
| Peak memory | 302296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740831592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3740831592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy_stress.3094605807 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 274546156 ps |
| CPU time | 9.47 seconds |
| Started | Oct 15 06:22:41 AM UTC 24 |
| Finished | Oct 15 06:22:52 AM UTC 24 |
| Peak memory | 261028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094605807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3094605807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_intr_timeout.584378721 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 384083452 ps |
| CPU time | 46.25 seconds |
| Started | Oct 15 06:22:33 AM UTC 24 |
| Finished | Oct 15 06:23:21 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584378721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.584378721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg.585326673 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 25865608240 ps |
| CPU time | 1776.33 seconds |
| Started | Oct 15 06:22:39 AM UTC 24 |
| Finished | Oct 15 06:52:35 AM UTC 24 |
| Peak memory | 293724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585326673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.585326673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg_stub_clk.3399570008 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 5245275882 ps |
| CPU time | 555.3 seconds |
| Started | Oct 15 06:22:39 AM UTC 24 |
| Finished | Oct 15 06:32:02 AM UTC 24 |
| Peak memory | 277212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399570008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3399570008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/4.alert_handler_ping_timeout.2649676473 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7886261580 ps |
| CPU time | 105.47 seconds |
| Started | Oct 15 06:22:39 AM UTC 24 |
| Finished | Oct 15 06:24:26 AM UTC 24 |
| Peak memory | 267044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649676473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2649676473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_alerts.3279966075 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 419762945 ps |
| CPU time | 22.93 seconds |
| Started | Oct 15 06:22:29 AM UTC 24 |
| Finished | Oct 15 06:22:53 AM UTC 24 |
| Peak memory | 266912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279966075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3279966075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_classes.2035566138 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 78803267 ps |
| CPU time | 8.22 seconds |
| Started | Oct 15 06:22:31 AM UTC 24 |
| Finished | Oct 15 06:22:40 AM UTC 24 |
| Peak memory | 265116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035566138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2035566138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/4.alert_handler_sec_cm.4059813800 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 848762969 ps |
| CPU time | 32.74 seconds |
| Started | Oct 15 06:22:44 AM UTC 24 |
| Finished | Oct 15 06:23:19 AM UTC 24 |
| Peak memory | 295052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059813800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.4059813800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/4.alert_handler_sig_int_fail.3698625852 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 219513455 ps |
| CPU time | 10.04 seconds |
| Started | Oct 15 06:22:33 AM UTC 24 |
| Finished | Oct 15 06:22:45 AM UTC 24 |
| Peak memory | 261056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698625852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3698625852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/4.alert_handler_smoke.4017102749 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 489937057 ps |
| CPU time | 10.25 seconds |
| Started | Oct 15 06:22:27 AM UTC 24 |
| Finished | Oct 15 06:22:38 AM UTC 24 |
| Peak memory | 261028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017102749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.4017102749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all_with_rand_reset.3657732814 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3425777729 ps |
| CPU time | 186.57 seconds |
| Started | Oct 15 06:22:41 AM UTC 24 |
| Finished | Oct 15 06:25:51 AM UTC 24 |
| Peak memory | 277332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3657732814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.al ert_handler_stress_all_with_rand_reset.3657732814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/40.alert_handler_entropy.2620540320 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 148934792370 ps |
| CPU time | 2555.79 seconds |
| Started | Oct 15 07:31:07 AM UTC 24 |
| Finished | Oct 15 08:14:11 AM UTC 24 |
| Peak memory | 302308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620540320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2620540320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/40.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_alert_accum.3395011383 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 2000856141 ps |
| CPU time | 140.93 seconds |
| Started | Oct 15 07:30:46 AM UTC 24 |
| Finished | Oct 15 07:33:10 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395011383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3395011383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/40.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_intr_timeout.3651644889 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 588452487 ps |
| CPU time | 37.82 seconds |
| Started | Oct 15 07:30:39 AM UTC 24 |
| Finished | Oct 15 07:31:19 AM UTC 24 |
| Peak memory | 260752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651644889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3651644889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg.1290655323 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 40135258199 ps |
| CPU time | 1099.1 seconds |
| Started | Oct 15 07:31:20 AM UTC 24 |
| Finished | Oct 15 07:49:52 AM UTC 24 |
| Peak memory | 283492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290655323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1290655323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/40.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg_stub_clk.2683222286 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 54942750818 ps |
| CPU time | 3283.97 seconds |
| Started | Oct 15 07:31:23 AM UTC 24 |
| Finished | Oct 15 08:26:44 AM UTC 24 |
| Peak memory | 302236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683222286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2683222286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/40.alert_handler_ping_timeout.3188108854 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 29946351211 ps |
| CPU time | 255.32 seconds |
| Started | Oct 15 07:31:20 AM UTC 24 |
| Finished | Oct 15 07:35:40 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188108854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3188108854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_alerts.2530908027 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 1714584897 ps |
| CPU time | 45.39 seconds |
| Started | Oct 15 07:30:13 AM UTC 24 |
| Finished | Oct 15 07:31:00 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530908027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2530908027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/40.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_classes.25344956 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 506921892 ps |
| CPU time | 26.14 seconds |
| Started | Oct 15 07:30:38 AM UTC 24 |
| Finished | Oct 15 07:31:06 AM UTC 24 |
| Peak memory | 266980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25344956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran dom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.25344956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/40.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/40.alert_handler_sig_int_fail.1452558531 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 775492042 ps |
| CPU time | 16.98 seconds |
| Started | Oct 15 07:31:01 AM UTC 24 |
| Finished | Oct 15 07:31:19 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452558531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1452558531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/40.alert_handler_smoke.3686128589 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 4313612272 ps |
| CPU time | 64.74 seconds |
| Started | Oct 15 07:29:39 AM UTC 24 |
| Finished | Oct 15 07:30:46 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686128589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3686128589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/40.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all.1715141969 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 71043324727 ps |
| CPU time | 4059.27 seconds |
| Started | Oct 15 07:31:26 AM UTC 24 |
| Finished | Oct 15 08:39:50 AM UTC 24 |
| Peak memory | 318616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715141969 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all.1715141969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/40.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all_with_rand_reset.934847456 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 5815882078 ps |
| CPU time | 611.24 seconds |
| Started | Oct 15 07:31:36 AM UTC 24 |
| Finished | Oct 15 07:41:55 AM UTC 24 |
| Peak memory | 293796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=934847456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.al ert_handler_stress_all_with_rand_reset.934847456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/41.alert_handler_entropy.2371269111 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 9012305712 ps |
| CPU time | 939 seconds |
| Started | Oct 15 07:33:11 AM UTC 24 |
| Finished | Oct 15 07:49:02 AM UTC 24 |
| Peak memory | 283368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371269111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2371269111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/41.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_alert_accum.602796309 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 7479969226 ps |
| CPU time | 162.54 seconds |
| Started | Oct 15 07:32:27 AM UTC 24 |
| Finished | Oct 15 07:35:13 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602796309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.602796309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/41.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_intr_timeout.435376141 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 5851754846 ps |
| CPU time | 98.72 seconds |
| Started | Oct 15 07:32:15 AM UTC 24 |
| Finished | Oct 15 07:33:56 AM UTC 24 |
| Peak memory | 266996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435376141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.435376141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg.1656751585 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 59134233073 ps |
| CPU time | 1913.39 seconds |
| Started | Oct 15 07:33:23 AM UTC 24 |
| Finished | Oct 15 08:05:38 AM UTC 24 |
| Peak memory | 297784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656751585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1656751585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/41.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg_stub_clk.808830460 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 49492315863 ps |
| CPU time | 2982.46 seconds |
| Started | Oct 15 07:33:50 AM UTC 24 |
| Finished | Oct 15 08:24:05 AM UTC 24 |
| Peak memory | 302308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808830460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.808830460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/41.alert_handler_ping_timeout.2051567929 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 24501724424 ps |
| CPU time | 272.33 seconds |
| Started | Oct 15 07:33:21 AM UTC 24 |
| Finished | Oct 15 07:37:57 AM UTC 24 |
| Peak memory | 261100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051567929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2051567929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_alerts.3203529467 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1240948197 ps |
| CPU time | 23.06 seconds |
| Started | Oct 15 07:32:02 AM UTC 24 |
| Finished | Oct 15 07:32:27 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203529467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3203529467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/41.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_classes.3219848960 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 97594922 ps |
| CPU time | 4.9 seconds |
| Started | Oct 15 07:32:08 AM UTC 24 |
| Finished | Oct 15 07:32:14 AM UTC 24 |
| Peak memory | 250588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219848960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3219848960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/41.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/41.alert_handler_sig_int_fail.1821998677 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1169518623 ps |
| CPU time | 59.05 seconds |
| Started | Oct 15 07:32:48 AM UTC 24 |
| Finished | Oct 15 07:33:49 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821998677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1821998677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/41.alert_handler_smoke.2609844076 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 154659752 ps |
| CPU time | 21.06 seconds |
| Started | Oct 15 07:31:39 AM UTC 24 |
| Finished | Oct 15 07:32:02 AM UTC 24 |
| Peak memory | 266912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609844076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2609844076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/41.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all.2121607673 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 19909838632 ps |
| CPU time | 1058.28 seconds |
| Started | Oct 15 07:33:56 AM UTC 24 |
| Finished | Oct 15 07:51:47 AM UTC 24 |
| Peak memory | 295716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121607673 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all.2121607673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/41.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all_with_rand_reset.2012042479 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 3529260301 ps |
| CPU time | 75.03 seconds |
| Started | Oct 15 07:34:58 AM UTC 24 |
| Finished | Oct 15 07:36:15 AM UTC 24 |
| Peak memory | 277604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2012042479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.a lert_handler_stress_all_with_rand_reset.2012042479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/41.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/42.alert_handler_entropy.3855624395 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 94458339188 ps |
| CPU time | 1680.09 seconds |
| Started | Oct 15 07:35:52 AM UTC 24 |
| Finished | Oct 15 08:04:12 AM UTC 24 |
| Peak memory | 277288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855624395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3855624395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/42.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_alert_accum.3137410492 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 4681870326 ps |
| CPU time | 213.37 seconds |
| Started | Oct 15 07:35:33 AM UTC 24 |
| Finished | Oct 15 07:39:09 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137410492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3137410492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/42.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_intr_timeout.786242098 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 218140457 ps |
| CPU time | 27.62 seconds |
| Started | Oct 15 07:35:27 AM UTC 24 |
| Finished | Oct 15 07:35:55 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786242098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.786242098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg_stub_clk.1587437593 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 119456736814 ps |
| CPU time | 2080.45 seconds |
| Started | Oct 15 07:36:16 AM UTC 24 |
| Finished | Oct 15 08:11:21 AM UTC 24 |
| Peak memory | 293864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587437593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1587437593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/42.alert_handler_ping_timeout.3181453835 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 34701115877 ps |
| CPU time | 323.39 seconds |
| Started | Oct 15 07:35:56 AM UTC 24 |
| Finished | Oct 15 07:41:24 AM UTC 24 |
| Peak memory | 260908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181453835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3181453835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_alerts.244452595 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 2259372334 ps |
| CPU time | 26.4 seconds |
| Started | Oct 15 07:35:04 AM UTC 24 |
| Finished | Oct 15 07:35:32 AM UTC 24 |
| Peak memory | 267044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244452595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.244452595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/42.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_classes.302483732 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2206397736 ps |
| CPU time | 36 seconds |
| Started | Oct 15 07:35:14 AM UTC 24 |
| Finished | Oct 15 07:35:51 AM UTC 24 |
| Peak memory | 260820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302483732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.302483732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/42.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/42.alert_handler_sig_int_fail.2284955254 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 620248888 ps |
| CPU time | 53.44 seconds |
| Started | Oct 15 07:35:41 AM UTC 24 |
| Finished | Oct 15 07:36:36 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284955254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2284955254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/42.alert_handler_smoke.141488972 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1181460795 ps |
| CPU time | 53.28 seconds |
| Started | Oct 15 07:35:02 AM UTC 24 |
| Finished | Oct 15 07:35:57 AM UTC 24 |
| Peak memory | 267168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141488972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.141488972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/42.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all.1008722377 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 638568788015 ps |
| CPU time | 1754.49 seconds |
| Started | Oct 15 07:36:37 AM UTC 24 |
| Finished | Oct 15 08:06:11 AM UTC 24 |
| Peak memory | 300068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008722377 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all.1008722377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/42.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/43.alert_handler_entropy.702317774 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 37305054265 ps |
| CPU time | 1160.39 seconds |
| Started | Oct 15 07:38:39 AM UTC 24 |
| Finished | Oct 15 07:58:13 AM UTC 24 |
| Peak memory | 299760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702317774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.702317774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/43.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_alert_accum.2915972820 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 661637628 ps |
| CPU time | 49.98 seconds |
| Started | Oct 15 07:38:13 AM UTC 24 |
| Finished | Oct 15 07:39:04 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915972820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2915972820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/43.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_intr_timeout.2783731963 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 213668390 ps |
| CPU time | 9.67 seconds |
| Started | Oct 15 07:38:00 AM UTC 24 |
| Finished | Oct 15 07:38:11 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783731963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2783731963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg.3013112484 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 44500883148 ps |
| CPU time | 1579.62 seconds |
| Started | Oct 15 07:39:05 AM UTC 24 |
| Finished | Oct 15 08:05:43 AM UTC 24 |
| Peak memory | 300084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013112484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3013112484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/43.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg_stub_clk.846302703 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 23466637582 ps |
| CPU time | 1093.86 seconds |
| Started | Oct 15 07:39:13 AM UTC 24 |
| Finished | Oct 15 07:57:40 AM UTC 24 |
| Peak memory | 293860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846302703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.846302703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/43.alert_handler_ping_timeout.2034816580 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 13336406418 ps |
| CPU time | 204.18 seconds |
| Started | Oct 15 07:38:53 AM UTC 24 |
| Finished | Oct 15 07:42:20 AM UTC 24 |
| Peak memory | 260904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034816580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2034816580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_alerts.2466953572 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 528762250 ps |
| CPU time | 38.08 seconds |
| Started | Oct 15 07:37:58 AM UTC 24 |
| Finished | Oct 15 07:38:38 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466953572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2466953572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/43.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_classes.3415649911 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 1438813513 ps |
| CPU time | 33.13 seconds |
| Started | Oct 15 07:37:58 AM UTC 24 |
| Finished | Oct 15 07:38:33 AM UTC 24 |
| Peak memory | 260956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415649911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3415649911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/43.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/43.alert_handler_sig_int_fail.3952659015 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1246225733 ps |
| CPU time | 54.06 seconds |
| Started | Oct 15 07:38:34 AM UTC 24 |
| Finished | Oct 15 07:39:29 AM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952659015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3952659015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/43.alert_handler_smoke.3242685870 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 1488097668 ps |
| CPU time | 26.02 seconds |
| Started | Oct 15 07:37:33 AM UTC 24 |
| Finished | Oct 15 07:38:00 AM UTC 24 |
| Peak memory | 267176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242685870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3242685870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/43.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all_with_rand_reset.3430950924 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 5598720573 ps |
| CPU time | 408.37 seconds |
| Started | Oct 15 07:39:14 AM UTC 24 |
| Finished | Oct 15 07:46:08 AM UTC 24 |
| Peak memory | 277340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3430950924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.a lert_handler_stress_all_with_rand_reset.3430950924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/44.alert_handler_entropy.3697722963 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 102822451732 ps |
| CPU time | 2367.87 seconds |
| Started | Oct 15 07:41:20 AM UTC 24 |
| Finished | Oct 15 08:21:15 AM UTC 24 |
| Peak memory | 296220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697722963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3697722963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/44.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_alert_accum.817006022 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2214077974 ps |
| CPU time | 62.12 seconds |
| Started | Oct 15 07:40:26 AM UTC 24 |
| Finished | Oct 15 07:41:30 AM UTC 24 |
| Peak memory | 267228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817006022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.817006022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/44.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_intr_timeout.998252461 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 411026092 ps |
| CPU time | 41.38 seconds |
| Started | Oct 15 07:40:21 AM UTC 24 |
| Finished | Oct 15 07:41:04 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998252461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.998252461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg.920619158 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 76515065650 ps |
| CPU time | 1362.98 seconds |
| Started | Oct 15 07:41:25 AM UTC 24 |
| Finished | Oct 15 08:04:23 AM UTC 24 |
| Peak memory | 293732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920619158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.920619158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/44.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg_stub_clk.1320695507 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 17870682691 ps |
| CPU time | 1366.02 seconds |
| Started | Oct 15 07:41:31 AM UTC 24 |
| Finished | Oct 15 08:04:32 AM UTC 24 |
| Peak memory | 299900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320695507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1320695507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/44.alert_handler_ping_timeout.3261161089 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 7706647896 ps |
| CPU time | 397.61 seconds |
| Started | Oct 15 07:41:23 AM UTC 24 |
| Finished | Oct 15 07:48:06 AM UTC 24 |
| Peak memory | 260908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261161089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3261161089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_alerts.2675276996 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 880223917 ps |
| CPU time | 44.54 seconds |
| Started | Oct 15 07:39:30 AM UTC 24 |
| Finished | Oct 15 07:40:16 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675276996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2675276996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/44.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_classes.2573395473 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 3377073989 ps |
| CPU time | 59.83 seconds |
| Started | Oct 15 07:40:17 AM UTC 24 |
| Finished | Oct 15 07:41:19 AM UTC 24 |
| Peak memory | 267036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573395473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2573395473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/44.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/44.alert_handler_sig_int_fail.1733186144 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 471699734 ps |
| CPU time | 31.65 seconds |
| Started | Oct 15 07:41:05 AM UTC 24 |
| Finished | Oct 15 07:41:38 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733186144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1733186144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/44.alert_handler_smoke.996225731 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 3460222002 ps |
| CPU time | 62.79 seconds |
| Started | Oct 15 07:39:21 AM UTC 24 |
| Finished | Oct 15 07:40:25 AM UTC 24 |
| Peak memory | 266968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996225731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.996225731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/44.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all.1536402940 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 15335655200 ps |
| CPU time | 1220.18 seconds |
| Started | Oct 15 07:41:39 AM UTC 24 |
| Finished | Oct 15 08:02:13 AM UTC 24 |
| Peak memory | 299812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536402940 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all.1536402940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/44.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/45.alert_handler_entropy.3326854395 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 55734392841 ps |
| CPU time | 2018.69 seconds |
| Started | Oct 15 07:43:25 AM UTC 24 |
| Finished | Oct 15 08:17:27 AM UTC 24 |
| Peak memory | 297088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326854395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3326854395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/45.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_alert_accum.2720938910 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 6398345712 ps |
| CPU time | 83.05 seconds |
| Started | Oct 15 07:42:39 AM UTC 24 |
| Finished | Oct 15 07:44:04 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720938910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2720938910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/45.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_intr_timeout.2511371868 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 769157207 ps |
| CPU time | 63.02 seconds |
| Started | Oct 15 07:42:23 AM UTC 24 |
| Finished | Oct 15 07:43:28 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511371868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2511371868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg.1476445493 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 347667462616 ps |
| CPU time | 1693.88 seconds |
| Started | Oct 15 07:44:01 AM UTC 24 |
| Finished | Oct 15 08:12:34 AM UTC 24 |
| Peak memory | 283428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476445493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1476445493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/45.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg_stub_clk.3528920970 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 13299018751 ps |
| CPU time | 1447.33 seconds |
| Started | Oct 15 07:44:05 AM UTC 24 |
| Finished | Oct 15 08:08:30 AM UTC 24 |
| Peak memory | 299820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528920970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3528920970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/45.alert_handler_ping_timeout.2981913175 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 6698116039 ps |
| CPU time | 146.14 seconds |
| Started | Oct 15 07:43:29 AM UTC 24 |
| Finished | Oct 15 07:45:58 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981913175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2981913175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_alerts.2948151902 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2986212695 ps |
| CPU time | 55.05 seconds |
| Started | Oct 15 07:42:20 AM UTC 24 |
| Finished | Oct 15 07:43:17 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948151902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2948151902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/45.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_classes.857181915 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 575939669 ps |
| CPU time | 15.67 seconds |
| Started | Oct 15 07:42:21 AM UTC 24 |
| Finished | Oct 15 07:42:38 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857181915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.857181915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/45.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/45.alert_handler_sig_int_fail.399276591 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1915163600 ps |
| CPU time | 59.44 seconds |
| Started | Oct 15 07:43:19 AM UTC 24 |
| Finished | Oct 15 07:44:20 AM UTC 24 |
| Peak memory | 266936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399276591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.399276591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/45.alert_handler_smoke.2414492598 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 173397269 ps |
| CPU time | 14.13 seconds |
| Started | Oct 15 07:42:07 AM UTC 24 |
| Finished | Oct 15 07:42:22 AM UTC 24 |
| Peak memory | 266920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414492598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2414492598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/45.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all.400181708 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 10009860955 ps |
| CPU time | 869.5 seconds |
| Started | Oct 15 07:44:21 AM UTC 24 |
| Finished | Oct 15 07:59:02 AM UTC 24 |
| Peak memory | 295968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400181708 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all.400181708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/45.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/46.alert_handler_entropy.942504789 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 28734868014 ps |
| CPU time | 1405.96 seconds |
| Started | Oct 15 07:46:31 AM UTC 24 |
| Finished | Oct 15 08:10:13 AM UTC 24 |
| Peak memory | 293748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942504789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.942504789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/46.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_alert_accum.3935965277 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 21460252046 ps |
| CPU time | 175.51 seconds |
| Started | Oct 15 07:46:09 AM UTC 24 |
| Finished | Oct 15 07:49:07 AM UTC 24 |
| Peak memory | 267228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935965277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3935965277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/46.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_intr_timeout.558915235 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 823189045 ps |
| CPU time | 23.28 seconds |
| Started | Oct 15 07:45:58 AM UTC 24 |
| Finished | Oct 15 07:46:23 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558915235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.558915235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg.588643311 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 19447190770 ps |
| CPU time | 1833.03 seconds |
| Started | Oct 15 07:46:43 AM UTC 24 |
| Finished | Oct 15 08:17:37 AM UTC 24 |
| Peak memory | 299760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588643311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.588643311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/46.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg_stub_clk.4119542629 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 235096702988 ps |
| CPU time | 2459.05 seconds |
| Started | Oct 15 07:46:47 AM UTC 24 |
| Finished | Oct 15 08:28:13 AM UTC 24 |
| Peak memory | 296164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119542629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.4119542629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/46.alert_handler_ping_timeout.4221560265 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 9608701572 ps |
| CPU time | 505.33 seconds |
| Started | Oct 15 07:46:33 AM UTC 24 |
| Finished | Oct 15 07:55:05 AM UTC 24 |
| Peak memory | 260904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221560265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.4221560265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_alerts.1950395684 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 2038914389 ps |
| CPU time | 78.97 seconds |
| Started | Oct 15 07:45:26 AM UTC 24 |
| Finished | Oct 15 07:46:47 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950395684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1950395684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/46.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_classes.3955270033 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 1244428987 ps |
| CPU time | 45.09 seconds |
| Started | Oct 15 07:45:45 AM UTC 24 |
| Finished | Oct 15 07:46:32 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955270033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3955270033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/46.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/46.alert_handler_sig_int_fail.2510374247 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 426264226 ps |
| CPU time | 21.44 seconds |
| Started | Oct 15 07:46:24 AM UTC 24 |
| Finished | Oct 15 07:46:47 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510374247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2510374247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/46.alert_handler_smoke.4182892650 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 947177884 ps |
| CPU time | 79.91 seconds |
| Started | Oct 15 07:45:08 AM UTC 24 |
| Finished | Oct 15 07:46:30 AM UTC 24 |
| Peak memory | 266912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182892650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.4182892650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/46.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all.1198969125 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 43942415512 ps |
| CPU time | 2644.4 seconds |
| Started | Oct 15 07:46:48 AM UTC 24 |
| Finished | Oct 15 08:31:22 AM UTC 24 |
| Peak memory | 302496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198969125 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all.1198969125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/46.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/47.alert_handler_entropy.305134269 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 17531932251 ps |
| CPU time | 900.93 seconds |
| Started | Oct 15 07:48:50 AM UTC 24 |
| Finished | Oct 15 08:04:02 AM UTC 24 |
| Peak memory | 283556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305134269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.305134269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/47.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_alert_accum.1586136481 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1786929166 ps |
| CPU time | 80.65 seconds |
| Started | Oct 15 07:48:12 AM UTC 24 |
| Finished | Oct 15 07:49:35 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586136481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1586136481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/47.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_intr_timeout.529397945 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1005771484 ps |
| CPU time | 53.35 seconds |
| Started | Oct 15 07:48:08 AM UTC 24 |
| Finished | Oct 15 07:49:03 AM UTC 24 |
| Peak memory | 261056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529397945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.529397945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg.1707803270 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 25245052145 ps |
| CPU time | 1410.08 seconds |
| Started | Oct 15 07:49:04 AM UTC 24 |
| Finished | Oct 15 08:12:51 AM UTC 24 |
| Peak memory | 283448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707803270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1707803270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/47.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg_stub_clk.1779995163 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 37389635847 ps |
| CPU time | 2866.98 seconds |
| Started | Oct 15 07:49:10 AM UTC 24 |
| Finished | Oct 15 08:37:29 AM UTC 24 |
| Peak memory | 285872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779995163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1779995163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/47.alert_handler_ping_timeout.3298598195 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 25458703278 ps |
| CPU time | 323.6 seconds |
| Started | Oct 15 07:49:04 AM UTC 24 |
| Finished | Oct 15 07:54:32 AM UTC 24 |
| Peak memory | 260908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298598195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3298598195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_alerts.4009348521 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1285917239 ps |
| CPU time | 18.46 seconds |
| Started | Oct 15 07:47:33 AM UTC 24 |
| Finished | Oct 15 07:47:53 AM UTC 24 |
| Peak memory | 260892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009348521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.4009348521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/47.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_classes.603063092 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1640797106 ps |
| CPU time | 45.38 seconds |
| Started | Oct 15 07:47:55 AM UTC 24 |
| Finished | Oct 15 07:48:42 AM UTC 24 |
| Peak memory | 261084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603063092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.603063092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/47.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/47.alert_handler_sig_int_fail.478355491 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 731529323 ps |
| CPU time | 69.41 seconds |
| Started | Oct 15 07:48:43 AM UTC 24 |
| Finished | Oct 15 07:49:54 AM UTC 24 |
| Peak memory | 267200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478355491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.478355491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/47.alert_handler_smoke.3860529406 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 905350189 ps |
| CPU time | 23.54 seconds |
| Started | Oct 15 07:47:07 AM UTC 24 |
| Finished | Oct 15 07:47:32 AM UTC 24 |
| Peak memory | 266984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860529406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3860529406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/47.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all.190931625 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 124782407032 ps |
| CPU time | 1991.31 seconds |
| Started | Oct 15 07:49:10 AM UTC 24 |
| Finished | Oct 15 08:22:45 AM UTC 24 |
| Peak memory | 283624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190931625 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all.190931625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/47.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all_with_rand_reset.3918327711 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 2166212385 ps |
| CPU time | 330.53 seconds |
| Started | Oct 15 07:49:35 AM UTC 24 |
| Finished | Oct 15 07:55:11 AM UTC 24 |
| Peak memory | 283092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3918327711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.a lert_handler_stress_all_with_rand_reset.3918327711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/48.alert_handler_entropy.2762152976 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 42625195568 ps |
| CPU time | 2187.67 seconds |
| Started | Oct 15 07:50:27 AM UTC 24 |
| Finished | Oct 15 08:27:19 AM UTC 24 |
| Peak memory | 286188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762152976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2762152976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/48.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_alert_accum.153750385 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 555958619 ps |
| CPU time | 71.84 seconds |
| Started | Oct 15 07:50:05 AM UTC 24 |
| Finished | Oct 15 07:51:19 AM UTC 24 |
| Peak memory | 267164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153750385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.153750385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/48.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_intr_timeout.2867046454 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 25372024 ps |
| CPU time | 5.07 seconds |
| Started | Oct 15 07:49:58 AM UTC 24 |
| Finished | Oct 15 07:50:04 AM UTC 24 |
| Peak memory | 250516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867046454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2867046454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg.1236383300 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 21567181502 ps |
| CPU time | 983.72 seconds |
| Started | Oct 15 07:51:10 AM UTC 24 |
| Finished | Oct 15 08:07:47 AM UTC 24 |
| Peak memory | 300080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236383300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1236383300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/48.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg_stub_clk.2277902754 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 38545386284 ps |
| CPU time | 2330.05 seconds |
| Started | Oct 15 07:51:19 AM UTC 24 |
| Finished | Oct 15 08:30:35 AM UTC 24 |
| Peak memory | 285988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277902754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2277902754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/48.alert_handler_ping_timeout.467734609 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 3838345402 ps |
| CPU time | 172.6 seconds |
| Started | Oct 15 07:51:06 AM UTC 24 |
| Finished | Oct 15 07:54:02 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467734609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.467734609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_alerts.9844114 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 963250622 ps |
| CPU time | 81.58 seconds |
| Started | Oct 15 07:49:54 AM UTC 24 |
| Finished | Oct 15 07:51:17 AM UTC 24 |
| Peak memory | 260796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9844114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_rand om_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.9844114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/48.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_classes.1126848939 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 365040302 ps |
| CPU time | 27.52 seconds |
| Started | Oct 15 07:49:55 AM UTC 24 |
| Finished | Oct 15 07:50:24 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126848939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1126848939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/48.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/48.alert_handler_sig_int_fail.3225490323 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1005956156 ps |
| CPU time | 43.88 seconds |
| Started | Oct 15 07:50:24 AM UTC 24 |
| Finished | Oct 15 07:51:10 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225490323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3225490323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/48.alert_handler_smoke.794844089 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 761649673 ps |
| CPU time | 49.59 seconds |
| Started | Oct 15 07:49:35 AM UTC 24 |
| Finished | Oct 15 07:50:27 AM UTC 24 |
| Peak memory | 260308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794844089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.794844089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/48.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all.3783955090 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 160968098947 ps |
| CPU time | 2369.55 seconds |
| Started | Oct 15 07:51:20 AM UTC 24 |
| Finished | Oct 15 08:31:16 AM UTC 24 |
| Peak memory | 296368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783955090 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all.3783955090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/48.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/49.alert_handler_entropy.1403692947 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 29269686050 ps |
| CPU time | 1588.18 seconds |
| Started | Oct 15 07:52:19 AM UTC 24 |
| Finished | Oct 15 08:19:06 AM UTC 24 |
| Peak memory | 283504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403692947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1403692947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/49.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_alert_accum.3388797193 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 723459524 ps |
| CPU time | 29.6 seconds |
| Started | Oct 15 07:52:05 AM UTC 24 |
| Finished | Oct 15 07:52:36 AM UTC 24 |
| Peak memory | 266900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388797193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3388797193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/49.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_intr_timeout.2604875146 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 23635758 ps |
| CPU time | 4.52 seconds |
| Started | Oct 15 07:51:59 AM UTC 24 |
| Finished | Oct 15 07:52:05 AM UTC 24 |
| Peak memory | 250588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604875146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2604875146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg.548180941 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 43437956843 ps |
| CPU time | 1064.4 seconds |
| Started | Oct 15 07:52:37 AM UTC 24 |
| Finished | Oct 15 08:10:34 AM UTC 24 |
| Peak memory | 283444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548180941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.548180941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/49.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg_stub_clk.3439444190 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 28974187317 ps |
| CPU time | 1528.3 seconds |
| Started | Oct 15 07:52:40 AM UTC 24 |
| Finished | Oct 15 08:18:25 AM UTC 24 |
| Peak memory | 283440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439444190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3439444190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/49.alert_handler_ping_timeout.2737823122 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 11621625961 ps |
| CPU time | 323.77 seconds |
| Started | Oct 15 07:52:26 AM UTC 24 |
| Finished | Oct 15 07:57:54 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737823122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2737823122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_alerts.844755747 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 725484672 ps |
| CPU time | 34.71 seconds |
| Started | Oct 15 07:51:49 AM UTC 24 |
| Finished | Oct 15 07:52:25 AM UTC 24 |
| Peak memory | 266904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844755747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.844755747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/49.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_classes.1931179277 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 545704795 ps |
| CPU time | 14.4 seconds |
| Started | Oct 15 07:51:51 AM UTC 24 |
| Finished | Oct 15 07:52:07 AM UTC 24 |
| Peak memory | 260756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931179277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1931179277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/49.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/49.alert_handler_sig_int_fail.896309577 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2458914586 ps |
| CPU time | 50.72 seconds |
| Started | Oct 15 07:52:07 AM UTC 24 |
| Finished | Oct 15 07:53:00 AM UTC 24 |
| Peak memory | 267264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896309577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.896309577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/49.alert_handler_smoke.3271329412 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 580033523 ps |
| CPU time | 33.09 seconds |
| Started | Oct 15 07:51:43 AM UTC 24 |
| Finished | Oct 15 07:52:17 AM UTC 24 |
| Peak memory | 260840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271329412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3271329412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/49.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all.1722652220 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 91697993671 ps |
| CPU time | 1645.23 seconds |
| Started | Oct 15 07:53:00 AM UTC 24 |
| Finished | Oct 15 08:20:46 AM UTC 24 |
| Peak memory | 293672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722652220 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all.1722652220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/49.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all_with_rand_reset.4130080122 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 27710564881 ps |
| CPU time | 150.69 seconds |
| Started | Oct 15 07:53:07 AM UTC 24 |
| Finished | Oct 15 07:55:40 AM UTC 24 |
| Peak memory | 277412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4130080122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.a lert_handler_stress_all_with_rand_reset.4130080122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/5.alert_handler_alert_accum_saturation.1874891793 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 106118430 ps |
| CPU time | 4.25 seconds |
| Started | Oct 15 06:23:17 AM UTC 24 |
| Finished | Oct 15 06:23:22 AM UTC 24 |
| Peak memory | 261036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874891793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1874891793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy.3423178162 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 65956680018 ps |
| CPU time | 842.7 seconds |
| Started | Oct 15 06:23:01 AM UTC 24 |
| Finished | Oct 15 06:37:14 AM UTC 24 |
| Peak memory | 283360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423178162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3423178162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy_stress.3670664300 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 257423313 ps |
| CPU time | 21.25 seconds |
| Started | Oct 15 06:23:13 AM UTC 24 |
| Finished | Oct 15 06:23:36 AM UTC 24 |
| Peak memory | 260800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670664300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3670664300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_alert_accum.471757696 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1723994575 ps |
| CPU time | 30.44 seconds |
| Started | Oct 15 06:22:53 AM UTC 24 |
| Finished | Oct 15 06:23:25 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471757696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.471757696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_intr_timeout.2358757180 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1618442238 ps |
| CPU time | 51.07 seconds |
| Started | Oct 15 06:22:49 AM UTC 24 |
| Finished | Oct 15 06:23:42 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358757180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2358757180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg_stub_clk.247968371 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 268735525734 ps |
| CPU time | 2263.95 seconds |
| Started | Oct 15 06:23:09 AM UTC 24 |
| Finished | Oct 15 07:01:17 AM UTC 24 |
| Peak memory | 283444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247968371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.247968371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_alerts.3527856264 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 3286200580 ps |
| CPU time | 44.15 seconds |
| Started | Oct 15 06:22:47 AM UTC 24 |
| Finished | Oct 15 06:23:32 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527856264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3527856264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_classes.1856868948 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 491672532 ps |
| CPU time | 28.1 seconds |
| Started | Oct 15 06:22:47 AM UTC 24 |
| Finished | Oct 15 06:23:16 AM UTC 24 |
| Peak memory | 266972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856868948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1856868948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/5.alert_handler_sig_int_fail.2459772229 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 120439932 ps |
| CPU time | 10.74 seconds |
| Started | Oct 15 06:22:54 AM UTC 24 |
| Finished | Oct 15 06:23:06 AM UTC 24 |
| Peak memory | 264960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459772229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2459772229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/5.alert_handler_smoke.2686271742 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 796033275 ps |
| CPU time | 28.72 seconds |
| Started | Oct 15 06:22:45 AM UTC 24 |
| Finished | Oct 15 06:23:15 AM UTC 24 |
| Peak memory | 266980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686271742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2686271742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all.978807345 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 61613865613 ps |
| CPU time | 3173.4 seconds |
| Started | Oct 15 06:23:16 AM UTC 24 |
| Finished | Oct 15 07:16:45 AM UTC 24 |
| Peak memory | 319012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978807345 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all.978807345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/5.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/6.alert_handler_alert_accum_saturation.34694343 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 46452985 ps |
| CPU time | 5.97 seconds |
| Started | Oct 15 06:23:46 AM UTC 24 |
| Finished | Oct 15 06:23:53 AM UTC 24 |
| Peak memory | 261036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34694343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_h andler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_h andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.34694343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy.388096997 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 33669321230 ps |
| CPU time | 1117.11 seconds |
| Started | Oct 15 06:23:27 AM UTC 24 |
| Finished | Oct 15 06:42:18 AM UTC 24 |
| Peak memory | 283492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388096997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.388096997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy_stress.2778218548 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 114114687 ps |
| CPU time | 10.08 seconds |
| Started | Oct 15 06:23:41 AM UTC 24 |
| Finished | Oct 15 06:23:52 AM UTC 24 |
| Peak memory | 260836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778218548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2778218548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_alert_accum.3363773315 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 13104354597 ps |
| CPU time | 148 seconds |
| Started | Oct 15 06:23:23 AM UTC 24 |
| Finished | Oct 15 06:25:54 AM UTC 24 |
| Peak memory | 266960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363773315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3363773315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_intr_timeout.3160805790 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 979556696 ps |
| CPU time | 84.85 seconds |
| Started | Oct 15 06:23:22 AM UTC 24 |
| Finished | Oct 15 06:24:49 AM UTC 24 |
| Peak memory | 266976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160805790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3160805790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg.583551836 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 202294714555 ps |
| CPU time | 1767.97 seconds |
| Started | Oct 15 06:23:33 AM UTC 24 |
| Finished | Oct 15 06:53:21 AM UTC 24 |
| Peak memory | 283352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583551836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.583551836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg_stub_clk.1201944271 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 23679077194 ps |
| CPU time | 722.33 seconds |
| Started | Oct 15 06:23:36 AM UTC 24 |
| Finished | Oct 15 06:35:48 AM UTC 24 |
| Peak memory | 279336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201944271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1201944271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/6.alert_handler_ping_timeout.1362623345 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 6806204464 ps |
| CPU time | 106.04 seconds |
| Started | Oct 15 06:23:29 AM UTC 24 |
| Finished | Oct 15 06:25:17 AM UTC 24 |
| Peak memory | 261100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362623345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1362623345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_alerts.897913447 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 735797734 ps |
| CPU time | 41.27 seconds |
| Started | Oct 15 06:23:22 AM UTC 24 |
| Finished | Oct 15 06:24:05 AM UTC 24 |
| Peak memory | 261120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897913447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.897913447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_classes.1537902375 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 757271205 ps |
| CPU time | 16.71 seconds |
| Started | Oct 15 06:23:22 AM UTC 24 |
| Finished | Oct 15 06:23:40 AM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537902375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1537902375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/6.alert_handler_sig_int_fail.2776601235 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2246986216 ps |
| CPU time | 45.83 seconds |
| Started | Oct 15 06:23:25 AM UTC 24 |
| Finished | Oct 15 06:24:13 AM UTC 24 |
| Peak memory | 267264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776601235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2776601235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/6.alert_handler_smoke.3866458712 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 843774934 ps |
| CPU time | 21.12 seconds |
| Started | Oct 15 06:23:22 AM UTC 24 |
| Finished | Oct 15 06:23:44 AM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866458712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3866458712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/6.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/7.alert_handler_alert_accum_saturation.62651607 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 49838049 ps |
| CPU time | 3.83 seconds |
| Started | Oct 15 06:24:53 AM UTC 24 |
| Finished | Oct 15 06:24:58 AM UTC 24 |
| Peak memory | 260960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62651607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_h andler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_h andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.62651607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy.1645497221 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 137515213065 ps |
| CPU time | 2981.8 seconds |
| Started | Oct 15 06:24:36 AM UTC 24 |
| Finished | Oct 15 07:14:51 AM UTC 24 |
| Peak memory | 302296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645497221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1645497221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy_stress.4024153940 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 320262823 ps |
| CPU time | 26.68 seconds |
| Started | Oct 15 06:24:50 AM UTC 24 |
| Finished | Oct 15 06:25:18 AM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024153940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.4024153940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_intr_timeout.1455894292 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3452531671 ps |
| CPU time | 41.77 seconds |
| Started | Oct 15 06:24:05 AM UTC 24 |
| Finished | Oct 15 06:24:49 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455894292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1455894292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg_stub_clk.1059446734 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 6640582104 ps |
| CPU time | 688.49 seconds |
| Started | Oct 15 06:24:49 AM UTC 24 |
| Finished | Oct 15 06:36:26 AM UTC 24 |
| Peak memory | 283684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059446734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1059446734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/7.alert_handler_ping_timeout.3214458861 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 44979574978 ps |
| CPU time | 386.38 seconds |
| Started | Oct 15 06:24:44 AM UTC 24 |
| Finished | Oct 15 06:31:16 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214458861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3214458861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_alerts.4283908804 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1622971344 ps |
| CPU time | 56.33 seconds |
| Started | Oct 15 06:23:54 AM UTC 24 |
| Finished | Oct 15 06:24:52 AM UTC 24 |
| Peak memory | 266984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283908804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.4283908804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_classes.1825507305 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 880847970 ps |
| CPU time | 42.74 seconds |
| Started | Oct 15 06:24:00 AM UTC 24 |
| Finished | Oct 15 06:24:44 AM UTC 24 |
| Peak memory | 260832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825507305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1825507305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/7.alert_handler_sig_int_fail.2620366181 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 528622185 ps |
| CPU time | 13.78 seconds |
| Started | Oct 15 06:24:28 AM UTC 24 |
| Finished | Oct 15 06:24:43 AM UTC 24 |
| Peak memory | 260868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620366181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2620366181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/7.alert_handler_smoke.2403441022 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 8444325301 ps |
| CPU time | 66.43 seconds |
| Started | Oct 15 06:23:54 AM UTC 24 |
| Finished | Oct 15 06:25:02 AM UTC 24 |
| Peak memory | 260824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403441022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2403441022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all.3449554026 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 99275753242 ps |
| CPU time | 1848.57 seconds |
| Started | Oct 15 06:24:53 AM UTC 24 |
| Finished | Oct 15 06:56:02 AM UTC 24 |
| Peak memory | 293728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449554026 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all.3449554026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/7.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/8.alert_handler_alert_accum_saturation.354662715 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 58234491 ps |
| CPU time | 4.86 seconds |
| Started | Oct 15 06:25:55 AM UTC 24 |
| Finished | Oct 15 06:26:01 AM UTC 24 |
| Peak memory | 260964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354662715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.354662715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy.817839337 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 106250788845 ps |
| CPU time | 2336.39 seconds |
| Started | Oct 15 06:25:36 AM UTC 24 |
| Finished | Oct 15 07:04:58 AM UTC 24 |
| Peak memory | 293924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817839337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.817839337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy_stress.968311660 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 144898640 ps |
| CPU time | 10.08 seconds |
| Started | Oct 15 06:25:50 AM UTC 24 |
| Finished | Oct 15 06:26:01 AM UTC 24 |
| Peak memory | 260760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968311660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.968311660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_alert_accum.3849320747 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 4566632595 ps |
| CPU time | 228.26 seconds |
| Started | Oct 15 06:25:35 AM UTC 24 |
| Finished | Oct 15 06:29:26 AM UTC 24 |
| Peak memory | 266960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849320747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3849320747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_intr_timeout.1471298026 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 425046549 ps |
| CPU time | 36.34 seconds |
| Started | Oct 15 06:25:32 AM UTC 24 |
| Finished | Oct 15 06:26:10 AM UTC 24 |
| Peak memory | 261084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471298026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1471298026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg.4197307970 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 15712607195 ps |
| CPU time | 1748.51 seconds |
| Started | Oct 15 06:25:43 AM UTC 24 |
| Finished | Oct 15 06:55:12 AM UTC 24 |
| Peak memory | 299820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197307970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.4197307970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg_stub_clk.3050285286 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 155049048633 ps |
| CPU time | 2494.09 seconds |
| Started | Oct 15 06:25:45 AM UTC 24 |
| Finished | Oct 15 07:07:48 AM UTC 24 |
| Peak memory | 299888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050285286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3050285286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/8.alert_handler_ping_timeout.3799980798 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 30229464067 ps |
| CPU time | 466.95 seconds |
| Started | Oct 15 06:25:41 AM UTC 24 |
| Finished | Oct 15 06:33:33 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799980798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3799980798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_alerts.505693470 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 287255946 ps |
| CPU time | 15.17 seconds |
| Started | Oct 15 06:25:18 AM UTC 24 |
| Finished | Oct 15 06:25:35 AM UTC 24 |
| Peak memory | 260792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505693470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.505693470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_classes.2775596712 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 689325858 ps |
| CPU time | 57.44 seconds |
| Started | Oct 15 06:25:19 AM UTC 24 |
| Finished | Oct 15 06:26:18 AM UTC 24 |
| Peak memory | 261020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775596712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2775596712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/8.alert_handler_smoke.2976482484 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 452473418 ps |
| CPU time | 30.27 seconds |
| Started | Oct 15 06:25:03 AM UTC 24 |
| Finished | Oct 15 06:25:35 AM UTC 24 |
| Peak memory | 267172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976482484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2976482484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all.4226983431 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 172078446215 ps |
| CPU time | 2703 seconds |
| Started | Oct 15 06:25:52 AM UTC 24 |
| Finished | Oct 15 07:11:24 AM UTC 24 |
| Peak memory | 293592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226983431 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all.4226983431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/8.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/9.alert_handler_alert_accum_saturation.683501736 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 48747625 ps |
| CPU time | 4.32 seconds |
| Started | Oct 15 06:26:50 AM UTC 24 |
| Finished | Oct 15 06:26:55 AM UTC 24 |
| Peak memory | 261296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683501736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.683501736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy.1863308032 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 61039217364 ps |
| CPU time | 1523.05 seconds |
| Started | Oct 15 06:26:17 AM UTC 24 |
| Finished | Oct 15 06:51:59 AM UTC 24 |
| Peak memory | 299816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863308032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1863308032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy_stress.1142285456 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3323579210 ps |
| CPU time | 51.41 seconds |
| Started | Oct 15 06:26:32 AM UTC 24 |
| Finished | Oct 15 06:27:25 AM UTC 24 |
| Peak memory | 260900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142285456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1142285456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_alert_accum.4162119709 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 9505689235 ps |
| CPU time | 127.52 seconds |
| Started | Oct 15 06:26:10 AM UTC 24 |
| Finished | Oct 15 06:28:20 AM UTC 24 |
| Peak memory | 260952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162119709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4162119709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_intr_timeout.3303729486 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 574186366 ps |
| CPU time | 39.4 seconds |
| Started | Oct 15 06:26:08 AM UTC 24 |
| Finished | Oct 15 06:26:49 AM UTC 24 |
| Peak memory | 260828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303729486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3303729486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg.1500467767 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 37283760766 ps |
| CPU time | 2501.94 seconds |
| Started | Oct 15 06:26:21 AM UTC 24 |
| Finished | Oct 15 07:08:32 AM UTC 24 |
| Peak memory | 297752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500467767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1500467767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg_stub_clk.2531184210 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 38634522550 ps |
| CPU time | 2236.2 seconds |
| Started | Oct 15 06:26:26 AM UTC 24 |
| Finished | Oct 15 07:04:06 AM UTC 24 |
| Peak memory | 299820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531184210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2531184210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/9.alert_handler_ping_timeout.1701859942 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 50253194476 ps |
| CPU time | 505.19 seconds |
| Started | Oct 15 06:26:20 AM UTC 24 |
| Finished | Oct 15 06:34:51 AM UTC 24 |
| Peak memory | 261092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701859942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1701859942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_alerts.2248526794 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2222164964 ps |
| CPU time | 46.06 seconds |
| Started | Oct 15 06:26:02 AM UTC 24 |
| Finished | Oct 15 06:26:50 AM UTC 24 |
| Peak memory | 266964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248526794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2248526794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_classes.2848933068 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 184216121 ps |
| CPU time | 23.63 seconds |
| Started | Oct 15 06:26:05 AM UTC 24 |
| Finished | Oct 15 06:26:30 AM UTC 24 |
| Peak memory | 267168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848933068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2848933068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/9.alert_handler_sig_int_fail.3248763201 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 93507122 ps |
| CPU time | 12.45 seconds |
| Started | Oct 15 06:26:11 AM UTC 24 |
| Finished | Oct 15 06:26:25 AM UTC 24 |
| Peak memory | 267204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248763201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3248763201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/default/9.alert_handler_smoke.3902209024 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 2050936251 ps |
| CPU time | 27.28 seconds |
| Started | Oct 15 06:26:02 AM UTC 24 |
| Finished | Oct 15 06:26:31 AM UTC 24 |
| Peak memory | 266980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902209024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3902209024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/9.alert_handler_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |