Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 332603684 1 T4 15944 T6 48674 T7 1810
auto[1] 413254 1 T7 142 T23 310 T1 968


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 332586582 1 T4 9330 T6 48674 T7 1786
auto[1] 430356 1 T4 6614 T7 166 T5 1654


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 332521586 1 T4 15944 T6 48674 T7 1864
auto[1] 495352 1 T7 88 T5 1654 T22 126


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 308159992 1 T4 15944 T6 48674 T7 60
auto[1] 24856946 1 T7 1892 T22 462 T23 576


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 193682722 1 T4 15944 T6 48674 T7 1922
auto[1] 139334216 1 T7 30 T27 58 T28 24


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 171615846 1 T4 9330 T6 48674 T7 30
auto[0] auto[0] auto[0] auto[0] auto[1] 136188032 1 T7 30 T27 58 T28 24
auto[0] auto[0] auto[0] auto[1] auto[0] 29636 1 T23 12 T1 38 T2 150
auto[0] auto[0] auto[0] auto[1] auto[1] 7214 1 T1 42 T111 20 T112 26
auto[0] auto[0] auto[1] auto[0] auto[0] 21465198 1 T7 1718 T22 54 T23 332
auto[0] auto[0] auto[1] auto[0] auto[1] 3031540 1 T22 268 T1 154 T2 378
auto[0] auto[0] auto[1] auto[1] auto[0] 51980 1 T7 8 T23 36 T1 106
auto[0] auto[0] auto[1] auto[1] auto[1] 12764 1 T1 36 T2 38 T16 30
auto[0] auto[1] auto[0] auto[0] auto[0] 65232 1 T4 6614 T23 2 T2 14
auto[0] auto[1] auto[0] auto[0] auto[1] 1678 1 T23 28 T11 36 T13 38
auto[0] auto[1] auto[0] auto[1] auto[0] 11894 1 T23 62 T11 158 T161 52
auto[0] auto[1] auto[0] auto[1] auto[1] 3734 1 T11 60 T162 74 T163 84
auto[0] auto[1] auto[1] auto[0] auto[0] 9224 1 T7 14 T22 32 T2 34
auto[0] auto[1] auto[1] auto[0] auto[1] 2550 1 T22 36 T1 40 T2 4
auto[0] auto[1] auto[1] auto[1] auto[0] 19524 1 T7 64 T2 92 T9 170
auto[0] auto[1] auto[1] auto[1] auto[1] 5540 1 T1 84 T2 52 T164 128
auto[1] auto[0] auto[0] auto[0] auto[0] 36314 1 T22 28 T2 14 T9 30
auto[1] auto[0] auto[0] auto[0] auto[1] 3506 1 T11 4 T161 28 T165 8
auto[1] auto[0] auto[0] auto[1] auto[0] 33518 1 T2 316 T9 112 T111 62
auto[1] auto[0] auto[0] auto[1] auto[1] 7178 1 T11 104 T165 50 T25 84
auto[1] auto[0] auto[1] auto[0] auto[0] 29674 1 T23 2 T1 54 T2 110
auto[1] auto[0] auto[1] auto[0] auto[1] 6530 1 T22 72 T2 6 T9 2
auto[1] auto[0] auto[1] auto[1] auto[0] 54102 1 T23 56 T1 70 T2 364
auto[1] auto[0] auto[1] auto[1] auto[1] 13550 1 T2 58 T9 52 T112 70
auto[1] auto[1] auto[0] auto[0] auto[0] 90478 1 T5 1654 T22 26 T23 8
auto[1] auto[1] auto[0] auto[0] auto[1] 5652 1 T1 22 T2 24 T111 2
auto[1] auto[1] auto[0] auto[1] auto[0] 48070 1 T1 178 T2 200 T9 150
auto[1] auto[1] auto[0] auto[1] auto[1] 12010 1 T1 70 T2 40 T111 52
auto[1] auto[1] auto[1] auto[0] auto[0] 41108 1 T7 18 T23 6 T1 92
auto[1] auto[1] auto[1] auto[0] auto[1] 11122 1 T2 28 T16 10 T9 12
auto[1] auto[1] auto[1] auto[1] auto[0] 80924 1 T7 70 T23 144 T1 344
auto[1] auto[1] auto[1] auto[1] auto[1] 21616 1 T2 190 T16 72 T9 44

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