Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 327472848 1 T1 224144 T4 4156 T2 948055
auto[1] 437108 1 T2 8288 T3 8488 T15 844


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 327480460 1 T1 224144 T4 4156 T2 948302
auto[1] 429496 1 T2 5816 T3 6770 T15 662


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 327390994 1 T1 224144 T4 4156 T2 947993
auto[1] 518962 1 T2 8902 T3 9868 T15 950


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 306992472 1 T1 224144 T4 4156 T2 945589
auto[1] 20917484 1 T2 32944 T3 230398 T15 3882


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 192597478 1 T1 224076 T4 4138 T2 464151
auto[1] 135312478 1 T1 68 T4 18 T2 484732


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 174148758 1 T1 224076 T4 4138 T2 461296
auto[0] auto[0] auto[0] auto[0] auto[1] 132490164 1 T1 68 T4 18 T2 483945
auto[0] auto[0] auto[0] auto[1] auto[0] 30664 1 T2 380 T3 590 T87 102
auto[0] auto[0] auto[0] auto[1] auto[1] 8820 1 T2 198 T3 132 T87 6
auto[0] auto[0] auto[1] auto[0] auto[0] 17829750 1 T2 18842 T3 229407 T15 2830
auto[0] auto[0] auto[1] auto[0] auto[1] 2699560 1 T2 5420 T3 1170 T25 310
auto[0] auto[0] auto[1] auto[1] auto[0] 56498 1 T2 1528 T3 1060 T15 102
auto[0] auto[0] auto[1] auto[1] auto[1] 14290 1 T2 482 T3 266 T10 292
auto[0] auto[1] auto[0] auto[0] auto[0] 53554 1 T2 72 T3 164 T19 1860
auto[0] auto[1] auto[0] auto[0] auto[1] 1424 1 T2 94 T22 48 T23 92
auto[0] auto[1] auto[0] auto[1] auto[0] 13546 1 T2 66 T3 312 T87 58
auto[0] auto[1] auto[0] auto[1] auto[1] 3206 1 T2 54 T22 116 T23 246
auto[0] auto[1] auto[1] auto[0] auto[0] 11062 1 T2 90 T3 676 T25 38
auto[0] auto[1] auto[1] auto[0] auto[1] 2816 1 T2 8 T3 86 T10 58
auto[0] auto[1] auto[1] auto[1] auto[0] 21526 1 T2 206 T3 410 T10 468
auto[0] auto[1] auto[1] auto[1] auto[1] 5356 1 T2 78 T10 98 T14 128
auto[1] auto[0] auto[0] auto[0] auto[0] 43716 1 T2 408 T3 608 T25 44
auto[1] auto[0] auto[0] auto[0] auto[1] 5328 1 T2 130 T3 126 T87 6
auto[1] auto[0] auto[0] auto[1] auto[0] 33204 1 T2 574 T3 676 T87 178
auto[1] auto[0] auto[0] auto[1] auto[1] 9366 1 T2 200 T3 242 T87 100
auto[1] auto[0] auto[1] auto[0] auto[0] 32322 1 T2 862 T3 1256 T15 44
auto[1] auto[0] auto[1] auto[0] auto[1] 7530 1 T2 142 T3 166 T25 96
auto[1] auto[0] auto[1] auto[1] auto[0] 57564 1 T2 1378 T3 1336 T15 244
auto[1] auto[0] auto[1] auto[1] auto[1] 12926 1 T2 60 T3 336 T10 62
auto[1] auto[1] auto[0] auto[0] auto[0] 81724 1 T2 420 T3 548 T87 94
auto[1] auto[1] auto[0] auto[0] auto[1] 6456 1 T2 142 T3 142 T87 8
auto[1] auto[1] auto[0] auto[1] auto[0] 49938 1 T2 580 T3 1076 T87 220
auto[1] auto[1] auto[0] auto[1] auto[1] 12604 1 T2 158 T3 216 T10 180
auto[1] auto[1] auto[1] auto[0] auto[0] 46546 1 T2 1164 T3 1078 T15 164
auto[1] auto[1] auto[1] auto[0] auto[1] 12138 1 T2 338 T3 226 T87 8
auto[1] auto[1] auto[1] auto[1] auto[0] 87106 1 T2 1986 T3 1670 T15 498
auto[1] auto[1] auto[1] auto[1] auto[1] 20494 1 T2 360 T3 166 T10 606

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