Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

356356492

1

T4

223402

T5

2268

T6

8536

auto[1]

491222

1

T6

808

T26

388

T27

126

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

356378344

1

T4

223402

T5

2268

T6

8430

auto[1]

469370

1

T6

914

T24

290

T26

470

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

356276258

1

T4

223402

T5

2268

T6

8556

auto[1]

571456

1

T6

788

T24

374

T26

432

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

335353082

1

T4

223402

T5

2268

T6

4674

auto[1]

21494632

1

T6

4670

T24

3182

T26

694

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

214314460

1

T4

223402

T5

2248

T6

7350

auto[1]

142533254

1

T5

20

T6

1994

T24

2480

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

197712424

1

T4

223402

T5

2248

T6

2434

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

137251848

1

T5

20

T6

1592

T24

94

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

34836

1

T6

8

T26

2

T27

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8688

1

T6

14

T28

6

T1

64

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

15915864

1

T6

4054

T24

602

T26

288

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5142582

1

T6

100

T24

2296

T26

106

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

63808

1

T6

140

T26

2

T27

14

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

16590

1

T6

8

T1

188

T18

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

63922

1

T6

64

T24

30

T26

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1878

1

T6

26

T133

8

T11

32

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

15034

1

T6

72

T26

48

T1

110

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

4150

1

T133

90

T11

88

T16

58

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

12624

1

T6

6

T24

26

T1

282

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2462

1

T1

50

T11

112

T157

24

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

24152

1

T6

38

T1

482

T18

76

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5396

1

T1

150

T11

88

T83

68

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

58112

1

T24

12

T27

2

T28

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4768

1

T6

28

T1

50

T104

18

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

36424

1

T27

58

T28

54

T1

390

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

10070

1

T1

82

T153

38

T158

54

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

33624

1

T6

52

T24

94

T28

28

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8530

1

T24

34

T26

12

T1

72

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

63320

1

T1

974

T20

80

T3

244

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

16856

1

T1

220

T3

98

T134

76

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

73670

1

T6

82

T24

78

T26

16

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7266

1

T6

28

T24

26

T27

8

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

55436

1

T6

200

T26

118

T28

42

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

14556

1

T6

126

T28

58

T1

84

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

53156

1

T6

60

T24

100

T26

68

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

13762

1

T6

10

T24

30

T28

8

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

98054

1

T6

140

T26

218

T27

42

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

23852

1

T6

62

T1

144

T18

72