Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.01 98.80


Total test records in report: 1009
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T800 /workspace/coverage/default/49.clkmgr_trans.2609310757 Apr 16 02:48:25 PM PDT 24 Apr 16 02:48:27 PM PDT 24 89513270 ps
T801 /workspace/coverage/default/41.clkmgr_alert_test.179293069 Apr 16 02:48:10 PM PDT 24 Apr 16 02:48:12 PM PDT 24 18834266 ps
T802 /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.2670722846 Apr 16 02:47:15 PM PDT 24 Apr 16 02:47:18 PM PDT 24 21496252 ps
T803 /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.735786820 Apr 16 02:46:45 PM PDT 24 Apr 16 02:46:48 PM PDT 24 23947858 ps
T804 /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.758998357 Apr 16 02:47:54 PM PDT 24 Apr 16 02:53:53 PM PDT 24 74627671259 ps
T805 /workspace/coverage/default/43.clkmgr_alert_test.2027221399 Apr 16 02:48:10 PM PDT 24 Apr 16 02:48:12 PM PDT 24 27321042 ps
T806 /workspace/coverage/default/26.clkmgr_alert_test.1533936745 Apr 16 02:47:37 PM PDT 24 Apr 16 02:47:41 PM PDT 24 19799998 ps
T807 /workspace/coverage/default/37.clkmgr_clk_status.3019889463 Apr 16 02:47:54 PM PDT 24 Apr 16 02:47:56 PM PDT 24 12552012 ps
T808 /workspace/coverage/default/21.clkmgr_stress_all.3724355413 Apr 16 02:47:24 PM PDT 24 Apr 16 02:47:41 PM PDT 24 2015142696 ps
T809 /workspace/coverage/default/32.clkmgr_frequency.4076602538 Apr 16 02:47:46 PM PDT 24 Apr 16 02:47:59 PM PDT 24 1516305614 ps
T810 /workspace/coverage/default/9.clkmgr_regwen.3749540251 Apr 16 02:46:56 PM PDT 24 Apr 16 02:47:05 PM PDT 24 1377133330 ps
T811 /workspace/coverage/default/31.clkmgr_frequency_timeout.3686115719 Apr 16 02:47:42 PM PDT 24 Apr 16 02:47:52 PM PDT 24 1463958953 ps
T812 /workspace/coverage/default/14.clkmgr_frequency_timeout.3280457842 Apr 16 02:47:05 PM PDT 24 Apr 16 02:47:09 PM PDT 24 879354875 ps
T813 /workspace/coverage/default/43.clkmgr_clk_status.3774219733 Apr 16 02:48:12 PM PDT 24 Apr 16 02:48:14 PM PDT 24 23793070 ps
T814 /workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.2791752438 Apr 16 02:47:34 PM PDT 24 Apr 16 02:59:07 PM PDT 24 49802936045 ps
T815 /workspace/coverage/default/7.clkmgr_smoke.3894308889 Apr 16 02:46:45 PM PDT 24 Apr 16 02:46:48 PM PDT 24 54593168 ps
T48 /workspace/coverage/default/3.clkmgr_sec_cm.750651324 Apr 16 02:46:39 PM PDT 24 Apr 16 02:46:43 PM PDT 24 159284110 ps
T816 /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.1890279851 Apr 16 02:48:00 PM PDT 24 Apr 16 02:48:02 PM PDT 24 147123203 ps
T817 /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.4200792392 Apr 16 02:46:33 PM PDT 24 Apr 16 02:46:36 PM PDT 24 45635715 ps
T818 /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.1407091006 Apr 16 02:47:43 PM PDT 24 Apr 16 02:47:45 PM PDT 24 38887491 ps
T819 /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.105063418 Apr 16 02:46:35 PM PDT 24 Apr 16 02:46:38 PM PDT 24 26825562 ps
T820 /workspace/coverage/default/29.clkmgr_trans.3127436309 Apr 16 02:47:40 PM PDT 24 Apr 16 02:47:44 PM PDT 24 80103424 ps
T821 /workspace/coverage/default/31.clkmgr_alert_test.630779276 Apr 16 02:47:49 PM PDT 24 Apr 16 02:47:51 PM PDT 24 61944000 ps
T822 /workspace/coverage/default/24.clkmgr_smoke.4049584046 Apr 16 02:47:24 PM PDT 24 Apr 16 02:47:26 PM PDT 24 37713780 ps
T823 /workspace/coverage/default/10.clkmgr_stress_all.3398908221 Apr 16 02:46:57 PM PDT 24 Apr 16 02:47:56 PM PDT 24 8165346186 ps
T824 /workspace/coverage/default/46.clkmgr_smoke.2907219662 Apr 16 02:48:20 PM PDT 24 Apr 16 02:48:22 PM PDT 24 51479764 ps
T825 /workspace/coverage/default/3.clkmgr_frequency.2895308940 Apr 16 02:46:43 PM PDT 24 Apr 16 02:46:55 PM PDT 24 1398565745 ps
T826 /workspace/coverage/default/39.clkmgr_regwen.1622458315 Apr 16 02:48:03 PM PDT 24 Apr 16 02:48:09 PM PDT 24 1078809120 ps
T827 /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.2920715594 Apr 16 02:47:29 PM PDT 24 Apr 16 02:47:31 PM PDT 24 22303738 ps
T828 /workspace/coverage/default/48.clkmgr_trans.2238318027 Apr 16 02:48:28 PM PDT 24 Apr 16 02:48:30 PM PDT 24 42702477 ps
T829 /workspace/coverage/default/2.clkmgr_peri.681355934 Apr 16 02:46:37 PM PDT 24 Apr 16 02:46:39 PM PDT 24 43589158 ps
T830 /workspace/coverage/default/19.clkmgr_clk_status.4279892111 Apr 16 02:47:17 PM PDT 24 Apr 16 02:47:19 PM PDT 24 23652291 ps
T831 /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.2479821673 Apr 16 02:46:58 PM PDT 24 Apr 16 02:47:00 PM PDT 24 14954054 ps
T832 /workspace/coverage/default/40.clkmgr_extclk.4086861782 Apr 16 02:48:03 PM PDT 24 Apr 16 02:48:05 PM PDT 24 32201273 ps
T833 /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.3797842343 Apr 16 02:47:38 PM PDT 24 Apr 16 02:47:43 PM PDT 24 25629836 ps
T834 /workspace/coverage/default/30.clkmgr_trans.1379754300 Apr 16 02:47:45 PM PDT 24 Apr 16 02:47:48 PM PDT 24 36440750 ps
T49 /workspace/coverage/default/1.clkmgr_sec_cm.969358197 Apr 16 02:46:30 PM PDT 24 Apr 16 02:46:34 PM PDT 24 169827146 ps
T835 /workspace/coverage/default/36.clkmgr_regwen.3860392797 Apr 16 02:47:53 PM PDT 24 Apr 16 02:47:57 PM PDT 24 177634684 ps
T836 /workspace/coverage/default/17.clkmgr_clk_status.1126510987 Apr 16 02:47:16 PM PDT 24 Apr 16 02:47:18 PM PDT 24 18181295 ps
T837 /workspace/coverage/default/10.clkmgr_alert_test.2944175941 Apr 16 02:46:53 PM PDT 24 Apr 16 02:46:56 PM PDT 24 94231646 ps
T838 /workspace/coverage/default/30.clkmgr_peri.2707823489 Apr 16 02:47:44 PM PDT 24 Apr 16 02:47:46 PM PDT 24 13407573 ps
T839 /workspace/coverage/default/45.clkmgr_extclk.2772194365 Apr 16 02:48:22 PM PDT 24 Apr 16 02:48:25 PM PDT 24 24043965 ps
T840 /workspace/coverage/default/44.clkmgr_regwen.121501004 Apr 16 02:48:17 PM PDT 24 Apr 16 02:48:22 PM PDT 24 577744045 ps
T841 /workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.716858410 Apr 16 02:47:57 PM PDT 24 Apr 16 02:55:48 PM PDT 24 49819678732 ps
T842 /workspace/coverage/default/24.clkmgr_stress_all.838901741 Apr 16 02:47:33 PM PDT 24 Apr 16 02:47:48 PM PDT 24 3285856690 ps
T843 /workspace/coverage/default/1.clkmgr_clk_status.2120614706 Apr 16 02:46:32 PM PDT 24 Apr 16 02:46:34 PM PDT 24 29428538 ps
T844 /workspace/coverage/default/20.clkmgr_div_intersig_mubi.111165060 Apr 16 02:47:20 PM PDT 24 Apr 16 02:47:22 PM PDT 24 54383479 ps
T845 /workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.656564186 Apr 16 02:47:21 PM PDT 24 Apr 16 02:56:39 PM PDT 24 40552323178 ps
T846 /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.3683786609 Apr 16 02:47:10 PM PDT 24 Apr 16 02:47:11 PM PDT 24 16302902 ps
T847 /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.198334140 Apr 16 02:47:43 PM PDT 24 Apr 16 02:47:45 PM PDT 24 28719518 ps
T848 /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.2048928302 Apr 16 02:48:07 PM PDT 24 Apr 16 02:48:09 PM PDT 24 36520550 ps
T849 /workspace/coverage/default/41.clkmgr_div_intersig_mubi.605764452 Apr 16 02:48:12 PM PDT 24 Apr 16 02:48:14 PM PDT 24 20328797 ps
T850 /workspace/coverage/default/48.clkmgr_smoke.2753611825 Apr 16 02:48:20 PM PDT 24 Apr 16 02:48:22 PM PDT 24 17667272 ps
T851 /workspace/coverage/default/5.clkmgr_trans.251453758 Apr 16 02:46:40 PM PDT 24 Apr 16 02:46:43 PM PDT 24 132612596 ps
T59 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.1218369478 Apr 16 12:49:28 PM PDT 24 Apr 16 12:49:33 PM PDT 24 525440337 ps
T95 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2418068756 Apr 16 12:49:26 PM PDT 24 Apr 16 12:49:30 PM PDT 24 173990280 ps
T852 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.1006505757 Apr 16 12:49:28 PM PDT 24 Apr 16 12:49:31 PM PDT 24 12085546 ps
T76 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3583806510 Apr 16 12:49:26 PM PDT 24 Apr 16 12:49:29 PM PDT 24 38932492 ps
T60 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.3337836709 Apr 16 12:49:19 PM PDT 24 Apr 16 12:49:22 PM PDT 24 209710800 ps
T853 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3233046054 Apr 16 12:49:42 PM PDT 24 Apr 16 12:49:44 PM PDT 24 15180063 ps
T854 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.2291967295 Apr 16 12:49:39 PM PDT 24 Apr 16 12:49:40 PM PDT 24 22911286 ps
T855 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.3741384045 Apr 16 12:49:28 PM PDT 24 Apr 16 12:49:32 PM PDT 24 32298544 ps
T88 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.3122583577 Apr 16 12:49:40 PM PDT 24 Apr 16 12:49:43 PM PDT 24 121409256 ps
T77 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.180037368 Apr 16 12:49:17 PM PDT 24 Apr 16 12:49:19 PM PDT 24 17956285 ps
T856 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.2486883715 Apr 16 12:49:34 PM PDT 24 Apr 16 12:49:36 PM PDT 24 11535403 ps
T857 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3279155592 Apr 16 12:49:10 PM PDT 24 Apr 16 12:49:13 PM PDT 24 134587926 ps
T61 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.913670103 Apr 16 12:49:22 PM PDT 24 Apr 16 12:49:26 PM PDT 24 138480549 ps
T78 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1955773579 Apr 16 12:49:23 PM PDT 24 Apr 16 12:49:28 PM PDT 24 624454261 ps
T62 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.1885964400 Apr 16 12:49:07 PM PDT 24 Apr 16 12:49:11 PM PDT 24 364909183 ps
T858 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.255863952 Apr 16 12:49:39 PM PDT 24 Apr 16 12:49:41 PM PDT 24 44253904 ps
T79 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.1277980229 Apr 16 12:49:31 PM PDT 24 Apr 16 12:49:34 PM PDT 24 21065020 ps
T859 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.1542365661 Apr 16 12:49:37 PM PDT 24 Apr 16 12:49:39 PM PDT 24 31633340 ps
T860 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.704021335 Apr 16 12:49:18 PM PDT 24 Apr 16 12:49:21 PM PDT 24 141731553 ps
T80 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.3998251998 Apr 16 12:49:22 PM PDT 24 Apr 16 12:49:24 PM PDT 24 18738624 ps
T861 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.900426251 Apr 16 12:49:20 PM PDT 24 Apr 16 12:49:22 PM PDT 24 39488908 ps
T89 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.722795065 Apr 16 12:49:20 PM PDT 24 Apr 16 12:49:23 PM PDT 24 57321684 ps
T81 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2555552984 Apr 16 12:49:16 PM PDT 24 Apr 16 12:49:18 PM PDT 24 40061630 ps
T90 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.2586051792 Apr 16 12:49:25 PM PDT 24 Apr 16 12:49:30 PM PDT 24 374799429 ps
T862 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.975011039 Apr 16 12:49:35 PM PDT 24 Apr 16 12:49:37 PM PDT 24 29602247 ps
T863 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.1174160556 Apr 16 12:49:43 PM PDT 24 Apr 16 12:49:45 PM PDT 24 39305857 ps
T864 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.331244197 Apr 16 12:49:35 PM PDT 24 Apr 16 12:49:37 PM PDT 24 58694459 ps
T68 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.3583839763 Apr 16 12:49:20 PM PDT 24 Apr 16 12:49:23 PM PDT 24 136282333 ps
T865 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.601685703 Apr 16 12:49:06 PM PDT 24 Apr 16 12:49:11 PM PDT 24 180169183 ps
T866 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.3621235089 Apr 16 12:49:10 PM PDT 24 Apr 16 12:49:12 PM PDT 24 19953234 ps
T867 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.883308290 Apr 16 12:49:26 PM PDT 24 Apr 16 12:49:30 PM PDT 24 42614527 ps
T868 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.3315739877 Apr 16 12:49:16 PM PDT 24 Apr 16 12:49:21 PM PDT 24 143747461 ps
T869 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.373150174 Apr 16 12:49:27 PM PDT 24 Apr 16 12:49:31 PM PDT 24 20529839 ps
T870 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.1032122473 Apr 16 12:49:25 PM PDT 24 Apr 16 12:49:29 PM PDT 24 112559915 ps
T64 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.836957166 Apr 16 12:49:29 PM PDT 24 Apr 16 12:49:33 PM PDT 24 139603958 ps
T82 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.4234318185 Apr 16 12:49:20 PM PDT 24 Apr 16 12:49:22 PM PDT 24 32675585 ps
T871 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.4276869575 Apr 16 12:49:21 PM PDT 24 Apr 16 12:49:23 PM PDT 24 72992065 ps
T67 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.2857495122 Apr 16 12:49:27 PM PDT 24 Apr 16 12:49:32 PM PDT 24 176543464 ps
T63 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.4028656059 Apr 16 12:49:33 PM PDT 24 Apr 16 12:49:38 PM PDT 24 306751583 ps
T872 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.3418136349 Apr 16 12:49:37 PM PDT 24 Apr 16 12:49:39 PM PDT 24 20866217 ps
T873 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.1811598101 Apr 16 12:49:24 PM PDT 24 Apr 16 12:49:28 PM PDT 24 44049903 ps
T874 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1269390423 Apr 16 12:49:24 PM PDT 24 Apr 16 12:49:28 PM PDT 24 182631866 ps
T66 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.1303968237 Apr 16 12:49:35 PM PDT 24 Apr 16 12:49:38 PM PDT 24 175339734 ps
T875 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.439775884 Apr 16 12:49:37 PM PDT 24 Apr 16 12:49:39 PM PDT 24 16815400 ps
T876 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.2889398617 Apr 16 12:49:21 PM PDT 24 Apr 16 12:49:29 PM PDT 24 677953994 ps
T877 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3859726051 Apr 16 12:49:38 PM PDT 24 Apr 16 12:49:40 PM PDT 24 56926639 ps
T111 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.4008421025 Apr 16 12:49:26 PM PDT 24 Apr 16 12:49:29 PM PDT 24 91606256 ps
T155 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1161372840 Apr 16 12:49:24 PM PDT 24 Apr 16 12:49:29 PM PDT 24 161231943 ps
T878 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2732249417 Apr 16 12:49:29 PM PDT 24 Apr 16 12:49:33 PM PDT 24 218608309 ps
T879 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.1734051750 Apr 16 12:49:29 PM PDT 24 Apr 16 12:49:32 PM PDT 24 55822063 ps
T880 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.1117146036 Apr 16 12:49:29 PM PDT 24 Apr 16 12:49:34 PM PDT 24 89580815 ps
T881 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.807981667 Apr 16 12:49:37 PM PDT 24 Apr 16 12:49:39 PM PDT 24 48686986 ps
T93 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.303861813 Apr 16 12:49:25 PM PDT 24 Apr 16 12:49:30 PM PDT 24 154461450 ps
T882 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.4141112331 Apr 16 12:49:29 PM PDT 24 Apr 16 12:49:32 PM PDT 24 31998736 ps
T65 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.4190708781 Apr 16 12:49:33 PM PDT 24 Apr 16 12:49:36 PM PDT 24 109425050 ps
T883 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.1968484077 Apr 16 12:49:25 PM PDT 24 Apr 16 12:49:28 PM PDT 24 11819131 ps
T884 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.4243257349 Apr 16 12:49:39 PM PDT 24 Apr 16 12:49:42 PM PDT 24 129636756 ps
T99 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.1408583027 Apr 16 12:49:29 PM PDT 24 Apr 16 12:49:33 PM PDT 24 241719217 ps
T115 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.3185033060 Apr 16 12:49:19 PM PDT 24 Apr 16 12:49:22 PM PDT 24 105409242 ps
T885 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1004870307 Apr 16 12:49:25 PM PDT 24 Apr 16 12:49:28 PM PDT 24 14822089 ps
T886 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1236890026 Apr 16 12:49:39 PM PDT 24 Apr 16 12:49:41 PM PDT 24 19024229 ps
T887 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.2653221911 Apr 16 12:49:31 PM PDT 24 Apr 16 12:49:34 PM PDT 24 27586482 ps
T888 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.3092467019 Apr 16 12:49:33 PM PDT 24 Apr 16 12:49:35 PM PDT 24 129352745 ps
T889 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2064802880 Apr 16 12:49:28 PM PDT 24 Apr 16 12:49:31 PM PDT 24 65751833 ps
T890 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.950290682 Apr 16 12:49:37 PM PDT 24 Apr 16 12:49:39 PM PDT 24 28504678 ps
T891 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3987969549 Apr 16 12:49:25 PM PDT 24 Apr 16 12:49:29 PM PDT 24 67945180 ps
T892 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.863139247 Apr 16 12:49:35 PM PDT 24 Apr 16 12:49:37 PM PDT 24 11720656 ps
T893 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.153763070 Apr 16 12:49:22 PM PDT 24 Apr 16 12:49:25 PM PDT 24 31452633 ps
T894 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.767952664 Apr 16 12:49:21 PM PDT 24 Apr 16 12:49:23 PM PDT 24 40883320 ps
T125 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3584425370 Apr 16 12:49:09 PM PDT 24 Apr 16 12:49:13 PM PDT 24 87821303 ps
T895 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.2188071724 Apr 16 12:49:37 PM PDT 24 Apr 16 12:49:38 PM PDT 24 12491611 ps
T896 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.3320975245 Apr 16 12:49:29 PM PDT 24 Apr 16 12:49:31 PM PDT 24 21946385 ps
T897 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.1870259676 Apr 16 12:49:13 PM PDT 24 Apr 16 12:49:14 PM PDT 24 15632747 ps
T898 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.2842958854 Apr 16 12:49:35 PM PDT 24 Apr 16 12:49:37 PM PDT 24 10969949 ps
T123 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.1738525867 Apr 16 12:49:21 PM PDT 24 Apr 16 12:49:26 PM PDT 24 582847086 ps
T98 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.2016850601 Apr 16 12:49:20 PM PDT 24 Apr 16 12:49:24 PM PDT 24 111917272 ps
T899 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.3074628736 Apr 16 12:49:38 PM PDT 24 Apr 16 12:49:40 PM PDT 24 31073540 ps
T112 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3328228829 Apr 16 12:49:14 PM PDT 24 Apr 16 12:49:16 PM PDT 24 67491339 ps
T900 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.825523663 Apr 16 12:49:42 PM PDT 24 Apr 16 12:49:44 PM PDT 24 13856021 ps
T901 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.76760442 Apr 16 12:49:22 PM PDT 24 Apr 16 12:49:26 PM PDT 24 21696005 ps
T902 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2976769072 Apr 16 12:49:24 PM PDT 24 Apr 16 12:49:28 PM PDT 24 40966428 ps
T903 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.2948864379 Apr 16 12:49:34 PM PDT 24 Apr 16 12:49:37 PM PDT 24 55493860 ps
T904 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.172376548 Apr 16 12:49:32 PM PDT 24 Apr 16 12:49:35 PM PDT 24 82020626 ps
T905 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.83519879 Apr 16 12:49:21 PM PDT 24 Apr 16 12:49:23 PM PDT 24 130223153 ps
T906 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.572644361 Apr 16 12:49:08 PM PDT 24 Apr 16 12:49:10 PM PDT 24 36960312 ps
T907 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.3429251536 Apr 16 12:49:29 PM PDT 24 Apr 16 12:49:32 PM PDT 24 17842500 ps
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