Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 306658316 1 T5 11520 T1 539744 T6 2552
auto[1] 409396 1 T1 1534 T15 1028 T2 648


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 306648506 1 T5 11520 T1 539972 T6 2552
auto[1] 419206 1 T1 1306 T15 684 T2 452


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 306590320 1 T5 11520 T1 540042 T6 2552
auto[1] 477392 1 T1 1236 T15 774 T2 482


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 295056186 1 T5 11520 T1 538830 T6 2552
auto[1] 12011526 1 T1 2448 T15 4138 T2 2112


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 180617610 1 T5 11498 T1 533818 T6 2552
auto[1] 126450102 1 T5 22 T1 7460 T15 992


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 171829718 1 T5 11498 T1 531164 T6 2552
auto[0] auto[0] auto[0] auto[0] auto[1] 122894470 1 T5 22 T1 6890 T15 298
auto[0] auto[0] auto[0] auto[1] auto[0] 29450 1 T1 162 T15 30 T19 28
auto[0] auto[0] auto[0] auto[1] auto[1] 8046 1 T15 22 T2 8 T82 32
auto[0] auto[0] auto[1] auto[0] auto[0] 8207084 1 T1 922 T15 3014 T2 1450
auto[0] auto[0] auto[1] auto[0] auto[1] 3435144 1 T1 266 T15 266 T2 228
auto[0] auto[0] auto[1] auto[1] auto[0] 51406 1 T1 150 T15 138 T2 34
auto[0] auto[0] auto[1] auto[1] auto[1] 13654 1 T1 56 T15 52 T2 34
auto[0] auto[1] auto[0] auto[0] auto[0] 65426 1 T1 4 T25 44 T27 940
auto[0] auto[1] auto[0] auto[0] auto[1] 1210 1 T15 8 T83 10 T3 8
auto[0] auto[1] auto[0] auto[1] auto[0] 11968 1 T1 52 T82 56 T136 52
auto[0] auto[1] auto[0] auto[1] auto[1] 3544 1 T15 62 T3 60 T159 64
auto[0] auto[1] auto[1] auto[0] auto[0] 10890 1 T1 112 T15 34 T2 4
auto[0] auto[1] auto[1] auto[0] auto[1] 2988 1 T1 12 T2 4 T24 10
auto[0] auto[1] auto[1] auto[1] auto[0] 18654 1 T1 164 T15 140 T2 106
auto[0] auto[1] auto[1] auto[1] auto[1] 6668 1 T1 88 T2 92 T24 86
auto[1] auto[0] auto[0] auto[0] auto[0] 34790 1 T1 64 T2 46 T19 28
auto[1] auto[0] auto[0] auto[0] auto[1] 4234 1 T15 26 T24 42 T85 30
auto[1] auto[0] auto[0] auto[1] auto[0] 29930 1 T1 122 T2 146 T24 182
auto[1] auto[0] auto[0] auto[1] auto[1] 6780 1 T15 122 T3 138 T159 46
auto[1] auto[0] auto[1] auto[0] auto[0] 29792 1 T1 68 T15 2 T19 28
auto[1] auto[0] auto[1] auto[0] auto[1] 7252 1 T15 46 T2 4 T25 106
auto[1] auto[0] auto[1] auto[1] auto[0] 54268 1 T1 108 T15 62 T19 54
auto[1] auto[0] auto[1] auto[1] auto[1] 12488 1 T15 76 T2 40 T80 48
auto[1] auto[1] auto[0] auto[0] auto[0] 71170 1 T1 92 T15 48 T2 26
auto[1] auto[1] auto[0] auto[0] auto[1] 6968 1 T1 32 T2 2 T19 28
auto[1] auto[1] auto[0] auto[1] auto[0] 45268 1 T1 248 T15 84 T2 62
auto[1] auto[1] auto[0] auto[1] auto[1] 13214 1 T2 40 T82 152 T136 98
auto[1] auto[1] auto[1] auto[0] auto[0] 44982 1 T1 78 T15 54 T2 30
auto[1] auto[1] auto[1] auto[0] auto[1] 12198 1 T1 40 T15 14 T24 26
auto[1] auto[1] auto[1] auto[1] auto[0] 82814 1 T1 308 T15 240 T2 86
auto[1] auto[1] auto[1] auto[1] auto[1] 21244 1 T1 76 T24 72 T78 108

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