SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 22 | 0 | 22 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
io_div2_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_div2_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_div4_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_div4_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
main_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
main_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
shadow_update_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
usb_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
usb_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 18964 | 1 | T5 | 1 | T1 | 67 | T6 | 1 | ||||
auto[1] | 774 | 1 | T1 | 4 | T2 | 3 | T19 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 16024 | 1 | T5 | 1 | T1 | 55 | T6 | 1 | ||||
auto[1] | 3714 | 1 | T1 | 16 | T2 | 13 | T17 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19032 | 1 | T5 | 1 | T1 | 71 | T6 | 1 | ||||
auto[1] | 706 | 1 | T2 | 5 | T19 | 1 | T20 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 16008 | 1 | T5 | 1 | T1 | 51 | T6 | 1 | ||||
auto[1] | 3730 | 1 | T1 | 20 | T2 | 12 | T17 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19008 | 1 | T5 | 1 | T1 | 69 | T6 | 1 | ||||
auto[1] | 730 | 1 | T1 | 2 | T2 | 4 | T20 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 16034 | 1 | T5 | 1 | T1 | 55 | T6 | 1 | ||||
auto[1] | 3704 | 1 | T1 | 16 | T2 | 13 | T17 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19004 | 1 | T5 | 1 | T1 | 67 | T6 | 1 | ||||
auto[1] | 734 | 1 | T1 | 4 | T2 | 3 | T19 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 18815 | 1 | T5 | 1 | T1 | 69 | T6 | 1 | ||||
auto[1] | 923 | 1 | T1 | 2 | T2 | 4 | T17 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19582 | 1 | T5 | 1 | T1 | 71 | T6 | 1 | ||||
auto[1] | 156 | 1 | T48 | 4 | T49 | 6 | T50 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 19062 | 1 | T5 | 1 | T1 | 70 | T6 | 1 | ||||
auto[1] | 676 | 1 | T1 | 1 | T2 | 7 | T19 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 18793 | 1 | T5 | 1 | T1 | 67 | T6 | 1 | ||||
auto[1] | 945 | 1 | T1 | 4 | T2 | 3 | T17 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |