Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 298552758 1 T4 7366 T6 3140 T7 3608
auto[1] 415770 1 T7 90 T1 1086 T17 614


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 298563850 1 T4 7366 T6 3140 T7 3524
auto[1] 404678 1 T7 174 T1 720 T17 372


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 298480376 1 T4 4050 T6 3140 T7 3468
auto[1] 488152 1 T4 3316 T7 230 T1 1214


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 278982228 1 T4 7366 T6 3140 T7 2560
auto[1] 19986300 1 T7 1138 T1 4818 T17 1610


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 170857260 1 T4 7342 T6 2556 T7 3676
auto[1] 128111268 1 T4 24 T6 584 T7 22


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 153654740 1 T4 4026 T6 2556 T7 2414
auto[0] auto[0] auto[0] auto[0] auto[1] 124991692 1 T4 24 T6 584 T7 22
auto[0] auto[0] auto[0] auto[1] auto[0] 30850 1 T7 24 T1 120 T17 72
auto[0] auto[0] auto[0] auto[1] auto[1] 7176 1 T1 10 T18 22 T2 280
auto[0] auto[0] auto[1] auto[0] auto[0] 16615584 1 T7 984 T1 2124 T17 1006
auto[0] auto[0] auto[1] auto[0] auto[1] 3000560 1 T1 1668 T20 1592 T2 2286
auto[0] auto[0] auto[1] auto[1] auto[0] 52212 1 T1 196 T17 100 T20 178
auto[0] auto[0] auto[1] auto[1] auto[1] 14188 1 T1 4 T2 272 T3 532
auto[0] auto[1] auto[0] auto[0] auto[0] 56096 1 T17 8 T18 44 T2 248
auto[0] auto[1] auto[0] auto[0] auto[1] 1288 1 T2 174 T3 28 T10 22
auto[0] auto[1] auto[0] auto[1] auto[0] 12944 1 T2 512 T81 52 T3 316
auto[0] auto[1] auto[0] auto[1] auto[1] 3036 1 T2 358 T3 82 T160 164
auto[0] auto[1] auto[1] auto[0] auto[0] 11698 1 T7 24 T1 26 T17 16
auto[0] auto[1] auto[1] auto[0] auto[1] 2628 1 T1 8 T2 126 T3 32
auto[0] auto[1] auto[1] auto[1] auto[0] 20544 1 T17 44 T2 150 T120 46
auto[0] auto[1] auto[1] auto[1] auto[1] 5140 1 T1 64 T2 92 T3 66
auto[1] auto[0] auto[0] auto[0] auto[0] 48456 1 T4 3316 T7 32 T1 98
auto[1] auto[0] auto[0] auto[0] auto[1] 4060 1 T1 16 T2 16 T81 24
auto[1] auto[0] auto[0] auto[1] auto[0] 31666 1 T18 76 T2 964 T81 82
auto[1] auto[0] auto[0] auto[1] auto[1] 7292 1 T1 62 T2 134 T81 72
auto[1] auto[0] auto[1] auto[0] auto[0] 28698 1 T7 48 T1 194 T17 52
auto[1] auto[0] auto[1] auto[0] auto[1] 8680 1 T2 182 T3 92 T122 16
auto[1] auto[0] auto[1] auto[1] auto[0] 52430 1 T1 222 T17 140 T20 58
auto[1] auto[0] auto[1] auto[1] auto[1] 15566 1 T2 440 T3 338 T10 414
auto[1] auto[1] auto[0] auto[0] auto[0] 64860 1 T7 2 T1 54 T18 130
auto[1] auto[1] auto[0] auto[0] auto[1] 5876 1 T17 2 T18 20 T2 288
auto[1] auto[1] auto[0] auto[1] auto[0] 48652 1 T7 66 T1 256 T18 164
auto[1] auto[1] auto[0] auto[1] auto[1] 13544 1 T17 50 T18 66 T2 282
auto[1] auto[1] auto[1] auto[0] auto[0] 47600 1 T7 82 T1 100 T17 44
auto[1] auto[1] auto[1] auto[0] auto[1] 10242 1 T1 60 T20 32 T2 156
auto[1] auto[1] auto[1] auto[1] auto[0] 80230 1 T1 152 T17 208 T20 152
auto[1] auto[1] auto[1] auto[1] auto[1] 20300 1 T2 382 T3 372 T10 314

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%