SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 22 | 0 | 22 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
io_div2_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_div2_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_div4_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_div4_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
io_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
main_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
main_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
shadow_update_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
usb_measure_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
usb_timeout_cp | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 18200 | 1 | T4 | 1 | T6 | 1 | T7 | 1 | ||||
auto[1] | 725 | 1 | T1 | 3 | T2 | 24 | T3 | 19 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 15455 | 1 | T4 | 1 | T6 | 1 | T7 | 1 | ||||
auto[1] | 3470 | 1 | T1 | 33 | T2 | 60 | T28 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 18157 | 1 | T4 | 1 | T6 | 1 | T7 | 1 | ||||
auto[1] | 768 | 1 | T1 | 6 | T2 | 21 | T3 | 17 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 15544 | 1 | T4 | 1 | T6 | 1 | T7 | 1 | ||||
auto[1] | 3381 | 1 | T1 | 33 | T2 | 57 | T28 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 18205 | 1 | T4 | 1 | T6 | 1 | T7 | 1 | ||||
auto[1] | 720 | 1 | T1 | 2 | T2 | 21 | T3 | 30 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 15454 | 1 | T4 | 1 | T6 | 1 | T7 | 1 | ||||
auto[1] | 3471 | 1 | T1 | 33 | T2 | 60 | T28 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 18245 | 1 | T4 | 1 | T6 | 1 | T7 | 1 | ||||
auto[1] | 680 | 1 | T1 | 2 | T2 | 19 | T3 | 26 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 18043 | 1 | T4 | 1 | T6 | 1 | T7 | 1 | ||||
auto[1] | 882 | 1 | T1 | 5 | T2 | 10 | T28 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 18770 | 1 | T4 | 1 | T6 | 1 | T7 | 1 | ||||
auto[1] | 155 | 1 | T65 | 2 | T62 | 4 | T63 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 18213 | 1 | T4 | 1 | T6 | 1 | T7 | 1 | ||||
auto[1] | 712 | 1 | T1 | 5 | T2 | 22 | T3 | 17 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 18036 | 1 | T4 | 1 | T6 | 1 | T7 | 1 | ||||
auto[1] | 889 | 1 | T1 | 8 | T2 | 9 | T29 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |