Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.01 98.80


Total test records in report: 1010
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T797 /workspace/coverage/default/20.clkmgr_frequency_timeout.3146882055 Apr 21 12:58:02 PM PDT 24 Apr 21 12:58:08 PM PDT 24 616395474 ps
T798 /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.1389629950 Apr 21 12:58:07 PM PDT 24 Apr 21 12:58:08 PM PDT 24 25192536 ps
T799 /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.1592661460 Apr 21 12:58:58 PM PDT 24 Apr 21 12:59:00 PM PDT 24 55436778 ps
T800 /workspace/coverage/default/40.clkmgr_smoke.3523493585 Apr 21 12:58:54 PM PDT 24 Apr 21 12:58:55 PM PDT 24 21933621 ps
T801 /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.877695325 Apr 21 12:57:49 PM PDT 24 Apr 21 12:57:51 PM PDT 24 268266337 ps
T802 /workspace/coverage/default/31.clkmgr_frequency_timeout.1065463082 Apr 21 12:58:32 PM PDT 24 Apr 21 12:58:40 PM PDT 24 2330416161 ps
T9 /workspace/coverage/default/47.clkmgr_regwen.2238952128 Apr 21 12:59:31 PM PDT 24 Apr 21 12:59:35 PM PDT 24 738172027 ps
T803 /workspace/coverage/default/8.clkmgr_extclk.3893447077 Apr 21 12:57:43 PM PDT 24 Apr 21 12:57:44 PM PDT 24 42290787 ps
T804 /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.1938788028 Apr 21 12:57:27 PM PDT 24 Apr 21 12:57:28 PM PDT 24 44408352 ps
T805 /workspace/coverage/default/45.clkmgr_smoke.1892430641 Apr 21 12:59:06 PM PDT 24 Apr 21 12:59:07 PM PDT 24 75159173 ps
T806 /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.4225257055 Apr 21 12:58:40 PM PDT 24 Apr 21 12:58:41 PM PDT 24 41727691 ps
T807 /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.1350117365 Apr 21 12:59:22 PM PDT 24 Apr 21 12:59:23 PM PDT 24 26018379 ps
T808 /workspace/coverage/default/8.clkmgr_stress_all_with_rand_reset.825581674 Apr 21 12:57:53 PM PDT 24 Apr 21 01:06:55 PM PDT 24 85530953617 ps
T809 /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.3987943897 Apr 21 12:57:40 PM PDT 24 Apr 21 12:57:42 PM PDT 24 41123518 ps
T810 /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.1339184550 Apr 21 12:59:06 PM PDT 24 Apr 21 12:59:07 PM PDT 24 18335490 ps
T811 /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.541149409 Apr 21 12:59:07 PM PDT 24 Apr 21 12:59:08 PM PDT 24 15967143 ps
T812 /workspace/coverage/default/11.clkmgr_trans.2897632465 Apr 21 12:57:48 PM PDT 24 Apr 21 12:57:49 PM PDT 24 15903746 ps
T813 /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.1871778558 Apr 21 12:58:03 PM PDT 24 Apr 21 12:58:05 PM PDT 24 46921715 ps
T814 /workspace/coverage/default/47.clkmgr_clk_status.1456717847 Apr 21 12:59:08 PM PDT 24 Apr 21 12:59:09 PM PDT 24 41883797 ps
T815 /workspace/coverage/default/7.clkmgr_clk_status.392462315 Apr 21 12:57:55 PM PDT 24 Apr 21 12:57:56 PM PDT 24 18372000 ps
T816 /workspace/coverage/default/39.clkmgr_regwen.2363551348 Apr 21 12:59:01 PM PDT 24 Apr 21 12:59:04 PM PDT 24 232975911 ps
T817 /workspace/coverage/default/19.clkmgr_peri.359878118 Apr 21 12:58:05 PM PDT 24 Apr 21 12:58:07 PM PDT 24 50256864 ps
T818 /workspace/coverage/default/5.clkmgr_stress_all.1199858253 Apr 21 12:57:33 PM PDT 24 Apr 21 12:58:51 PM PDT 24 11051911960 ps
T819 /workspace/coverage/default/39.clkmgr_smoke.2117403331 Apr 21 12:59:00 PM PDT 24 Apr 21 12:59:01 PM PDT 24 47409667 ps
T820 /workspace/coverage/default/12.clkmgr_stress_all.225469523 Apr 21 12:57:54 PM PDT 24 Apr 21 12:58:04 PM PDT 24 1045558532 ps
T821 /workspace/coverage/default/37.clkmgr_extclk.1306743584 Apr 21 12:58:44 PM PDT 24 Apr 21 12:58:45 PM PDT 24 52026752 ps
T822 /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.3820775325 Apr 21 12:58:57 PM PDT 24 Apr 21 12:58:59 PM PDT 24 18986378 ps
T823 /workspace/coverage/default/17.clkmgr_stress_all.2296399617 Apr 21 12:57:59 PM PDT 24 Apr 21 12:58:32 PM PDT 24 10660855654 ps
T824 /workspace/coverage/default/20.clkmgr_div_intersig_mubi.300526604 Apr 21 12:58:04 PM PDT 24 Apr 21 12:58:06 PM PDT 24 25458736 ps
T825 /workspace/coverage/default/26.clkmgr_extclk.2846270075 Apr 21 12:58:31 PM PDT 24 Apr 21 12:58:33 PM PDT 24 44327167 ps
T826 /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.1353100208 Apr 21 12:58:32 PM PDT 24 Apr 21 12:58:34 PM PDT 24 24567216 ps
T827 /workspace/coverage/default/45.clkmgr_frequency.1466177821 Apr 21 12:59:06 PM PDT 24 Apr 21 12:59:09 PM PDT 24 320900183 ps
T828 /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.944738898 Apr 21 12:58:05 PM PDT 24 Apr 21 12:58:07 PM PDT 24 66287803 ps
T829 /workspace/coverage/default/4.clkmgr_extclk.2341354793 Apr 21 12:57:28 PM PDT 24 Apr 21 12:57:31 PM PDT 24 47477132 ps
T830 /workspace/coverage/default/21.clkmgr_div_intersig_mubi.1060187158 Apr 21 12:58:14 PM PDT 24 Apr 21 12:58:16 PM PDT 24 47938226 ps
T831 /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.2596452148 Apr 21 12:59:04 PM PDT 24 Apr 21 12:59:05 PM PDT 24 58350038 ps
T832 /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.2509430487 Apr 21 12:59:26 PM PDT 24 Apr 21 12:59:27 PM PDT 24 28734958 ps
T833 /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.3712113816 Apr 21 12:58:02 PM PDT 24 Apr 21 12:58:04 PM PDT 24 23791473 ps
T834 /workspace/coverage/default/7.clkmgr_extclk.2201269289 Apr 21 12:57:43 PM PDT 24 Apr 21 12:57:44 PM PDT 24 14483309 ps
T835 /workspace/coverage/default/2.clkmgr_regwen.2882019949 Apr 21 12:57:25 PM PDT 24 Apr 21 12:57:30 PM PDT 24 796101684 ps
T836 /workspace/coverage/default/13.clkmgr_stress_all.879047294 Apr 21 12:58:07 PM PDT 24 Apr 21 12:58:18 PM PDT 24 3085068445 ps
T837 /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.2432786063 Apr 21 12:58:05 PM PDT 24 Apr 21 12:58:07 PM PDT 24 26217796 ps
T838 /workspace/coverage/default/13.clkmgr_extclk.794658854 Apr 21 12:57:49 PM PDT 24 Apr 21 12:57:50 PM PDT 24 75276218 ps
T839 /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.2895984950 Apr 21 12:58:37 PM PDT 24 Apr 21 12:58:39 PM PDT 24 61689124 ps
T840 /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.763357400 Apr 21 12:58:43 PM PDT 24 Apr 21 12:58:44 PM PDT 24 60672935 ps
T841 /workspace/coverage/default/4.clkmgr_frequency.3469480370 Apr 21 12:57:29 PM PDT 24 Apr 21 12:57:39 PM PDT 24 1650112062 ps
T842 /workspace/coverage/default/17.clkmgr_trans.3178470000 Apr 21 12:57:59 PM PDT 24 Apr 21 12:58:00 PM PDT 24 117822174 ps
T843 /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.4069712152 Apr 21 12:58:41 PM PDT 24 Apr 21 12:58:43 PM PDT 24 61769758 ps
T844 /workspace/coverage/default/42.clkmgr_peri.2378510503 Apr 21 12:59:23 PM PDT 24 Apr 21 12:59:24 PM PDT 24 38858273 ps
T845 /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.4122621823 Apr 21 12:59:01 PM PDT 24 Apr 21 12:59:02 PM PDT 24 21187550 ps
T846 /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.364376160 Apr 21 12:58:21 PM PDT 24 Apr 21 12:58:22 PM PDT 24 20152635 ps
T847 /workspace/coverage/default/17.clkmgr_frequency_timeout.1748821360 Apr 21 12:57:59 PM PDT 24 Apr 21 12:58:03 PM PDT 24 903472545 ps
T848 /workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.586926518 Apr 21 12:58:09 PM PDT 24 Apr 21 01:03:38 PM PDT 24 47842035521 ps
T849 /workspace/coverage/default/21.clkmgr_extclk.4053780357 Apr 21 12:58:24 PM PDT 24 Apr 21 12:58:25 PM PDT 24 18508929 ps
T850 /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.880835878 Apr 21 12:57:31 PM PDT 24 Apr 21 12:57:32 PM PDT 24 24292193 ps
T65 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2635812090 Apr 21 12:41:39 PM PDT 24 Apr 21 12:41:42 PM PDT 24 99141709 ps
T89 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.84573566 Apr 21 12:42:00 PM PDT 24 Apr 21 12:42:02 PM PDT 24 15286829 ps
T90 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.193641346 Apr 21 12:41:48 PM PDT 24 Apr 21 12:41:49 PM PDT 24 64902305 ps
T91 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.1585495375 Apr 21 12:41:42 PM PDT 24 Apr 21 12:41:43 PM PDT 24 36893274 ps
T851 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.3036094978 Apr 21 12:41:58 PM PDT 24 Apr 21 12:42:05 PM PDT 24 1406479653 ps
T852 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1472422642 Apr 21 12:41:49 PM PDT 24 Apr 21 12:41:51 PM PDT 24 22448015 ps
T853 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.802027547 Apr 21 12:42:08 PM PDT 24 Apr 21 12:42:09 PM PDT 24 44686502 ps
T146 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.2138472783 Apr 21 12:41:44 PM PDT 24 Apr 21 12:41:45 PM PDT 24 17368493 ps
T854 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.2027273665 Apr 21 12:42:08 PM PDT 24 Apr 21 12:42:09 PM PDT 24 30688649 ps
T855 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.816382828 Apr 21 12:41:55 PM PDT 24 Apr 21 12:41:57 PM PDT 24 52114719 ps
T856 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.981089800 Apr 21 12:41:38 PM PDT 24 Apr 21 12:41:40 PM PDT 24 74696882 ps
T62 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.698220615 Apr 21 12:41:48 PM PDT 24 Apr 21 12:41:50 PM PDT 24 81083234 ps
T63 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.2421024173 Apr 21 12:42:22 PM PDT 24 Apr 21 12:42:31 PM PDT 24 177438085 ps
T857 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.2834528823 Apr 21 12:42:03 PM PDT 24 Apr 21 12:42:05 PM PDT 24 43382093 ps
T858 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.1715712102 Apr 21 12:41:47 PM PDT 24 Apr 21 12:41:48 PM PDT 24 29827312 ps
T64 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.716360622 Apr 21 12:41:41 PM PDT 24 Apr 21 12:41:43 PM PDT 24 177920489 ps
T859 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.2921598451 Apr 21 12:42:11 PM PDT 24 Apr 21 12:42:12 PM PDT 24 15711308 ps
T860 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.4083077962 Apr 21 12:42:22 PM PDT 24 Apr 21 12:42:23 PM PDT 24 13135008 ps
T861 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.1855573804 Apr 21 12:42:00 PM PDT 24 Apr 21 12:42:02 PM PDT 24 38832293 ps
T69 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.3967510599 Apr 21 12:42:07 PM PDT 24 Apr 21 12:42:11 PM PDT 24 149233964 ps
T862 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.1465619363 Apr 21 12:42:09 PM PDT 24 Apr 21 12:42:10 PM PDT 24 15262461 ps
T863 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.3299526612 Apr 21 12:42:04 PM PDT 24 Apr 21 12:42:05 PM PDT 24 23710738 ps
T70 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3740901555 Apr 21 12:41:41 PM PDT 24 Apr 21 12:41:44 PM PDT 24 352673375 ps
T92 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1463062156 Apr 21 12:41:54 PM PDT 24 Apr 21 12:41:56 PM PDT 24 36861200 ps
T108 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.4240873161 Apr 21 12:42:02 PM PDT 24 Apr 21 12:42:05 PM PDT 24 100905654 ps
T864 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.3648508952 Apr 21 12:42:06 PM PDT 24 Apr 21 12:42:07 PM PDT 24 14646584 ps
T865 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.3502011196 Apr 21 12:41:47 PM PDT 24 Apr 21 12:41:48 PM PDT 24 33894376 ps
T71 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3506279083 Apr 21 12:42:09 PM PDT 24 Apr 21 12:42:11 PM PDT 24 245673514 ps
T66 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.1033357359 Apr 21 12:42:14 PM PDT 24 Apr 21 12:42:16 PM PDT 24 123506423 ps
T866 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.1090325835 Apr 21 12:41:52 PM PDT 24 Apr 21 12:41:56 PM PDT 24 388906530 ps
T867 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2174590580 Apr 21 12:41:41 PM PDT 24 Apr 21 12:41:42 PM PDT 24 129857870 ps
T868 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.1802425965 Apr 21 12:42:12 PM PDT 24 Apr 21 12:42:14 PM PDT 24 23855538 ps
T93 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.1638292821 Apr 21 12:41:47 PM PDT 24 Apr 21 12:41:48 PM PDT 24 32085089 ps
T94 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.986606021 Apr 21 12:42:19 PM PDT 24 Apr 21 12:42:20 PM PDT 24 95264618 ps
T132 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.811044899 Apr 21 12:41:56 PM PDT 24 Apr 21 12:41:59 PM PDT 24 95636978 ps
T136 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.1443925964 Apr 21 12:42:07 PM PDT 24 Apr 21 12:42:10 PM PDT 24 204796933 ps
T68 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.1710400751 Apr 21 12:41:45 PM PDT 24 Apr 21 12:41:48 PM PDT 24 271506251 ps
T869 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.667328248 Apr 21 12:42:07 PM PDT 24 Apr 21 12:42:08 PM PDT 24 28971893 ps
T870 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.1903009092 Apr 21 12:42:12 PM PDT 24 Apr 21 12:42:13 PM PDT 24 17250441 ps
T109 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2772623435 Apr 21 12:41:52 PM PDT 24 Apr 21 12:41:54 PM PDT 24 53176876 ps
T871 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.2622884943 Apr 21 12:42:00 PM PDT 24 Apr 21 12:42:01 PM PDT 24 75259592 ps
T872 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.3647538250 Apr 21 12:42:03 PM PDT 24 Apr 21 12:42:04 PM PDT 24 74887723 ps
T873 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1430785378 Apr 21 12:41:58 PM PDT 24 Apr 21 12:41:59 PM PDT 24 119101359 ps
T874 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.3550563703 Apr 21 12:41:40 PM PDT 24 Apr 21 12:41:43 PM PDT 24 93790184 ps
T875 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1165141602 Apr 21 12:41:56 PM PDT 24 Apr 21 12:41:59 PM PDT 24 87735127 ps
T876 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.2883406784 Apr 21 12:41:51 PM PDT 24 Apr 21 12:41:52 PM PDT 24 26878176 ps
T877 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.992706481 Apr 21 12:42:09 PM PDT 24 Apr 21 12:42:11 PM PDT 24 11621212 ps
T878 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.1056217080 Apr 21 12:41:57 PM PDT 24 Apr 21 12:41:59 PM PDT 24 17286453 ps
T879 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.896694026 Apr 21 12:42:24 PM PDT 24 Apr 21 12:42:25 PM PDT 24 15871197 ps
T72 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3036488415 Apr 21 12:42:16 PM PDT 24 Apr 21 12:42:19 PM PDT 24 210273393 ps
T880 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.1390522952 Apr 21 12:42:11 PM PDT 24 Apr 21 12:42:12 PM PDT 24 13211583 ps
T881 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.3398085537 Apr 21 12:42:13 PM PDT 24 Apr 21 12:42:14 PM PDT 24 103093487 ps
T882 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.2727166990 Apr 21 12:41:56 PM PDT 24 Apr 21 12:41:59 PM PDT 24 19250675 ps
T110 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1141639915 Apr 21 12:41:41 PM PDT 24 Apr 21 12:41:44 PM PDT 24 351535580 ps
T883 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.753297506 Apr 21 12:42:05 PM PDT 24 Apr 21 12:42:07 PM PDT 24 118285026 ps
T884 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.1877808112 Apr 21 12:41:52 PM PDT 24 Apr 21 12:41:53 PM PDT 24 17962160 ps
T885 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.4067875390 Apr 21 12:41:58 PM PDT 24 Apr 21 12:42:02 PM PDT 24 136078654 ps
T886 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2666597246 Apr 21 12:42:11 PM PDT 24 Apr 21 12:42:13 PM PDT 24 121256421 ps
T887 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.283350440 Apr 21 12:42:00 PM PDT 24 Apr 21 12:42:03 PM PDT 24 21795194 ps
T888 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.2316126447 Apr 21 12:41:58 PM PDT 24 Apr 21 12:42:00 PM PDT 24 35865522 ps
T889 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.2734656369 Apr 21 12:42:00 PM PDT 24 Apr 21 12:42:02 PM PDT 24 45774122 ps
T890 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.2378311768 Apr 21 12:41:50 PM PDT 24 Apr 21 12:41:51 PM PDT 24 59128618 ps
T891 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.3854371690 Apr 21 12:41:58 PM PDT 24 Apr 21 12:42:01 PM PDT 24 83520438 ps
T892 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.799833853 Apr 21 12:42:00 PM PDT 24 Apr 21 12:42:02 PM PDT 24 31692334 ps
T67 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1296926415 Apr 21 12:42:07 PM PDT 24 Apr 21 12:42:09 PM PDT 24 156248348 ps
T893 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.1686246074 Apr 21 12:41:39 PM PDT 24 Apr 21 12:41:44 PM PDT 24 346373559 ps
T894 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2606306175 Apr 21 12:41:39 PM PDT 24 Apr 21 12:41:41 PM PDT 24 14772084 ps
T895 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.3428633747 Apr 21 12:41:52 PM PDT 24 Apr 21 12:41:54 PM PDT 24 52414019 ps
T896 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.3957977038 Apr 21 12:42:04 PM PDT 24 Apr 21 12:42:06 PM PDT 24 11918370 ps
T897 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.2042208537 Apr 21 12:42:04 PM PDT 24 Apr 21 12:42:05 PM PDT 24 13824569 ps
T898 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.2168023486 Apr 21 12:42:02 PM PDT 24 Apr 21 12:42:04 PM PDT 24 14238576 ps
T899 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.269918337 Apr 21 12:41:56 PM PDT 24 Apr 21 12:42:04 PM PDT 24 13125326 ps
T115 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.502815306 Apr 21 12:41:37 PM PDT 24 Apr 21 12:41:40 PM PDT 24 198918981 ps
T900 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1747136245 Apr 21 12:41:39 PM PDT 24 Apr 21 12:41:40 PM PDT 24 81093641 ps
T901 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3235867358 Apr 21 12:42:15 PM PDT 24 Apr 21 12:42:15 PM PDT 24 26780914 ps
T902 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2367579698 Apr 21 12:41:55 PM PDT 24 Apr 21 12:41:57 PM PDT 24 71723894 ps
T903 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.4009481761 Apr 21 12:41:52 PM PDT 24 Apr 21 12:41:53 PM PDT 24 13449847 ps
T116 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.1012775796 Apr 21 12:42:03 PM PDT 24 Apr 21 12:42:07 PM PDT 24 358715486 ps
T904 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.3014462580 Apr 21 12:41:33 PM PDT 24 Apr 21 12:41:35 PM PDT 24 30321119 ps
T905 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.3894139221 Apr 21 12:41:43 PM PDT 24 Apr 21 12:41:45 PM PDT 24 97520017 ps
T906 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.385550883 Apr 21 12:41:54 PM PDT 24 Apr 21 12:41:55 PM PDT 24 12249401 ps
T907 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.118262149 Apr 21 12:42:02 PM PDT 24 Apr 21 12:42:04 PM PDT 24 38887313 ps
T908 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.2265118923 Apr 21 12:42:16 PM PDT 24 Apr 21 12:42:17 PM PDT 24 12753988 ps
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