Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 334483620 1 T7 2350 T8 6716 T9 3838
auto[1] 434400 1 T27 78 T28 1030 T29 1110


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 334500084 1 T7 2178 T8 6716 T9 3838
auto[1] 417936 1 T7 172 T27 588 T28 660


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 334401036 1 T7 2208 T8 6716 T9 3838
auto[1] 516984 1 T7 142 T27 622 T28 746


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 309167886 1 T7 592 T8 6716 T9 3838
auto[1] 25750134 1 T7 1758 T27 3776 T28 416


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 188420948 1 T7 2100 T8 3102 T9 2978
auto[1] 146497072 1 T7 250 T8 3614 T9 860


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 167124722 1 T7 470 T8 3102 T9 2978
auto[0] auto[0] auto[0] auto[0] auto[1] 141697706 1 T8 3614 T9 860 T27 28
auto[0] auto[0] auto[0] auto[1] auto[0] 31566 1 T28 396 T29 156 T30 16
auto[0] auto[0] auto[0] auto[1] auto[1] 7730 1 T28 56 T29 68 T40 26
auto[0] auto[0] auto[1] auto[0] auto[0] 20691024 1 T7 1480 T27 2906 T28 224
auto[0] auto[0] auto[1] auto[0] auto[1] 4678072 1 T7 198 T27 438 T30 88
auto[0] auto[0] auto[1] auto[1] auto[0] 55484 1 T28 28 T31 116 T23 58
auto[0] auto[0] auto[1] auto[1] auto[1] 13000 1 T27 18 T31 64 T40 52
auto[0] auto[1] auto[0] auto[0] auto[0] 42402 1 T7 32 T27 116 T28 20
auto[0] auto[1] auto[0] auto[0] auto[1] 1348 1 T29 48 T22 32 T23 8
auto[0] auto[1] auto[0] auto[1] auto[0] 13160 1 T31 76 T40 48 T22 106
auto[0] auto[1] auto[0] auto[1] auto[1] 3502 1 T29 88 T22 58 T23 58
auto[0] auto[1] auto[1] auto[0] auto[0] 10978 1 T7 28 T28 16 T30 24
auto[0] auto[1] auto[1] auto[0] auto[1] 2782 1 T2 96 T44 2 T45 4
auto[0] auto[1] auto[1] auto[1] auto[0] 21578 1 T28 48 T2 348 T115 120
auto[0] auto[1] auto[1] auto[1] auto[1] 5982 1 T2 84 T44 60 T45 98
auto[1] auto[0] auto[0] auto[0] auto[0] 44770 1 T7 30 T27 82 T28 44
auto[1] auto[0] auto[0] auto[0] auto[1] 4516 1 T29 8 T20 116 T22 56
auto[1] auto[0] auto[0] auto[1] auto[0] 33702 1 T28 60 T29 204 T31 76
auto[1] auto[0] auto[0] auto[1] auto[1] 8724 1 T29 70 T20 62 T22 144
auto[1] auto[0] auto[1] auto[0] auto[0] 30516 1 T28 6 T29 50 T30 34
auto[1] auto[0] auto[1] auto[0] auto[1] 8088 1 T27 68 T30 8 T2 154
auto[1] auto[0] auto[1] auto[1] auto[0] 56442 1 T28 60 T31 176 T23 216
auto[1] auto[0] auto[1] auto[1] auto[1] 14022 1 T2 286 T115 40 T176 82
auto[1] auto[1] auto[0] auto[0] auto[0] 82386 1 T7 60 T27 126 T28 160
auto[1] auto[1] auto[0] auto[0] auto[1] 6878 1 T29 2 T40 38 T20 14
auto[1] auto[1] auto[0] auto[1] auto[0] 51850 1 T28 382 T29 434 T30 50
auto[1] auto[1] auto[0] auto[1] auto[1] 12924 1 T29 90 T40 100 T20 74
auto[1] auto[1] auto[1] auto[0] auto[0] 45576 1 T27 236 T28 34 T30 52
auto[1] auto[1] auto[1] auto[0] auto[1] 11856 1 T7 52 T27 50 T20 16
auto[1] auto[1] auto[1] auto[1] auto[0] 84792 1 T30 42 T23 232 T2 1018
auto[1] auto[1] auto[1] auto[1] auto[1] 19942 1 T27 60 T20 98 T23 42

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