Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 334865246 1 T4 289162 T5 2846 T6 3150
auto[1] 444244 1 T5 454 T6 44 T22 172


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 334895660 1 T4 289162 T5 2894 T6 2938
auto[1] 413830 1 T5 406 T6 256 T25 162


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 334807974 1 T4 289162 T5 2920 T6 2824
auto[1] 501516 1 T5 380 T6 370 T22 150


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 318510438 1 T4 289162 T5 410 T6 578
auto[1] 16799052 1 T5 2890 T6 2616 T22 1636


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 192160234 1 T4 289138 T5 2922 T6 3052
auto[1] 143149256 1 T4 24 T5 378 T6 142


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 181143382 1 T4 289138 T5 330 T6 348
auto[0] auto[0] auto[0] auto[0] auto[1] 137030126 1 T4 24 T6 94 T21 1596
auto[0] auto[0] auto[0] auto[1] auto[0] 33546 1 T5 4 T25 48 T1 76
auto[0] auto[0] auto[0] auto[1] auto[1] 8294 1 T1 8 T2 140 T18 6
auto[0] auto[0] auto[1] auto[0] auto[0] 10420428 1 T5 2186 T6 2358 T22 1436
auto[0] auto[0] auto[1] auto[0] auto[1] 5991614 1 T5 224 T1 358 T2 9900
auto[0] auto[0] auto[1] auto[1] auto[0] 54676 1 T5 50 T22 50 T25 22
auto[0] auto[0] auto[1] auto[1] auto[1] 15168 1 T5 12 T1 86 T2 548
auto[0] auto[1] auto[0] auto[0] auto[0] 52454 1 T5 8 T6 24 T2 120
auto[0] auto[1] auto[0] auto[0] auto[1] 1728 1 T2 72 T10 28 T154 8
auto[0] auto[1] auto[0] auto[1] auto[0] 13020 1 T2 264 T20 52 T12 174
auto[0] auto[1] auto[0] auto[1] auto[1] 3748 1 T2 210 T12 46 T184 44
auto[0] auto[1] auto[1] auto[0] auto[0] 11146 1 T5 18 T1 22 T2 246
auto[0] auto[1] auto[1] auto[0] auto[1] 2818 1 T2 34 T9 8 T10 4
auto[0] auto[1] auto[1] auto[1] auto[0] 20212 1 T5 88 T1 134 T2 792
auto[0] auto[1] auto[1] auto[1] auto[1] 5614 1 T2 226 T9 70 T10 56
auto[1] auto[0] auto[0] auto[0] auto[0] 44000 1 T5 8 T25 34 T1 24
auto[1] auto[0] auto[0] auto[0] auto[1] 4032 1 T1 10 T2 48 T18 2
auto[1] auto[0] auto[0] auto[1] auto[0] 32136 1 T25 42 T1 52 T2 478
auto[1] auto[0] auto[0] auto[1] auto[1] 7138 1 T1 66 T18 58 T9 54
auto[1] auto[0] auto[1] auto[0] auto[0] 31668 1 T5 2 T6 94 T22 28
auto[1] auto[0] auto[1] auto[0] auto[1] 7324 1 T5 30 T1 8 T2 154
auto[1] auto[0] auto[1] auto[1] auto[0] 58634 1 T5 48 T6 44 T22 122
auto[1] auto[0] auto[1] auto[1] auto[1] 13494 1 T2 478 T9 84 T10 174
auto[1] auto[1] auto[0] auto[0] auto[0] 59136 1 T5 16 T6 64 T25 18
auto[1] auto[1] auto[0] auto[0] auto[1] 7268 1 T6 48 T1 30 T2 214
auto[1] auto[1] auto[0] auto[1] auto[0] 55594 1 T5 44 T25 68 T1 272
auto[1] auto[1] auto[0] auto[1] auto[1] 14836 1 T1 48 T2 126 T10 38
auto[1] auto[1] auto[1] auto[0] auto[0] 45442 1 T5 12 T6 120 T25 6
auto[1] auto[1] auto[1] auto[0] auto[1] 12680 1 T5 12 T1 26 T2 210
auto[1] auto[1] auto[1] auto[1] auto[0] 84760 1 T5 108 T25 70 T1 502
auto[1] auto[1] auto[1] auto[1] auto[1] 23374 1 T5 100 T1 108 T2 542

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