Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 322047012 1 T7 3818 T8 1978 T9 1220
auto[1] 421702 1 T7 990 T8 90 T9 74


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 322053746 1 T7 3964 T8 1996 T9 1294
auto[1] 414968 1 T7 844 T8 72 T1 5210


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 321990670 1 T7 3682 T8 1906 T9 1226
auto[1] 478044 1 T7 1126 T8 162 T9 68


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 299658670 1 T7 906 T8 66 T9 1294
auto[1] 22810044 1 T7 3902 T8 2002 T1 32320


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 193000482 1 T7 4360 T8 2068 T9 1294
auto[1] 129468232 1 T7 448 T4 20 T26 1008


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 174023726 1 T7 436 T8 66 T9 1218
auto[0] auto[0] auto[0] auto[0] auto[1] 125290978 1 T7 96 T4 20 T26 1008
auto[0] auto[0] auto[0] auto[1] auto[0] 31770 1 T7 16 T9 8 T1 572
auto[0] auto[0] auto[0] auto[1] auto[1] 6676 1 T1 56 T20 10 T21 26
auto[0] auto[0] auto[1] auto[0] auto[0] 18365744 1 T7 2552 T8 1824 T1 15768
auto[0] auto[0] auto[1] auto[0] auto[1] 4063650 1 T7 196 T1 9846 T3 6258
auto[0] auto[0] auto[1] auto[1] auto[0] 56544 1 T7 176 T8 16 T1 906
auto[0] auto[0] auto[1] auto[1] auto[1] 13468 1 T7 6 T1 366 T3 184
auto[0] auto[1] auto[0] auto[0] auto[0] 81328 1 T7 20 T1 24 T21 22
auto[0] auto[1] auto[0] auto[0] auto[1] 1492 1 T1 8 T20 10 T39 2
auto[0] auto[1] auto[0] auto[1] auto[0] 12796 1 T1 176 T21 116 T99 46
auto[0] auto[1] auto[0] auto[1] auto[1] 2444 1 T20 58 T39 58 T99 64
auto[0] auto[1] auto[1] auto[0] auto[0] 11848 1 T7 52 T1 82 T20 4
auto[0] auto[1] auto[1] auto[0] auto[1] 2494 1 T7 46 T1 20 T62 2
auto[0] auto[1] auto[1] auto[1] auto[0] 21112 1 T7 86 T1 410 T20 86
auto[0] auto[1] auto[1] auto[1] auto[1] 4600 1 T1 52 T62 64 T99 50
auto[1] auto[0] auto[0] auto[0] auto[0] 41618 1 T7 18 T9 2 T1 170
auto[1] auto[0] auto[0] auto[0] auto[1] 3780 1 T21 8 T3 102 T76 2
auto[1] auto[0] auto[0] auto[1] auto[0] 36414 1 T7 70 T9 66 T1 680
auto[1] auto[0] auto[0] auto[1] auto[1] 7770 1 T76 56 T14 48 T18 156
auto[1] auto[0] auto[1] auto[0] auto[0] 32044 1 T7 52 T8 16 T1 354
auto[1] auto[0] auto[1] auto[0] auto[1] 7372 1 T7 14 T1 122 T3 198
auto[1] auto[0] auto[1] auto[1] auto[0] 57914 1 T7 272 T8 74 T1 1196
auto[1] auto[0] auto[1] auto[1] auto[1] 14278 1 T7 60 T1 348 T3 282
auto[1] auto[1] auto[0] auto[0] auto[0] 56070 1 T7 74 T1 372 T20 56
auto[1] auto[1] auto[0] auto[0] auto[1] 6004 1 T7 30 T1 74 T20 14
auto[1] auto[1] auto[0] auto[1] auto[0] 45068 1 T7 146 T1 804 T20 88
auto[1] auto[1] auto[0] auto[1] auto[1] 10736 1 T1 338 T20 116 T21 154
auto[1] auto[1] auto[1] auto[0] auto[0] 46898 1 T7 232 T8 72 T1 578
auto[1] auto[1] auto[1] auto[0] auto[1] 11966 1 T1 122 T3 554 T62 10
auto[1] auto[1] auto[1] auto[1] auto[0] 79588 1 T7 158 T1 1680 T20 240
auto[1] auto[1] auto[1] auto[1] auto[1] 20524 1 T1 470 T3 456 T62 36

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%