Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 328999082 1 T1 414438 T5 2976 T6 2702
auto[1] 426958 1 T2 5132 T19 464 T20 606


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 329026152 1 T1 414438 T5 2976 T6 2492
auto[1] 399888 1 T6 210 T2 3520 T19 122


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 328936986 1 T1 414438 T5 2976 T6 2402
auto[1] 489054 1 T6 300 T2 4486 T19 316


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 312686358 1 T1 414438 T5 2976 T6 586
auto[1] 16739682 1 T6 2116 T2 19230 T20 2590


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 182707390 1 T1 414438 T5 2976 T6 2502
auto[1] 146718650 1 T6 200 T2 729519 T19 176


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 167182098 1 T1 414438 T5 2976 T6 300
auto[0] auto[0] auto[0] auto[0] auto[1] 145189280 1 T6 150 T2 729303 T19 74
auto[0] auto[0] auto[0] auto[1] auto[0] 30488 1 T2 184 T19 66 T20 32
auto[0] auto[0] auto[0] auto[1] auto[1] 7900 1 T2 68 T19 102 T20 10
auto[0] auto[0] auto[1] auto[0] auto[0] 14952508 1 T6 1916 T2 13910 T20 2066
auto[0] auto[0] auto[1] auto[0] auto[1] 1409766 1 T2 1090 T20 148 T22 2056
auto[0] auto[0] auto[1] auto[1] auto[0] 55972 1 T2 558 T20 8 T61 10
auto[0] auto[0] auto[1] auto[1] auto[1] 13560 1 T2 90 T20 38 T39 114
auto[0] auto[1] auto[0] auto[0] auto[0] 40566 1 T2 80 T19 40 T20 42
auto[0] auto[1] auto[0] auto[0] auto[1] 1760 1 T6 36 T2 22 T66 16
auto[0] auto[1] auto[0] auto[1] auto[0] 11882 1 T2 184 T19 50 T20 56
auto[0] auto[1] auto[0] auto[1] auto[1] 3278 1 T2 48 T10 98 T174 48
auto[0] auto[1] auto[1] auto[0] auto[0] 10340 1 T2 162 T39 14 T66 16
auto[0] auto[1] auto[1] auto[0] auto[1] 2672 1 T39 8 T66 58 T3 58
auto[0] auto[1] auto[1] auto[1] auto[0] 20720 1 T2 464 T39 60 T66 86
auto[0] auto[1] auto[1] auto[1] auto[1] 4196 1 T39 56 T3 60 T85 64
auto[1] auto[0] auto[0] auto[0] auto[0] 31886 1 T6 44 T2 140 T19 38
auto[1] auto[0] auto[0] auto[0] auto[1] 3898 1 T6 14 T2 30 T20 22
auto[1] auto[0] auto[0] auto[1] auto[0] 32358 1 T2 308 T19 246 T61 62
auto[1] auto[0] auto[0] auto[1] auto[1] 7952 1 T2 144 T20 50 T61 42
auto[1] auto[0] auto[1] auto[0] auto[0] 29326 1 T6 68 T2 220 T20 52
auto[1] auto[0] auto[1] auto[0] auto[1] 7976 1 T2 40 T20 20 T61 20
auto[1] auto[0] auto[1] auto[1] auto[0] 55502 1 T2 898 T20 74 T61 82
auto[1] auto[0] auto[1] auto[1] auto[1] 15682 1 T2 146 T20 160 T61 46
auto[1] auto[1] auto[0] auto[0] auto[0] 73946 1 T6 42 T2 136 T19 32
auto[1] auto[1] auto[0] auto[0] auto[1] 6490 1 T2 40 T84 8 T175 16
auto[1] auto[1] auto[0] auto[1] auto[0] 50134 1 T2 612 T20 178 T21 100
auto[1] auto[1] auto[0] auto[1] auto[1] 12442 1 T2 120 T3 168 T71 72
auto[1] auto[1] auto[1] auto[0] auto[0] 45574 1 T6 132 T2 262 T20 24
auto[1] auto[1] auto[1] auto[0] auto[1] 10996 1 T2 82 T22 68 T61 44
auto[1] auto[1] auto[1] auto[1] auto[0] 84090 1 T2 1074 T22 82 T39 44
auto[1] auto[1] auto[1] auto[1] auto[1] 20802 1 T2 234 T61 58 T3 224

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