Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 349550176 1 T7 6092 T8 2402 T9 3588
auto[1] 478652 1 T9 734 T27 498 T28 124


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 349571548 1 T7 6092 T8 2402 T9 3708
auto[1] 457280 1 T9 614 T27 378 T4 296


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 349479802 1 T7 6092 T8 2402 T9 3572
auto[1] 549026 1 T9 750 T27 366 T28 52


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 330534170 1 T7 6092 T8 2402 T9 4322
auto[1] 19494658 1 T27 536 T1 19826 T22 144


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 193473108 1 T7 1702 T8 2402 T9 4110
auto[1] 156555720 1 T7 4390 T9 212 T27 588


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 176715300 1 T7 1702 T8 2402 T9 3196
auto[0] auto[0] auto[0] auto[0] auto[1] 153473994 1 T7 4390 T9 106 T27 188
auto[0] auto[0] auto[0] auto[1] auto[0] 35618 1 T9 248 T27 66 T28 56
auto[0] auto[0] auto[0] auto[1] auto[1] 6928 1 T9 22 T27 46 T28 18
auto[0] auto[0] auto[1] auto[0] auto[0] 16108760 1 T27 188 T1 14136 T25 436
auto[0] auto[0] auto[1] auto[0] auto[1] 2948622 1 T27 76 T1 1778 T22 128
auto[0] auto[0] auto[1] auto[1] auto[0] 62234 1 T27 16 T1 256 T25 80
auto[0] auto[0] auto[1] auto[1] auto[1] 15304 1 T27 24 T1 330 T25 30
auto[0] auto[1] auto[0] auto[0] auto[0] 47074 1 T1 84 T25 18 T2 168
auto[0] auto[1] auto[0] auto[0] auto[1] 1812 1 T1 18 T2 36 T107 12
auto[0] auto[1] auto[0] auto[1] auto[0] 14390 1 T1 234 T25 80 T2 328
auto[0] auto[1] auto[0] auto[1] auto[1] 3636 1 T1 44 T2 196 T107 60
auto[0] auto[1] auto[1] auto[0] auto[0] 12828 1 T27 22 T1 70 T25 10
auto[0] auto[1] auto[1] auto[0] auto[1] 3180 1 T1 34 T2 68 T159 14
auto[0] auto[1] auto[1] auto[1] auto[0] 23652 1 T27 76 T1 238 T25 102
auto[0] auto[1] auto[1] auto[1] auto[1] 6470 1 T1 92 T159 56 T13 236
auto[1] auto[0] auto[0] auto[0] auto[0] 28704 1 T9 34 T1 90 T5 1404
auto[1] auto[0] auto[0] auto[0] auto[1] 5036 1 T28 2 T1 34 T2 64
auto[1] auto[0] auto[0] auto[1] auto[0] 35494 1 T9 102 T1 292 T25 156
auto[1] auto[0] auto[0] auto[1] auto[1] 9214 1 T28 50 T1 224 T2 176
auto[1] auto[0] auto[1] auto[0] auto[0] 37510 1 T1 244 T25 78 T2 724
auto[1] auto[0] auto[1] auto[0] auto[1] 9116 1 T27 18 T1 124 T22 8
auto[1] auto[0] auto[1] auto[1] auto[0] 64066 1 T1 956 T25 46 T2 898
auto[1] auto[0] auto[1] auto[1] auto[1] 15648 1 T27 68 T1 282 T2 722
auto[1] auto[1] auto[0] auto[0] auto[0] 82618 1 T9 230 T27 18 T4 296
auto[1] auto[1] auto[0] auto[0] auto[1] 7098 1 T9 22 T27 12 T1 2
auto[1] auto[1] auto[0] auto[1] auto[0] 54140 1 T9 300 T27 46 T1 600
auto[1] auto[1] auto[0] auto[1] auto[1] 13114 1 T9 62 T27 156 T1 40
auto[1] auto[1] auto[1] auto[0] auto[0] 54706 1 T27 48 T1 264 T25 42
auto[1] auto[1] auto[1] auto[0] auto[1] 13818 1 T1 64 T22 8 T25 4
auto[1] auto[1] auto[1] auto[1] auto[0] 96014 1 T1 694 T2 2236 T103 208
auto[1] auto[1] auto[1] auto[1] auto[1] 22730 1 T1 264 T25 76 T2 364

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