Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 334102090 1 T5 2516 T4 14180 T1 982540
auto[1] 430302 1 T1 7526 T16 928 T2 2630


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 334105204 1 T5 2412 T4 14180 T1 982655
auto[1] 427188 1 T5 104 T1 6368 T16 882


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 334016164 1 T5 2428 T4 14180 T1 982587
auto[1] 516228 1 T5 88 T1 7050 T16 1026


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 314369972 1 T5 134 T4 14180 T1 964113
auto[1] 20162420 1 T5 2382 T1 191796 T16 4092


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 168002316 1 T5 2158 T4 14180 T1 570689
auto[1] 166530076 1 T5 358 T1 412603 T15 1898


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 150420482 1 T5 58 T4 14180 T1 568363
auto[0] auto[0] auto[0] auto[0] auto[1] 163599676 1 T5 68 T1 395374 T15 1898
auto[0] auto[0] auto[0] auto[1] auto[0] 31992 1 T1 546 T16 10 T2 182
auto[0] auto[0] auto[0] auto[1] auto[1] 7022 1 T1 198 T16 34 T2 54
auto[0] auto[0] auto[1] auto[0] auto[0] 16978518 1 T5 2032 T1 14790 T16 2860
auto[0] auto[0] auto[1] auto[0] auto[1] 2809086 1 T5 222 T1 169466 T16 324
auto[0] auto[0] auto[1] auto[1] auto[0] 50662 1 T1 1018 T16 40 T2 300
auto[0] auto[0] auto[1] auto[1] auto[1] 13542 1 T1 334 T16 98 T2 112
auto[0] auto[1] auto[0] auto[0] auto[0] 43780 1 T1 148 T2 24 T3 48
auto[0] auto[1] auto[0] auto[0] auto[1] 1742 1 T1 12 T3 48 T8 2
auto[0] auto[1] auto[0] auto[1] auto[0] 13194 1 T1 368 T2 148 T3 88
auto[0] auto[1] auto[0] auto[1] auto[1] 3274 1 T1 88 T8 50 T13 62
auto[0] auto[1] auto[1] auto[0] auto[0] 11600 1 T5 48 T1 462 T2 42
auto[0] auto[1] auto[1] auto[0] auto[1] 2668 1 T1 106 T2 20 T3 82
auto[0] auto[1] auto[1] auto[1] auto[0] 23090 1 T1 788 T2 152 T17 56
auto[0] auto[1] auto[1] auto[1] auto[1] 5836 1 T1 176 T2 78 T3 136
auto[1] auto[0] auto[0] auto[0] auto[0] 43894 1 T1 332 T2 144 T3 114
auto[1] auto[0] auto[0] auto[0] auto[1] 4482 1 T5 8 T1 2 T2 78
auto[1] auto[0] auto[0] auto[1] auto[0] 33886 1 T1 176 T2 184 T3 610
auto[1] auto[0] auto[0] auto[1] auto[1] 7590 1 T1 82 T2 80 T3 106
auto[1] auto[0] auto[1] auto[0] auto[0] 29074 1 T5 12 T1 622 T16 56
auto[1] auto[0] auto[1] auto[0] auto[1] 7430 1 T5 12 T1 278 T2 40
auto[1] auto[0] auto[1] auto[1] auto[0] 53164 1 T1 886 T16 88 T2 286
auto[1] auto[0] auto[1] auto[1] auto[1] 14704 1 T1 452 T2 138 T3 214
auto[1] auto[1] auto[0] auto[0] auto[0] 86700 1 T1 482 T16 30 T2 174
auto[1] auto[1] auto[0] auto[0] auto[1] 6632 1 T1 282 T16 16 T2 102
auto[1] auto[1] auto[0] auto[1] auto[0] 52644 1 T1 840 T16 156 T2 270
auto[1] auto[1] auto[0] auto[1] auto[1] 12982 1 T1 198 T16 54 T2 158
auto[1] auto[1] auto[1] auto[0] auto[0] 44368 1 T5 8 T1 800 T16 114
auto[1] auto[1] auto[1] auto[0] auto[1] 11958 1 T5 48 T1 242 T16 64
auto[1] auto[1] auto[1] auto[1] auto[0] 85268 1 T1 1002 T16 292 T2 418
auto[1] auto[1] auto[1] auto[1] auto[1] 21452 1 T1 374 T16 156 T2 70

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%