Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 321048418 1 T5 186648 T6 67614 T4 11190
auto[1] 450514 1 T26 524 T27 484 T1 10026


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 321046556 1 T5 186648 T6 67614 T4 8198
auto[1] 452376 1 T4 2992 T26 200 T27 358


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 320993088 1 T5 186648 T6 67614 T4 8198
auto[1] 505844 1 T4 2992 T25 26 T26 464


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 303274586 1 T5 186648 T6 67614 T4 11190
auto[1] 18224346 1 T25 1268 T26 2228 T27 792


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 190605610 1 T5 186626 T6 67614 T4 11170
auto[1] 130893322 1 T5 22 T4 20 T24 2206


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 175043294 1 T5 186626 T6 67614 T4 8178
auto[0] auto[0] auto[0] auto[0] auto[1] 127867046 1 T5 22 T4 20 T24 2206
auto[0] auto[0] auto[0] auto[1] auto[0] 32118 1 T26 34 T1 570 T2 58
auto[0] auto[0] auto[0] auto[1] auto[1] 8598 1 T27 2 T1 242 T17 80
auto[0] auto[0] auto[1] auto[0] auto[0] 14930600 1 T25 1242 T26 554 T27 380
auto[0] auto[0] auto[1] auto[0] auto[1] 2895206 1 T26 1234 T27 98 T1 3336
auto[0] auto[0] auto[1] auto[1] auto[0] 56596 1 T26 32 T27 142 T1 1824
auto[0] auto[0] auto[1] auto[1] auto[1] 14022 1 T26 20 T1 192 T2 22
auto[0] auto[1] auto[0] auto[0] auto[0] 85748 1 T26 2 T27 34 T1 20
auto[0] auto[1] auto[0] auto[0] auto[1] 1396 1 T2 46 T3 36 T117 14
auto[0] auto[1] auto[0] auto[1] auto[0] 12830 1 T26 56 T27 104 T1 82
auto[0] auto[1] auto[0] auto[1] auto[1] 2750 1 T117 118 T177 64 T88 70
auto[0] auto[1] auto[1] auto[0] auto[0] 11520 1 T27 14 T1 408 T16 20
auto[0] auto[1] auto[1] auto[0] auto[1] 3366 1 T1 152 T3 18 T108 6
auto[0] auto[1] auto[1] auto[1] auto[0] 21548 1 T27 54 T1 546 T16 66
auto[0] auto[1] auto[1] auto[1] auto[1] 6450 1 T1 268 T3 62 T108 56
auto[1] auto[0] auto[0] auto[0] auto[0] 42264 1 T26 2 T1 322 T2 66
auto[1] auto[0] auto[0] auto[0] auto[1] 5036 1 T26 8 T1 128 T117 18
auto[1] auto[0] auto[0] auto[1] auto[0] 33024 1 T26 66 T1 532 T2 140
auto[1] auto[0] auto[0] auto[1] auto[1] 9762 1 T1 298 T117 66 T88 78
auto[1] auto[0] auto[1] auto[0] auto[0] 30526 1 T25 26 T26 26 T27 28
auto[1] auto[0] auto[1] auto[0] auto[1] 7712 1 T26 6 T1 330 T21 38
auto[1] auto[0] auto[1] auto[1] auto[0] 57614 1 T26 58 T27 36 T1 1810
auto[1] auto[0] auto[1] auto[1] auto[1] 13138 1 T26 156 T1 340 T88 74
auto[1] auto[1] auto[0] auto[0] auto[0] 55150 1 T4 2992 T27 2 T1 756
auto[1] auto[1] auto[0] auto[0] auto[1] 7440 1 T27 2 T1 162 T108 22
auto[1] auto[1] auto[0] auto[1] auto[0] 53118 1 T27 46 T1 898 T16 96
auto[1] auto[1] auto[0] auto[1] auto[1] 15012 1 T27 62 T1 196 T178 52
auto[1] auto[1] auto[1] auto[0] auto[0] 49194 1 T26 40 T27 2 T1 1588
auto[1] auto[1] auto[1] auto[0] auto[1] 12920 1 T1 182 T2 62 T3 42
auto[1] auto[1] auto[1] auto[1] auto[0] 90466 1 T26 102 T27 38 T1 2016
auto[1] auto[1] auto[1] auto[1] auto[1] 23468 1 T1 212 T2 84 T3 80

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%