Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 330811894 1 T1 388324 T5 3798 T4 60600
auto[1] 403502 1 T1 1170 T16 532 T3 624


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 330845626 1 T1 388756 T5 3516 T4 60600
auto[1] 369770 1 T1 738 T5 282 T16 230


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 330728994 1 T1 387948 T5 3474 T4 60600
auto[1] 486402 1 T1 1546 T5 324 T16 426


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 312725926 1 T1 384104 T5 814 T4 60600
auto[1] 18489470 1 T1 5390 T5 2984 T3 1196


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 186645066 1 T1 158988 T5 1430 T4 60582
auto[1] 144570330 1 T1 230506 T5 2368 T4 18


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 169936238 1 T1 153540 T5 530 T4 60582
auto[0] auto[0] auto[0] auto[0] auto[1] 142468408 1 T1 230070 T5 78 T4 18
auto[0] auto[0] auto[0] auto[1] auto[0] 30000 1 T1 32 T16 166 T3 18
auto[0] auto[0] auto[0] auto[1] auto[1] 6834 1 T104 18 T12 24 T14 52
auto[0] auto[0] auto[1] auto[0] auto[0] 16143022 1 T1 3876 T5 552 T3 518
auto[0] auto[0] auto[1] auto[0] auto[1] 1991438 1 T1 172 T5 2218 T3 136
auto[0] auto[0] auto[1] auto[1] auto[0] 50220 1 T1 146 T3 28 T104 104
auto[0] auto[0] auto[1] auto[1] auto[1] 12426 1 T1 40 T3 32 T104 92
auto[0] auto[1] auto[0] auto[0] auto[0] 35516 1 T5 36 T3 14 T71 34
auto[0] auto[1] auto[0] auto[0] auto[1] 1884 1 T12 4 T14 4 T154 22
auto[0] auto[1] auto[0] auto[1] auto[0] 12012 1 T3 54 T104 38 T12 162
auto[0] auto[1] auto[0] auto[1] auto[1] 3038 1 T12 86 T14 96 T179 60
auto[0] auto[1] auto[1] auto[0] auto[0] 10752 1 T1 72 T5 60 T3 36
auto[0] auto[1] auto[1] auto[0] auto[1] 2718 1 T12 8 T14 60 T22 40
auto[0] auto[1] auto[1] auto[1] auto[0] 20064 1 T3 62 T12 300 T14 100
auto[0] auto[1] auto[1] auto[1] auto[1] 4424 1 T12 144 T14 170 T22 100
auto[1] auto[0] auto[0] auto[0] auto[0] 58504 1 T1 142 T5 66 T16 18
auto[1] auto[0] auto[0] auto[0] auto[1] 4474 1 T1 20 T5 42 T16 22
auto[1] auto[0] auto[0] auto[1] auto[0] 30352 1 T1 58 T16 100 T3 60
auto[1] auto[0] auto[0] auto[1] auto[1] 8858 1 T1 64 T16 56 T17 48
auto[1] auto[0] auto[1] auto[0] auto[0] 29266 1 T1 146 T3 22 T17 8
auto[1] auto[0] auto[1] auto[0] auto[1] 7004 1 T1 4 T5 30 T71 14
auto[1] auto[0] auto[1] auto[1] auto[0] 55696 1 T1 382 T3 62 T70 58
auto[1] auto[0] auto[1] auto[1] auto[1] 12886 1 T1 64 T12 216 T13 64
auto[1] auto[1] auto[0] auto[0] auto[0] 64856 1 T1 102 T5 62 T16 20
auto[1] auto[1] auto[0] auto[0] auto[1] 4980 1 T3 24 T71 28 T12 88
auto[1] auto[1] auto[0] auto[1] auto[0] 48928 1 T1 76 T16 210 T104 226
auto[1] auto[1] auto[0] auto[1] auto[1] 11044 1 T3 48 T12 152 T14 166
auto[1] auto[1] auto[1] auto[0] auto[0] 43026 1 T1 158 T5 124 T3 26
auto[1] auto[1] auto[1] auto[0] auto[1] 9808 1 T1 22 T3 14 T70 50
auto[1] auto[1] auto[1] auto[1] auto[0] 76614 1 T1 258 T3 122 T104 192
auto[1] auto[1] auto[1] auto[1] auto[1] 20106 1 T1 50 T3 138 T12 656

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