Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

314768164

1

T6

353128

T7

3454

T8

2188

auto[1]

404706

1

T7

618

T30

40

T32

118

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

314765212

1

T6

353128

T7

3566

T8

2188

auto[1]

407658

1

T7

506

T26

220

T30

94

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

314654534

1

T6

353128

T7

3572

T8

2188

auto[1]

518336

1

T7

500

T26

322

T30

54

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299217514

1

T6

353128

T7

898

T8

2188

auto[1]

15955356

1

T7

3174

T26

2512

T30

600

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

185154900

1

T6

353128

T7

3024

T8

2188

auto[1]

130017970

1

T7

1048

T26

218

T30

472

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

171411768

1

T6

353128

T7

478

T8

2188

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

127456056

1

T7

220

T26

166

T30

124

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

28834

1

T7

78

T32

24

T44

76

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8028

1

T44

6

T128

50

T87

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

13149922

1

T7

2108

T26

2300

T30

236

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2446544

1

T7

508

T30

298

T44

534

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

49482

1

T44

60

T128

138

T87

282

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12666

1

T7

66

T44

96

T43

16

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

34118

1

T7

2

T26

14

T30

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1848

1

T26

24

T88

30

T92

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

10508

1

T7

50

T30

40

T90

74

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3952

1

T88

112

T1

42

T162

146

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10670

1

T26

62

T44

18

T128

10

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3312

1

T7

10

T30

20

T44

18

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

21718

1

T44

60

T128

72

T88

158

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5108

1

T7

52

T44

64

T128

86

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

59432

1

T7

16

T26

68

T32

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3638

1

T26

28

T44

6

T128

46

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

31500

1

T32

94

T44

108

T87

142

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7028

1

T44

62

T128

60

T87

84

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

29202

1

T7

32

T26

106

T30

16

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5912

1

T30

14

T44

28

T43

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

51778

1

T7

60

T128

192

T87

124

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13422

1

T44

122

T43

66

T87

82

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

96466

1

T7

2

T26

76

T44

16

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5546

1

T7

8

T30

8

T128

16

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

47562

1

T7

44

T44

64

T87

86

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11230

1

T128

106

T90

56

T92

42

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

42566

1

T7

34

T26

44

T30

8

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11164

1

T7

36

T30

8

T44

44

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

79374

1

T7

120

T44

62

T43

54

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

22516

1

T7

148

T44

52

T128

98