Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.01	98.80

Total test records in report: 1010

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1003	/workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3866507703			May 12 01:18:59 PM PDT 24	May 12 01:19:01 PM PDT 24	55754618 ps
T1004	/workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.2700139081			May 12 01:18:22 PM PDT 24	May 12 01:18:27 PM PDT 24	137286849 ps
T145	/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.106222402			May 12 01:18:43 PM PDT 24	May 12 01:18:45 PM PDT 24	133769995 ps
T1005	/workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.2067228867			May 12 01:18:53 PM PDT 24	May 12 01:18:55 PM PDT 24	18065214 ps
T1006	/workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3406607871			May 12 01:18:32 PM PDT 24	May 12 01:18:33 PM PDT 24	12754480 ps
T1007	/workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.4163842910			May 12 01:18:33 PM PDT 24	May 12 01:18:36 PM PDT 24	137549060 ps
T1008	/workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.2087389959			May 12 01:18:45 PM PDT 24	May 12 01:18:48 PM PDT 24	257717089 ps
T1009	/workspace/coverage/cover_reg_top/37.clkmgr_intr_test.1208371708			May 12 01:18:56 PM PDT 24	May 12 01:18:57 PM PDT 24	20807912 ps
T185	/workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3758803359			May 12 01:18:29 PM PDT 24	May 12 01:18:34 PM PDT 24	609382262 ps
T1010	/workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2380676696			May 12 01:18:23 PM PDT 24	May 12 01:18:25 PM PDT 24	33642539 ps

Test location	/workspace/coverage/default/14.clkmgr_frequency_timeout.2330737147
Short name	T6
Test name
Test status
Simulation time	1822335842 ps
CPU time	12.8 seconds
Started	May 12 01:22:12 PM PDT 24
Finished	May 12 01:22:25 PM PDT 24
Peak memory	200620 kb
Host	smart-985ce445-4d9c-4f42-b9e4-47267c839243
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330737147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t imeout.2330737147
Directory	/workspace/14.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/45.clkmgr_stress_all.3447746487
Short name	T1
Test name
Test status
Simulation time	8424481712 ps
CPU time	59.5 seconds
Started	May 12 01:23:36 PM PDT 24
Finished	May 12 01:24:36 PM PDT 24
Peak memory	200924 kb
Host	smart-a603be99-042a-45c9-9e0d-f9db20bab7cb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447746487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all.3447746487
Directory	/workspace/45.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/38.clkmgr_extclk.1073728172
Short name	T7
Test name
Test status
Simulation time	86559556 ps
CPU time	1.02 seconds
Started	May 12 01:23:17 PM PDT 24
Finished	May 12 01:23:19 PM PDT 24
Peak memory	200540 kb
Host	smart-6d05c956-427c-49ca-abb5-9e0b4c854377
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073728172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.1073728172
Directory	/workspace/38.clkmgr_extclk/latest

Test location	/workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.2788248429
Short name	T3
Test name
Test status
Simulation time	68119090729 ps
CPU time	460.6 seconds
Started	May 12 01:21:58 PM PDT 24
Finished	May 12 01:29:39 PM PDT 24
Peak memory	217352 kb
Host	smart-76e32811-d812-422b-804c-771460945ea2
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2788248429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.2788248429
Directory	/workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2961172758
Short name	T74
Test name
Test status
Simulation time	206700609 ps
CPU time	2.21 seconds
Started	May 12 01:18:21 PM PDT 24
Finished	May 12 01:18:24 PM PDT 24
Peak memory	209292 kb
Host	smart-22ebc608-51ce-4436-bf1d-53fa0fe09472
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961172758 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.clkmgr_shadow_reg_errors.2961172758
Directory	/workspace/2.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/39.clkmgr_regwen.403023312
Short name	T4
Test name
Test status
Simulation time	647017247 ps
CPU time	2.81 seconds
Started	May 12 01:23:22 PM PDT 24
Finished	May 12 01:23:25 PM PDT 24
Peak memory	200592 kb
Host	smart-8e197a53-a395-4619-9f2a-30a715604702
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403023312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.403023312
Directory	/workspace/39.clkmgr_regwen/latest

Test location	/workspace/coverage/default/1.clkmgr_sec_cm.267210459
Short name	T58
Test name
Test status
Simulation time	5351055098 ps
CPU time	16.48 seconds
Started	May 12 01:21:17 PM PDT 24
Finished	May 12 01:21:34 PM PDT 24
Peak memory	216536 kb
Host	smart-c04bb413-2ba6-4f44-adc3-5aeb3f7b94cd
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267210459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr _sec_cm.267210459
Directory	/workspace/1.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/12.clkmgr_clk_status.2061813922
Short name	T182
Test name
Test status
Simulation time	34733021 ps
CPU time	0.75 seconds
Started	May 12 01:22:08 PM PDT 24
Finished	May 12 01:22:09 PM PDT 24
Peak memory	199488 kb
Host	smart-7e59afe5-e9e7-4165-8333-a8ce2eada7bd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061813922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.2061813922
Directory	/workspace/12.clkmgr_clk_status/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.406635292
Short name	T69
Test name
Test status
Simulation time	85896549 ps
CPU time	1.86 seconds
Started	May 12 01:18:31 PM PDT 24
Finished	May 12 01:18:34 PM PDT 24
Peak memory	200988 kb
Host	smart-aa53e4ad-7a07-406d-97d3-ac42c629e69c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406635292 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.406635292
Directory	/workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/12.clkmgr_idle_intersig_mubi.107416225
Short name	T253
Test name
Test status
Simulation time	204710432 ps
CPU time	1.43 seconds
Started	May 12 01:22:08 PM PDT 24
Finished	May 12 01:22:10 PM PDT 24
Peak memory	200456 kb
Host	smart-c4790f5b-df16-4b66-bc39-056713ab3a7c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107416225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.clkmgr_idle_intersig_mubi.107416225
Directory	/workspace/12.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1950079251
Short name	T126
Test name
Test status
Simulation time	129624138 ps
CPU time	2.82 seconds
Started	May 12 01:18:30 PM PDT 24
Finished	May 12 01:18:34 PM PDT 24
Peak memory	200672 kb
Host	smart-73672f20-6a57-43fa-8429-966513cd430c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950079251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 5.clkmgr_tl_intg_err.1950079251
Directory	/workspace/5.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.1583062613
Short name	T81
Test name
Test status
Simulation time	24068155271 ps
CPU time	369.94 seconds
Started	May 12 01:21:38 PM PDT 24
Finished	May 12 01:27:48 PM PDT 24
Peak memory	217344 kb
Host	smart-0bdd4f02-2d35-477f-8274-445b5564bf50
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1583062613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.1583062613
Directory	/workspace/4.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.clkmgr_sec_cm.3036372302
Short name	T47
Test name
Test status
Simulation time	177238232 ps
CPU time	2.23 seconds
Started	May 12 01:21:29 PM PDT 24
Finished	May 12 01:21:31 PM PDT 24
Peak memory	215984 kb
Host	smart-488a150e-945d-44a0-8085-5f3120d23a98
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036372302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg r_sec_cm.3036372302
Directory	/workspace/2.clkmgr_sec_cm/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.337976591
Short name	T77
Test name
Test status
Simulation time	111940443 ps
CPU time	1.99 seconds
Started	May 12 01:18:36 PM PDT 24
Finished	May 12 01:18:39 PM PDT 24
Peak memory	201044 kb
Host	smart-d4672ca7-1aff-48c2-a7dc-16c3d5382458
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337976591 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 9.clkmgr_shadow_reg_errors.337976591
Directory	/workspace/9.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/default/1.clkmgr_alert_test.46760222
Short name	T36
Test name
Test status
Simulation time	33699037 ps
CPU time	0.81 seconds
Started	May 12 01:21:19 PM PDT 24
Finished	May 12 01:21:20 PM PDT 24
Peak memory	200512 kb
Host	smart-0ecc611b-9f96-45c8-b5c2-fdea480a6de3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46760222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr _alert_test.46760222
Directory	/workspace/1.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.3811319014
Short name	T80
Test name
Test status
Simulation time	113763202980 ps
CPU time	654.07 seconds
Started	May 12 01:22:06 PM PDT 24
Finished	May 12 01:33:01 PM PDT 24
Peak memory	212040 kb
Host	smart-7f7c734a-b8ca-4777-bc00-db7ced16567b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3811319014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.3811319014
Directory	/workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.2033407651
Short name	T91
Test name
Test status
Simulation time	44916715 ps
CPU time	0.89 seconds
Started	May 12 01:21:16 PM PDT 24
Finished	May 12 01:21:17 PM PDT 24
Peak memory	200484 kb
Host	smart-9bb0ce72-7002-4423-b135-14cc128180f1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033407651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_handshake_intersig_mubi.2033407651
Directory	/workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_regwen.25629680
Short name	T9
Test name
Test status
Simulation time	1056147706 ps
CPU time	6.41 seconds
Started	May 12 01:22:52 PM PDT 24
Finished	May 12 01:23:00 PM PDT 24
Peak memory	200604 kb
Host	smart-300b949c-dd3e-4c9c-ab40-a59c601f02d2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25629680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.25629680
Directory	/workspace/28.clkmgr_regwen/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.551242805
Short name	T139
Test name
Test status
Simulation time	59118888 ps
CPU time	1.39 seconds
Started	May 12 01:18:49 PM PDT 24
Finished	May 12 01:18:51 PM PDT 24
Peak memory	200864 kb
Host	smart-b74d2843-b247-4141-a9e5-24abfcb0767d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551242805 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 19.clkmgr_shadow_reg_errors.551242805
Directory	/workspace/19.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3758803359
Short name	T185
Test name
Test status
Simulation time	609382262 ps
CPU time	4.35 seconds
Started	May 12 01:18:29 PM PDT 24
Finished	May 12 01:18:34 PM PDT 24
Peak memory	200568 kb
Host	smart-0c0554f2-0be4-4314-9e12-d511b00c3a8a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758803359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 7.clkmgr_tl_intg_err.3758803359
Directory	/workspace/7.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.597701713
Short name	T339
Test name
Test status
Simulation time	29704327684 ps
CPU time	555.45 seconds
Started	May 12 01:22:10 PM PDT 24
Finished	May 12 01:31:26 PM PDT 24
Peak memory	209192 kb
Host	smart-93361cc5-297f-4f89-8606-83de06112921
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=597701713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.597701713
Directory	/workspace/14.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.3955118683
Short name	T136
Test name
Test status
Simulation time	123408490 ps
CPU time	2.08 seconds
Started	May 12 01:18:50 PM PDT 24
Finished	May 12 01:18:54 PM PDT 24
Peak memory	201056 kb
Host	smart-bcf29b01-704c-4c0d-9991-f0be054bacab
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955118683 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 14.clkmgr_shadow_reg_errors.3955118683
Directory	/workspace/14.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2444589883
Short name	T124
Test name
Test status
Simulation time	142740842 ps
CPU time	2.77 seconds
Started	May 12 01:18:54 PM PDT 24
Finished	May 12 01:18:57 PM PDT 24
Peak memory	200652 kb
Host	smart-06b76888-21d1-442b-9b1a-12464011efd6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444589883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 16.clkmgr_tl_intg_err.2444589883
Directory	/workspace/16.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/11.clkmgr_stress_all.1045340908
Short name	T782
Test name
Test status
Simulation time	5936414573 ps
CPU time	29.83 seconds
Started	May 12 01:22:04 PM PDT 24
Finished	May 12 01:22:35 PM PDT 24
Peak memory	201012 kb
Host	smart-4e650a42-347a-4573-9203-dca8f7e08a2d
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045340908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all.1045340908
Directory	/workspace/11.clkmgr_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.622592877
Short name	T113
Test name
Test status
Simulation time	123707209 ps
CPU time	2.54 seconds
Started	May 12 01:18:20 PM PDT 24
Finished	May 12 01:18:23 PM PDT 24
Peak memory	200516 kb
Host	smart-4549c4ce-0681-4212-a83b-b9f56636751a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622592877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 0.clkmgr_tl_intg_err.622592877
Directory	/workspace/0.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2174551546
Short name	T116
Test name
Test status
Simulation time	246609707 ps
CPU time	3.23 seconds
Started	May 12 01:18:40 PM PDT 24
Finished	May 12 01:18:44 PM PDT 24
Peak memory	200620 kb
Host	smart-7c761b83-4020-4088-bf17-dd4b86042bd5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174551546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 10.clkmgr_tl_intg_err.2174551546
Directory	/workspace/10.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.2877867443
Short name	T968
Test name
Test status
Simulation time	106047757 ps
CPU time	1.68 seconds
Started	May 12 01:18:23 PM PDT 24
Finished	May 12 01:18:25 PM PDT 24
Peak memory	200564 kb
Host	smart-00c668db-6660-4364-93df-92c7c33c86ef
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877867443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_aliasing.2877867443
Directory	/workspace/0.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3933608196
Short name	T981
Test name
Test status
Simulation time	268372269 ps
CPU time	4.6 seconds
Started	May 12 01:18:22 PM PDT 24
Finished	May 12 01:18:27 PM PDT 24
Peak memory	200592 kb
Host	smart-9f486c5b-bfc5-426c-9a79-aa1f6682e048
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933608196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_bit_bash.3933608196
Directory	/workspace/0.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1169798527
Short name	T976
Test name
Test status
Simulation time	20077244 ps
CPU time	0.8 seconds
Started	May 12 01:18:21 PM PDT 24
Finished	May 12 01:18:22 PM PDT 24
Peak memory	200312 kb
Host	smart-e79bf93e-5c7f-4db3-8397-0676f3e78471
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169798527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.clkmgr_csr_hw_reset.1169798527
Directory	/workspace/0.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.254247645
Short name	T864
Test name
Test status
Simulation time	79797219 ps
CPU time	1.87 seconds
Started	May 12 01:18:24 PM PDT 24
Finished	May 12 01:18:26 PM PDT 24
Peak memory	200568 kb
Host	smart-cdff1567-3975-48da-853e-9319c32d391c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254247645 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.254247645
Directory	/workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.2508783449
Short name	T952
Test name
Test status
Simulation time	28888599 ps
CPU time	0.82 seconds
Started	May 12 01:18:25 PM PDT 24
Finished	May 12 01:18:26 PM PDT 24
Peak memory	200400 kb
Host	smart-580a40de-399d-4d9e-8a0c-e37bea1666ad
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508783449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. clkmgr_csr_rw.2508783449
Directory	/workspace/0.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_intr_test.4006938845
Short name	T891
Test name
Test status
Simulation time	30130385 ps
CPU time	0.67 seconds
Started	May 12 01:18:21 PM PDT 24
Finished	May 12 01:18:22 PM PDT 24
Peak memory	198912 kb
Host	smart-9e7eb008-4ed6-49a3-a31b-b006579d1f8e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006938845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk mgr_intr_test.4006938845
Directory	/workspace/0.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1909615536
Short name	T887
Test name
Test status
Simulation time	56333996 ps
CPU time	1 seconds
Started	May 12 01:18:21 PM PDT 24
Finished	May 12 01:18:23 PM PDT 24
Peak memory	200456 kb
Host	smart-b99a07b4-d351-41b8-976d-a08173c4ea67
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909615536 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.clkmgr_same_csr_outstanding.1909615536
Directory	/workspace/0.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.605779152
Short name	T137
Test name
Test status
Simulation time	197821995 ps
CPU time	1.69 seconds
Started	May 12 01:18:20 PM PDT 24
Finished	May 12 01:18:22 PM PDT 24
Peak memory	200840 kb
Host	smart-77724ff8-e31e-4f29-acec-a2794fb3554c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605779152 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.clkmgr_shadow_reg_errors.605779152
Directory	/workspace/0.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.4230523128
Short name	T142
Test name
Test status
Simulation time	180666552 ps
CPU time	3.03 seconds
Started	May 12 01:18:15 PM PDT 24
Finished	May 12 01:18:18 PM PDT 24
Peak memory	209204 kb
Host	smart-7e38c144-0ce4-4e79-b098-fc1c652ca1e1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230523128 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.4230523128
Directory	/workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.4103635847
Short name	T949
Test name
Test status
Simulation time	48884761 ps
CPU time	2.84 seconds
Started	May 12 01:18:23 PM PDT 24
Finished	May 12 01:18:26 PM PDT 24
Peak memory	200668 kb
Host	smart-f2765abb-bc84-4244-8c41-5119864db4be
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103635847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk mgr_tl_errors.4103635847
Directory	/workspace/0.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.3478847766
Short name	T977
Test name
Test status
Simulation time	37665693 ps
CPU time	1.25 seconds
Started	May 12 01:18:21 PM PDT 24
Finished	May 12 01:18:23 PM PDT 24
Peak memory	200548 kb
Host	smart-646dece7-b8f9-4ee7-97bc-3ddc673f387c
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478847766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_aliasing.3478847766
Directory	/workspace/1.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.4181882251
Short name	T892
Test name
Test status
Simulation time	136640253 ps
CPU time	3.54 seconds
Started	May 12 01:18:22 PM PDT 24
Finished	May 12 01:18:27 PM PDT 24
Peak memory	200608 kb
Host	smart-3840196f-bbe4-4f72-8e19-241e9db23adb
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181882251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_bit_bash.4181882251
Directory	/workspace/1.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.1429777877
Short name	T931
Test name
Test status
Simulation time	16052807 ps
CPU time	0.79 seconds
Started	May 12 01:18:21 PM PDT 24
Finished	May 12 01:18:22 PM PDT 24
Peak memory	200564 kb
Host	smart-2f3a40aa-28f9-48ca-b165-62f84ec767ee
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429777877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.clkmgr_csr_hw_reset.1429777877
Directory	/workspace/1.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.4288836387
Short name	T987
Test name
Test status
Simulation time	29136392 ps
CPU time	1.45 seconds
Started	May 12 01:18:23 PM PDT 24
Finished	May 12 01:18:25 PM PDT 24
Peak memory	200668 kb
Host	smart-828de6c2-c017-4ece-b5cc-42535fc89901
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288836387 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.4288836387
Directory	/workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2380676696
Short name	T1010
Test name
Test status
Simulation time	33642539 ps
CPU time	0.88 seconds
Started	May 12 01:18:23 PM PDT 24
Finished	May 12 01:18:25 PM PDT 24
Peak memory	200352 kb
Host	smart-821d3c6f-c17b-4f2c-9c69-f9f554adcf91
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380676696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. clkmgr_csr_rw.2380676696
Directory	/workspace/1.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_intr_test.1976739074
Short name	T995
Test name
Test status
Simulation time	11050465 ps
CPU time	0.66 seconds
Started	May 12 01:18:23 PM PDT 24
Finished	May 12 01:18:25 PM PDT 24
Peak memory	198980 kb
Host	smart-9194503f-f6a3-416b-89f4-25a52273e39a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976739074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk mgr_intr_test.1976739074
Directory	/workspace/1.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3762412149
Short name	T888
Test name
Test status
Simulation time	27416196 ps
CPU time	0.93 seconds
Started	May 12 01:18:21 PM PDT 24
Finished	May 12 01:18:23 PM PDT 24
Peak memory	200404 kb
Host	smart-d6f0f4b7-7a8d-4d4a-8ba5-bd0e7c987c8c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762412149 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.clkmgr_same_csr_outstanding.3762412149
Directory	/workspace/1.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.4198620215
Short name	T75
Test name
Test status
Simulation time	86453747 ps
CPU time	1.44 seconds
Started	May 12 01:18:24 PM PDT 24
Finished	May 12 01:18:26 PM PDT 24
Peak memory	200840 kb
Host	smart-98465035-1a03-46eb-94af-0f929c342c74
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198620215 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 1.clkmgr_shadow_reg_errors.4198620215
Directory	/workspace/1.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.1069856715
Short name	T974
Test name
Test status
Simulation time	178845868 ps
CPU time	2.4 seconds
Started	May 12 01:18:22 PM PDT 24
Finished	May 12 01:18:25 PM PDT 24
Peak memory	201224 kb
Host	smart-ffff54db-0acb-4208-a539-bce46c5798aa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069856715 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.1069856715
Directory	/workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.2700139081
Short name	T1004
Test name
Test status
Simulation time	137286849 ps
CPU time	3.38 seconds
Started	May 12 01:18:22 PM PDT 24
Finished	May 12 01:18:27 PM PDT 24
Peak memory	200536 kb
Host	smart-432dd127-f812-4711-83a8-b0def5a1dc7a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700139081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk mgr_tl_errors.2700139081
Directory	/workspace/1.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.509241775
Short name	T125
Test name
Test status
Simulation time	479165261 ps
CPU time	2.68 seconds
Started	May 12 01:18:24 PM PDT 24
Finished	May 12 01:18:27 PM PDT 24
Peak memory	200632 kb
Host	smart-6ee48528-f9bd-4677-b6a3-096833f65263
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509241775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 1.clkmgr_tl_intg_err.509241775
Directory	/workspace/1.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.4254615338
Short name	T943
Test name
Test status
Simulation time	29748054 ps
CPU time	1.03 seconds
Started	May 12 01:18:42 PM PDT 24
Finished	May 12 01:18:44 PM PDT 24
Peak memory	200364 kb
Host	smart-281ed770-8a03-48c8-a190-45bd973c30e6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254615338 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.4254615338
Directory	/workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.225491382
Short name	T1002
Test name
Test status
Simulation time	110771462 ps
CPU time	0.96 seconds
Started	May 12 01:18:42 PM PDT 24
Finished	May 12 01:18:44 PM PDT 24
Peak memory	200256 kb
Host	smart-0d767052-44aa-466c-bb1d-18189dd99c83
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225491382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. clkmgr_csr_rw.225491382
Directory	/workspace/10.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1784994564
Short name	T910
Test name
Test status
Simulation time	20480956 ps
CPU time	0.69 seconds
Started	May 12 01:18:41 PM PDT 24
Finished	May 12 01:18:42 PM PDT 24
Peak memory	198828 kb
Host	smart-334261e2-7b6f-481a-9d6c-f5559aadc515
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784994564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl kmgr_intr_test.1784994564
Directory	/workspace/10.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.867173646
Short name	T895
Test name
Test status
Simulation time	101723965 ps
CPU time	1.23 seconds
Started	May 12 01:18:42 PM PDT 24
Finished	May 12 01:18:44 PM PDT 24
Peak memory	200448 kb
Host	smart-49674faa-7453-4257-a782-5df657f96ba3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867173646 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 10.clkmgr_same_csr_outstanding.867173646
Directory	/workspace/10.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.2818215239
Short name	T945
Test name
Test status
Simulation time	140911776 ps
CPU time	1.85 seconds
Started	May 12 01:18:44 PM PDT 24
Finished	May 12 01:18:46 PM PDT 24
Peak memory	217404 kb
Host	smart-4ebef6d5-48e7-445b-9b50-8a6553d7d5a6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818215239 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 10.clkmgr_shadow_reg_errors.2818215239
Directory	/workspace/10.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2773681393
Short name	T134
Test name
Test status
Simulation time	187073809 ps
CPU time	2.99 seconds
Started	May 12 01:18:41 PM PDT 24
Finished	May 12 01:18:45 PM PDT 24
Peak memory	217276 kb
Host	smart-26d06032-0c9e-42d8-a126-163919029b96
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773681393 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.2773681393
Directory	/workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.330197091
Short name	T869
Test name
Test status
Simulation time	73360510 ps
CPU time	2.41 seconds
Started	May 12 01:18:42 PM PDT 24
Finished	May 12 01:18:45 PM PDT 24
Peak memory	200648 kb
Host	smart-c1f9d219-9702-4859-afce-2a29c6321677
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330197091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clk mgr_tl_errors.330197091
Directory	/workspace/10.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1853087129
Short name	T971
Test name
Test status
Simulation time	86563735 ps
CPU time	1.71 seconds
Started	May 12 01:18:40 PM PDT 24
Finished	May 12 01:18:43 PM PDT 24
Peak memory	208808 kb
Host	smart-92d41f9e-4caf-4959-801e-64f1f49368ad
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853087129 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.1853087129
Directory	/workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.1820527347
Short name	T991
Test name
Test status
Simulation time	15851023 ps
CPU time	0.75 seconds
Started	May 12 01:18:41 PM PDT 24
Finished	May 12 01:18:42 PM PDT 24
Peak memory	200368 kb
Host	smart-eedcb66a-1696-4809-afba-0a5d2e0276a3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820527347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .clkmgr_csr_rw.1820527347
Directory	/workspace/11.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_intr_test.2961583261
Short name	T874
Test name
Test status
Simulation time	21889205 ps
CPU time	0.69 seconds
Started	May 12 01:18:44 PM PDT 24
Finished	May 12 01:18:45 PM PDT 24
Peak memory	198808 kb
Host	smart-fa382fd2-7ae4-47b3-a44a-2b7d36112974
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961583261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl kmgr_intr_test.2961583261
Directory	/workspace/11.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.1509516553
Short name	T879
Test name
Test status
Simulation time	76283190 ps
CPU time	1.33 seconds
Started	May 12 01:18:42 PM PDT 24
Finished	May 12 01:18:44 PM PDT 24
Peak memory	200516 kb
Host	smart-033bdef5-9c07-46a4-a377-8f61028c0614
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509516553 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 11.clkmgr_same_csr_outstanding.1509516553
Directory	/workspace/11.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.1688925712
Short name	T151
Test name
Test status
Simulation time	58862428 ps
CPU time	1.34 seconds
Started	May 12 01:18:40 PM PDT 24
Finished	May 12 01:18:42 PM PDT 24
Peak memory	200836 kb
Host	smart-512e1d68-6057-4ae2-84ae-887d25e55691
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688925712 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 11.clkmgr_shadow_reg_errors.1688925712
Directory	/workspace/11.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3974608318
Short name	T138
Test name
Test status
Simulation time	157829575 ps
CPU time	2.65 seconds
Started	May 12 01:18:39 PM PDT 24
Finished	May 12 01:18:43 PM PDT 24
Peak memory	201476 kb
Host	smart-17413c24-7f08-4f69-b0a7-68ce168c6875
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974608318 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.3974608318
Directory	/workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.3569007325
Short name	T909
Test name
Test status
Simulation time	86213040 ps
CPU time	1.41 seconds
Started	May 12 01:18:43 PM PDT 24
Finished	May 12 01:18:45 PM PDT 24
Peak memory	200652 kb
Host	smart-ce5af06f-7338-4e4e-84fc-af38e0870594
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569007325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl kmgr_tl_errors.3569007325
Directory	/workspace/11.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2506224552
Short name	T186
Test name
Test status
Simulation time	93827255 ps
CPU time	1.78 seconds
Started	May 12 01:18:44 PM PDT 24
Finished	May 12 01:18:47 PM PDT 24
Peak memory	200504 kb
Host	smart-6a56dbca-e189-4acc-a666-fc36cd654e0b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506224552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 11.clkmgr_tl_intg_err.2506224552
Directory	/workspace/11.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.300914265
Short name	T873
Test name
Test status
Simulation time	40229648 ps
CPU time	1.35 seconds
Started	May 12 01:18:46 PM PDT 24
Finished	May 12 01:18:48 PM PDT 24
Peak memory	200412 kb
Host	smart-7a9cacb0-6602-457d-a92d-66eb386e4b5b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300914265 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.300914265
Directory	/workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.3420654633
Short name	T103
Test name
Test status
Simulation time	62614888 ps
CPU time	0.94 seconds
Started	May 12 01:18:46 PM PDT 24
Finished	May 12 01:18:47 PM PDT 24
Peak memory	200380 kb
Host	smart-aae4741d-1169-4d74-8333-f6b9c9101515
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420654633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .clkmgr_csr_rw.3420654633
Directory	/workspace/12.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_intr_test.3301011789
Short name	T1000
Test name
Test status
Simulation time	30695771 ps
CPU time	0.67 seconds
Started	May 12 01:18:43 PM PDT 24
Finished	May 12 01:18:44 PM PDT 24
Peak memory	198884 kb
Host	smart-616098b4-1de5-46da-87f4-82c6b66fb5c9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301011789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl kmgr_intr_test.3301011789
Directory	/workspace/12.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.902244277
Short name	T885
Test name
Test status
Simulation time	309194457 ps
CPU time	1.81 seconds
Started	May 12 01:18:45 PM PDT 24
Finished	May 12 01:18:47 PM PDT 24
Peak memory	200532 kb
Host	smart-bf26513a-2cf5-4bda-b495-1777528cafc0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902244277 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 12.clkmgr_same_csr_outstanding.902244277
Directory	/workspace/12.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.106222402
Short name	T145
Test name
Test status
Simulation time	133769995 ps
CPU time	1.38 seconds
Started	May 12 01:18:43 PM PDT 24
Finished	May 12 01:18:45 PM PDT 24
Peak memory	200732 kb
Host	smart-5e37612f-7961-4da5-bde5-409a4e041680
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106222402 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 12.clkmgr_shadow_reg_errors.106222402
Directory	/workspace/12.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.3813641368
Short name	T147
Test name
Test status
Simulation time	300212088 ps
CPU time	2.11 seconds
Started	May 12 01:18:41 PM PDT 24
Finished	May 12 01:18:44 PM PDT 24
Peak memory	209084 kb
Host	smart-30e6563d-41bc-4321-8f4c-cba2bb16e760
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813641368 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.3813641368
Directory	/workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.491034939
Short name	T924
Test name
Test status
Simulation time	73510133 ps
CPU time	2.23 seconds
Started	May 12 01:18:39 PM PDT 24
Finished	May 12 01:18:41 PM PDT 24
Peak memory	200528 kb
Host	smart-ab611d7c-7148-49d0-a241-63370ac1ab4b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491034939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clk mgr_tl_errors.491034939
Directory	/workspace/12.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2811044162
Short name	T121
Test name
Test status
Simulation time	67219936 ps
CPU time	1.6 seconds
Started	May 12 01:18:44 PM PDT 24
Finished	May 12 01:18:46 PM PDT 24
Peak memory	200520 kb
Host	smart-e56e26b7-c724-4ccb-8ffe-6b01adf26461
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811044162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 12.clkmgr_tl_intg_err.2811044162
Directory	/workspace/12.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.583080112
Short name	T861
Test name
Test status
Simulation time	80259478 ps
CPU time	1.44 seconds
Started	May 12 01:18:47 PM PDT 24
Finished	May 12 01:18:49 PM PDT 24
Peak memory	200536 kb
Host	smart-ff8cd04d-ef26-46a4-a180-c1db6f81058b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583080112 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.583080112
Directory	/workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.2715876961
Short name	T986
Test name
Test status
Simulation time	29393839 ps
CPU time	0.85 seconds
Started	May 12 01:18:48 PM PDT 24
Finished	May 12 01:18:49 PM PDT 24
Peak memory	200328 kb
Host	smart-fc915202-4461-43be-9ae0-dff627951006
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715876961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .clkmgr_csr_rw.2715876961
Directory	/workspace/13.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_intr_test.2172677735
Short name	T955
Test name
Test status
Simulation time	10740507 ps
CPU time	0.72 seconds
Started	May 12 01:18:49 PM PDT 24
Finished	May 12 01:18:50 PM PDT 24
Peak memory	198988 kb
Host	smart-f48baa82-d775-46b6-a2e7-68499789b460
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172677735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl kmgr_intr_test.2172677735
Directory	/workspace/13.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.1962254279
Short name	T917
Test name
Test status
Simulation time	48120018 ps
CPU time	1.28 seconds
Started	May 12 01:18:49 PM PDT 24
Finished	May 12 01:18:51 PM PDT 24
Peak memory	200368 kb
Host	smart-2351a3ae-c747-4e69-a5c9-44dfdb778fc8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962254279 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 13.clkmgr_same_csr_outstanding.1962254279
Directory	/workspace/13.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1429744626
Short name	T1001
Test name
Test status
Simulation time	104009374 ps
CPU time	1.39 seconds
Started	May 12 01:18:47 PM PDT 24
Finished	May 12 01:18:49 PM PDT 24
Peak memory	200736 kb
Host	smart-77543eac-56e1-4cf2-adef-593c8e00a6f9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429744626 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 13.clkmgr_shadow_reg_errors.1429744626
Directory	/workspace/13.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.2080367125
Short name	T70
Test name
Test status
Simulation time	156063103 ps
CPU time	1.81 seconds
Started	May 12 01:18:47 PM PDT 24
Finished	May 12 01:18:50 PM PDT 24
Peak memory	201088 kb
Host	smart-ea9c5619-210e-4409-a5ca-d8a131860197
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080367125 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.2080367125
Directory	/workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.908056239
Short name	T876
Test name
Test status
Simulation time	68527011 ps
CPU time	2.47 seconds
Started	May 12 01:18:47 PM PDT 24
Finished	May 12 01:18:51 PM PDT 24
Peak memory	200708 kb
Host	smart-f75039c6-fe00-4937-bb5a-61528517c760
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908056239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clk mgr_tl_errors.908056239
Directory	/workspace/13.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.3697963292
Short name	T893
Test name
Test status
Simulation time	120693601 ps
CPU time	1.76 seconds
Started	May 12 01:18:45 PM PDT 24
Finished	May 12 01:18:47 PM PDT 24
Peak memory	200456 kb
Host	smart-1dc5075c-da33-452a-bddb-abf54319ba22
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697963292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 13.clkmgr_tl_intg_err.3697963292
Directory	/workspace/13.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1728218271
Short name	T922
Test name
Test status
Simulation time	87717665 ps
CPU time	1.39 seconds
Started	May 12 01:18:47 PM PDT 24
Finished	May 12 01:18:49 PM PDT 24
Peak memory	200432 kb
Host	smart-8067142d-438a-4671-b655-8b8c3dc7acc1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728218271 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.1728218271
Directory	/workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.3098596110
Short name	T990
Test name
Test status
Simulation time	34020912 ps
CPU time	0.91 seconds
Started	May 12 01:18:49 PM PDT 24
Finished	May 12 01:18:51 PM PDT 24
Peak memory	200428 kb
Host	smart-2e6f481a-e5ff-4407-a3be-db95720f84f0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098596110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .clkmgr_csr_rw.3098596110
Directory	/workspace/14.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_intr_test.2472072812
Short name	T957
Test name
Test status
Simulation time	43689676 ps
CPU time	0.73 seconds
Started	May 12 01:18:48 PM PDT 24
Finished	May 12 01:18:49 PM PDT 24
Peak memory	198884 kb
Host	smart-a65249e7-de38-42b1-b401-ff9437283add
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472072812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl kmgr_intr_test.2472072812
Directory	/workspace/14.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.3989304207
Short name	T942
Test name
Test status
Simulation time	269813845 ps
CPU time	1.96 seconds
Started	May 12 01:18:46 PM PDT 24
Finished	May 12 01:18:48 PM PDT 24
Peak memory	200592 kb
Host	smart-f001fbb9-ab0d-4f1a-af61-38dbf7f5bc1f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989304207 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 14.clkmgr_same_csr_outstanding.3989304207
Directory	/workspace/14.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.350071576
Short name	T951
Test name
Test status
Simulation time	166328284 ps
CPU time	1.99 seconds
Started	May 12 01:18:48 PM PDT 24
Finished	May 12 01:18:51 PM PDT 24
Peak memory	217220 kb
Host	smart-814bc505-9b28-4b60-800a-0c175124a0c8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350071576 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.350071576
Directory	/workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2859393289
Short name	T927
Test name
Test status
Simulation time	59248256 ps
CPU time	2.57 seconds
Started	May 12 01:18:48 PM PDT 24
Finished	May 12 01:18:51 PM PDT 24
Peak memory	200664 kb
Host	smart-06206c3b-20d5-4b26-8363-229686049870
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859393289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl kmgr_tl_errors.2859393289
Directory	/workspace/14.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.2087389959
Short name	T1008
Test name
Test status
Simulation time	257717089 ps
CPU time	2.17 seconds
Started	May 12 01:18:45 PM PDT 24
Finished	May 12 01:18:48 PM PDT 24
Peak memory	200520 kb
Host	smart-65445514-c633-4d21-bff1-e08989442d4c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087389959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 14.clkmgr_tl_intg_err.2087389959
Directory	/workspace/14.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.2689379103
Short name	T944
Test name
Test status
Simulation time	34141154 ps
CPU time	1.69 seconds
Started	May 12 01:18:52 PM PDT 24
Finished	May 12 01:18:55 PM PDT 24
Peak memory	200624 kb
Host	smart-bfb0db44-16d6-41af-bf64-e801bed3ff0a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689379103 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.2689379103
Directory	/workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.2067228867
Short name	T1005
Test name
Test status
Simulation time	18065214 ps
CPU time	0.87 seconds
Started	May 12 01:18:53 PM PDT 24
Finished	May 12 01:18:55 PM PDT 24
Peak memory	200352 kb
Host	smart-3272de4a-7dde-4e6c-92b7-6189f7a6d595
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067228867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .clkmgr_csr_rw.2067228867
Directory	/workspace/15.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_intr_test.1726836754
Short name	T896
Test name
Test status
Simulation time	28569606 ps
CPU time	0.67 seconds
Started	May 12 01:18:46 PM PDT 24
Finished	May 12 01:18:47 PM PDT 24
Peak memory	198976 kb
Host	smart-421dc8ee-3abe-43d5-a964-bb9d620fe200
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726836754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl kmgr_intr_test.1726836754
Directory	/workspace/15.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.3034936735
Short name	T98
Test name
Test status
Simulation time	42757102 ps
CPU time	1.04 seconds
Started	May 12 01:18:53 PM PDT 24
Finished	May 12 01:18:55 PM PDT 24
Peak memory	200444 kb
Host	smart-b0903111-da1e-45c0-9708-ce83eb80a999
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034936735 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 15.clkmgr_same_csr_outstanding.3034936735
Directory	/workspace/15.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.1471125120
Short name	T76
Test name
Test status
Simulation time	1102642191 ps
CPU time	4.29 seconds
Started	May 12 01:18:49 PM PDT 24
Finished	May 12 01:18:54 PM PDT 24
Peak memory	201016 kb
Host	smart-c1c26e80-e28f-456d-a0af-383cb0074dba
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471125120 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 15.clkmgr_shadow_reg_errors.1471125120
Directory	/workspace/15.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.1265750162
Short name	T149
Test name
Test status
Simulation time	254754464 ps
CPU time	2.78 seconds
Started	May 12 01:18:48 PM PDT 24
Finished	May 12 01:18:51 PM PDT 24
Peak memory	209280 kb
Host	smart-a61c0d93-affd-491d-8a00-9e253476d7b6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265750162 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.1265750162
Directory	/workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.1011417037
Short name	T882
Test name
Test status
Simulation time	185140400 ps
CPU time	1.99 seconds
Started	May 12 01:18:48 PM PDT 24
Finished	May 12 01:18:51 PM PDT 24
Peak memory	200652 kb
Host	smart-e202586c-40f2-4386-a0b5-000731c3d6c4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011417037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl kmgr_tl_errors.1011417037
Directory	/workspace/15.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.4009430385
Short name	T119
Test name
Test status
Simulation time	1910834341 ps
CPU time	7.14 seconds
Started	May 12 01:18:47 PM PDT 24
Finished	May 12 01:18:55 PM PDT 24
Peak memory	200624 kb
Host	smart-92e0f4ca-6bfa-4c99-ac32-ba7a95ca39f6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009430385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 15.clkmgr_tl_intg_err.4009430385
Directory	/workspace/15.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.4218001982
Short name	T993
Test name
Test status
Simulation time	27789371 ps
CPU time	1.38 seconds
Started	May 12 01:18:55 PM PDT 24
Finished	May 12 01:18:56 PM PDT 24
Peak memory	200652 kb
Host	smart-00ac2ac6-61b9-4cee-9e9a-3a7a057a0e35
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218001982 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.4218001982
Directory	/workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.4215349506
Short name	T950
Test name
Test status
Simulation time	53860166 ps
CPU time	0.92 seconds
Started	May 12 01:18:56 PM PDT 24
Finished	May 12 01:18:57 PM PDT 24
Peak memory	200364 kb
Host	smart-43604c8b-6709-4d1c-9486-6093fd9e83a8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215349506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .clkmgr_csr_rw.4215349506
Directory	/workspace/16.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_intr_test.199302623
Short name	T954
Test name
Test status
Simulation time	13770655 ps
CPU time	0.68 seconds
Started	May 12 01:18:52 PM PDT 24
Finished	May 12 01:18:54 PM PDT 24
Peak memory	198848 kb
Host	smart-6a75a4af-8488-4551-a09a-b971945dbbd4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199302623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clk mgr_intr_test.199302623
Directory	/workspace/16.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.887958288
Short name	T901
Test name
Test status
Simulation time	53413534 ps
CPU time	0.98 seconds
Started	May 12 01:18:50 PM PDT 24
Finished	May 12 01:18:52 PM PDT 24
Peak memory	200352 kb
Host	smart-b8bb8abc-f0f6-4cb3-a332-b6de231f5080
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887958288 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 16.clkmgr_same_csr_outstanding.887958288
Directory	/workspace/16.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.475252686
Short name	T150
Test name
Test status
Simulation time	238386159 ps
CPU time	2.11 seconds
Started	May 12 01:18:51 PM PDT 24
Finished	May 12 01:18:54 PM PDT 24
Peak memory	201068 kb
Host	smart-577a80bc-9711-45e1-8958-93ee2fe16e86
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475252686 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 16.clkmgr_shadow_reg_errors.475252686
Directory	/workspace/16.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.756753558
Short name	T913
Test name
Test status
Simulation time	163565304 ps
CPU time	2.02 seconds
Started	May 12 01:18:53 PM PDT 24
Finished	May 12 01:18:56 PM PDT 24
Peak memory	217512 kb
Host	smart-5937e656-8b27-401e-994d-6f11106fd001
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756753558 -assert nopostproc +UVM_TESTNAME =clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.756753558
Directory	/workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.742799714
Short name	T905
Test name
Test status
Simulation time	61333693 ps
CPU time	1.86 seconds
Started	May 12 01:18:54 PM PDT 24
Finished	May 12 01:18:56 PM PDT 24
Peak memory	200696 kb
Host	smart-b1b890ab-f16f-4dd5-8476-d799af8137c3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742799714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clk mgr_tl_errors.742799714
Directory	/workspace/16.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3889249181
Short name	T932
Test name
Test status
Simulation time	42248943 ps
CPU time	1.21 seconds
Started	May 12 01:18:50 PM PDT 24
Finished	May 12 01:18:53 PM PDT 24
Peak memory	200476 kb
Host	smart-64712045-802a-44b3-b9cf-6dd06440038d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889249181 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.3889249181
Directory	/workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.2010663703
Short name	T919
Test name
Test status
Simulation time	23442563 ps
CPU time	0.8 seconds
Started	May 12 01:18:52 PM PDT 24
Finished	May 12 01:18:53 PM PDT 24
Peak memory	200336 kb
Host	smart-e7f41bd1-ad73-4108-a089-da9567acc1b3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010663703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .clkmgr_csr_rw.2010663703
Directory	/workspace/17.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_intr_test.69548085
Short name	T877
Test name
Test status
Simulation time	23130873 ps
CPU time	0.72 seconds
Started	May 12 01:18:53 PM PDT 24
Finished	May 12 01:18:54 PM PDT 24
Peak memory	198888 kb
Host	smart-7dbeea67-7b61-4694-8c1d-37e01b2b9c37
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69548085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ =clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkm gr_intr_test.69548085
Directory	/workspace/17.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.1708013453
Short name	T912
Test name
Test status
Simulation time	58085282 ps
CPU time	1.13 seconds
Started	May 12 01:18:52 PM PDT 24
Finished	May 12 01:18:54 PM PDT 24
Peak memory	200424 kb
Host	smart-e91ddb6f-1626-4b0a-a8c1-a1181821533e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708013453 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 17.clkmgr_same_csr_outstanding.1708013453
Directory	/workspace/17.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.1657821928
Short name	T926
Test name
Test status
Simulation time	109542006 ps
CPU time	1.97 seconds
Started	May 12 01:18:50 PM PDT 24
Finished	May 12 01:18:53 PM PDT 24
Peak memory	201052 kb
Host	smart-05f1167f-e162-4eb6-80db-593f9b673da4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657821928 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 17.clkmgr_shadow_reg_errors.1657821928
Directory	/workspace/17.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.2397112798
Short name	T980
Test name
Test status
Simulation time	171257924 ps
CPU time	2.3 seconds
Started	May 12 01:18:53 PM PDT 24
Finished	May 12 01:18:56 PM PDT 24
Peak memory	201192 kb
Host	smart-3ac6c861-8d50-4909-ae27-5263a1f9e273
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397112798 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.2397112798
Directory	/workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.11595605
Short name	T963
Test name
Test status
Simulation time	52537002 ps
CPU time	1.83 seconds
Started	May 12 01:18:51 PM PDT 24
Finished	May 12 01:18:54 PM PDT 24
Peak memory	200696 kb
Host	smart-f9bd76c7-c86d-486b-8791-8f7171a91aed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11595605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ =clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkm gr_tl_errors.11595605
Directory	/workspace/17.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1233385429
Short name	T120
Test name
Test status
Simulation time	264411797 ps
CPU time	2.91 seconds
Started	May 12 01:18:53 PM PDT 24
Finished	May 12 01:18:57 PM PDT 24
Peak memory	200516 kb
Host	smart-ba1e61f8-3249-4093-ba05-e20a55008787
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233385429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 17.clkmgr_tl_intg_err.1233385429
Directory	/workspace/17.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.1622904594
Short name	T906
Test name
Test status
Simulation time	47878355 ps
CPU time	1.02 seconds
Started	May 12 01:18:52 PM PDT 24
Finished	May 12 01:18:54 PM PDT 24
Peak memory	200484 kb
Host	smart-afd6bf8f-b1a8-4830-8983-3348aa4bfc50
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622904594 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.1622904594
Directory	/workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.2915832024
Short name	T948
Test name
Test status
Simulation time	128167856 ps
CPU time	1.1 seconds
Started	May 12 01:18:55 PM PDT 24
Finished	May 12 01:18:56 PM PDT 24
Peak memory	200364 kb
Host	smart-cc77e456-7a56-449f-a3cf-a5beeb625f8a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915832024 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .clkmgr_csr_rw.2915832024
Directory	/workspace/18.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_intr_test.2937775132
Short name	T923
Test name
Test status
Simulation time	109098580 ps
CPU time	0.88 seconds
Started	May 12 01:18:51 PM PDT 24
Finished	May 12 01:18:52 PM PDT 24
Peak memory	198912 kb
Host	smart-0c01d9ca-b82b-440c-9fcf-47243afb0dd5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937775132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl kmgr_intr_test.2937775132
Directory	/workspace/18.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3268558143
Short name	T99
Test name
Test status
Simulation time	127595580 ps
CPU time	1.6 seconds
Started	May 12 01:18:51 PM PDT 24
Finished	May 12 01:18:54 PM PDT 24
Peak memory	200640 kb
Host	smart-ffec888a-a7d6-4d22-8ab9-058a877158e8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268558143 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 18.clkmgr_same_csr_outstanding.3268558143
Directory	/workspace/18.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.1619763487
Short name	T72
Test name
Test status
Simulation time	148201631 ps
CPU time	1.48 seconds
Started	May 12 01:18:49 PM PDT 24
Finished	May 12 01:18:52 PM PDT 24
Peak memory	200860 kb
Host	smart-0c5518c9-1d98-4ce7-b66c-fc6c04a2c79c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619763487 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 18.clkmgr_shadow_reg_errors.1619763487
Directory	/workspace/18.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.1986222171
Short name	T940
Test name
Test status
Simulation time	77136423 ps
CPU time	1.87 seconds
Started	May 12 01:18:53 PM PDT 24
Finished	May 12 01:18:56 PM PDT 24
Peak memory	201064 kb
Host	smart-d9dd3ea7-4ad8-4b23-b47b-7d17fe6760f6
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986222171 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.1986222171
Directory	/workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.3564882909
Short name	T863
Test name
Test status
Simulation time	78864773 ps
CPU time	1.68 seconds
Started	May 12 01:18:51 PM PDT 24
Finished	May 12 01:18:54 PM PDT 24
Peak memory	200616 kb
Host	smart-cf663940-048b-4d17-955a-0c509101216b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564882909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl kmgr_tl_errors.3564882909
Directory	/workspace/18.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.1293046897
Short name	T184
Test name
Test status
Simulation time	67648344 ps
CPU time	1.76 seconds
Started	May 12 01:18:54 PM PDT 24
Finished	May 12 01:18:56 PM PDT 24
Peak memory	200592 kb
Host	smart-8d2d8899-a2ca-4acf-8e90-6862548c34c5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293046897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 18.clkmgr_tl_intg_err.1293046897
Directory	/workspace/18.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3866507703
Short name	T1003
Test name
Test status
Simulation time	55754618 ps
CPU time	1.66 seconds
Started	May 12 01:18:59 PM PDT 24
Finished	May 12 01:19:01 PM PDT 24
Peak memory	200640 kb
Host	smart-c258ff23-cb1d-4a30-a533-a7d14dde07b9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866507703 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.3866507703
Directory	/workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.524144389
Short name	T970
Test name
Test status
Simulation time	14995718 ps
CPU time	0.74 seconds
Started	May 12 01:18:55 PM PDT 24
Finished	May 12 01:18:56 PM PDT 24
Peak memory	200388 kb
Host	smart-9ab5f1e2-af49-4580-9734-ac676dd227f8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524144389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. clkmgr_csr_rw.524144389
Directory	/workspace/19.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2751840127
Short name	T920
Test name
Test status
Simulation time	28885951 ps
CPU time	0.7 seconds
Started	May 12 01:18:55 PM PDT 24
Finished	May 12 01:18:56 PM PDT 24
Peak memory	198884 kb
Host	smart-a4665acb-d8c4-4889-8ada-272d28120d87
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751840127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl kmgr_intr_test.2751840127
Directory	/workspace/19.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1532562295
Short name	T881
Test name
Test status
Simulation time	63147274 ps
CPU time	1.58 seconds
Started	May 12 01:18:55 PM PDT 24
Finished	May 12 01:18:57 PM PDT 24
Peak memory	200628 kb
Host	smart-595cec24-824a-44a2-84e3-acb12d6f343d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532562295 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 19.clkmgr_same_csr_outstanding.1532562295
Directory	/workspace/19.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2184921792
Short name	T992
Test name
Test status
Simulation time	331442659 ps
CPU time	2.38 seconds
Started	May 12 01:18:58 PM PDT 24
Finished	May 12 01:19:01 PM PDT 24
Peak memory	217260 kb
Host	smart-b0f6dbff-f087-4ca6-9832-1cb5a0dbb456
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184921792 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.2184921792
Directory	/workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.3444544031
Short name	T973
Test name
Test status
Simulation time	108242411 ps
CPU time	2.53 seconds
Started	May 12 01:18:58 PM PDT 24
Finished	May 12 01:19:01 PM PDT 24
Peak memory	200600 kb
Host	smart-299630ec-434e-4cef-9d14-292c5026a998
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444544031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl kmgr_tl_errors.3444544031
Directory	/workspace/19.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.750076099
Short name	T122
Test name
Test status
Simulation time	147074181 ps
CPU time	2.41 seconds
Started	May 12 01:19:02 PM PDT 24
Finished	May 12 01:19:05 PM PDT 24
Peak memory	200628 kb
Host	smart-5eaa15b6-cd1b-4d1d-81fe-4345a086342b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750076099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 19.clkmgr_tl_intg_err.750076099
Directory	/workspace/19.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.3792425139
Short name	T102
Test name
Test status
Simulation time	72763999 ps
CPU time	1.78 seconds
Started	May 12 01:18:26 PM PDT 24
Finished	May 12 01:18:28 PM PDT 24
Peak memory	200608 kb
Host	smart-bbee9833-acaa-4dd0-804b-7243b4c7656d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792425139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_aliasing.3792425139
Directory	/workspace/2.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.2242966645
Short name	T983
Test name
Test status
Simulation time	1009931433 ps
CPU time	6.25 seconds
Started	May 12 01:18:28 PM PDT 24
Finished	May 12 01:18:34 PM PDT 24
Peak memory	200504 kb
Host	smart-92dc1740-670f-4ca8-8dbb-18f30ac56786
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242966645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_bit_bash.2242966645
Directory	/workspace/2.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2765929556
Short name	T860
Test name
Test status
Simulation time	20973372 ps
CPU time	0.77 seconds
Started	May 12 01:18:26 PM PDT 24
Finished	May 12 01:18:27 PM PDT 24
Peak memory	200396 kb
Host	smart-c3fd019d-4fbb-45e2-bc6b-89a3d319d073
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765929556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.clkmgr_csr_hw_reset.2765929556
Directory	/workspace/2.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1905767396
Short name	T969
Test name
Test status
Simulation time	35812662 ps
CPU time	1.1 seconds
Started	May 12 01:18:34 PM PDT 24
Finished	May 12 01:18:35 PM PDT 24
Peak memory	200416 kb
Host	smart-c8a44d62-53d2-4d1c-9546-631dc6ba8632
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905767396 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.1905767396
Directory	/workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.4251822240
Short name	T105
Test name
Test status
Simulation time	27795831 ps
CPU time	0.83 seconds
Started	May 12 01:18:26 PM PDT 24
Finished	May 12 01:18:28 PM PDT 24
Peak memory	200376 kb
Host	smart-c1be6e96-3fe3-4623-b49a-9a3b8c23f3d3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251822240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. clkmgr_csr_rw.4251822240
Directory	/workspace/2.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_intr_test.3932245789
Short name	T961
Test name
Test status
Simulation time	14266266 ps
CPU time	0.73 seconds
Started	May 12 01:18:32 PM PDT 24
Finished	May 12 01:18:33 PM PDT 24
Peak memory	198908 kb
Host	smart-50596435-783f-4884-bad5-991f46d51c27
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932245789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk mgr_intr_test.3932245789
Directory	/workspace/2.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.3088531720
Short name	T956
Test name
Test status
Simulation time	105614836 ps
CPU time	1.61 seconds
Started	May 12 01:18:35 PM PDT 24
Finished	May 12 01:18:37 PM PDT 24
Peak memory	200576 kb
Host	smart-5f567a5a-ed27-4054-a78e-ae9d14ee81fa
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088531720 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.clkmgr_same_csr_outstanding.3088531720
Directory	/workspace/2.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1089836805
Short name	T133
Test name
Test status
Simulation time	596904260 ps
CPU time	2.92 seconds
Started	May 12 01:18:23 PM PDT 24
Finished	May 12 01:18:27 PM PDT 24
Peak memory	201092 kb
Host	smart-1699f505-1801-43cc-8002-dad8c8a812c1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089836805 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.1089836805
Directory	/workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.3172634453
Short name	T941
Test name
Test status
Simulation time	160499753 ps
CPU time	3.02 seconds
Started	May 12 01:18:22 PM PDT 24
Finished	May 12 01:18:26 PM PDT 24
Peak memory	200600 kb
Host	smart-90b7269f-bc6f-468f-b9a1-0ee56fa67243
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172634453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk mgr_tl_errors.3172634453
Directory	/workspace/2.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3505817971
Short name	T117
Test name
Test status
Simulation time	239227362 ps
CPU time	2.98 seconds
Started	May 12 01:18:23 PM PDT 24
Finished	May 12 01:18:27 PM PDT 24
Peak memory	200656 kb
Host	smart-e8f1a9b2-e9f9-4f85-8c0d-0e652f767029
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505817971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 2.clkmgr_tl_intg_err.3505817971
Directory	/workspace/2.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2411801857
Short name	T929
Test name
Test status
Simulation time	14257755 ps
CPU time	0.71 seconds
Started	May 12 01:18:57 PM PDT 24
Finished	May 12 01:18:58 PM PDT 24
Peak memory	198888 kb
Host	smart-749392d6-aec0-4ff8-8311-6ea0ed7d827c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411801857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl kmgr_intr_test.2411801857
Directory	/workspace/20.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.clkmgr_intr_test.3966169256
Short name	T939
Test name
Test status
Simulation time	13142689 ps
CPU time	0.73 seconds
Started	May 12 01:18:55 PM PDT 24
Finished	May 12 01:18:57 PM PDT 24
Peak memory	198832 kb
Host	smart-f336da9d-32b7-4547-8dd7-3721c17f9f9b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966169256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl kmgr_intr_test.3966169256
Directory	/workspace/21.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.clkmgr_intr_test.3494837127
Short name	T897
Test name
Test status
Simulation time	18159492 ps
CPU time	0.78 seconds
Started	May 12 01:18:58 PM PDT 24
Finished	May 12 01:18:59 PM PDT 24
Peak memory	198872 kb
Host	smart-c4500bd8-df71-4280-822e-43e642a99ae4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494837127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl kmgr_intr_test.3494837127
Directory	/workspace/22.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.clkmgr_intr_test.1086022689
Short name	T998
Test name
Test status
Simulation time	21165252 ps
CPU time	0.75 seconds
Started	May 12 01:18:56 PM PDT 24
Finished	May 12 01:18:57 PM PDT 24
Peak memory	198900 kb
Host	smart-42a3b057-4aa8-45ec-a213-4dbceea63a0a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086022689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl kmgr_intr_test.1086022689
Directory	/workspace/23.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.clkmgr_intr_test.3858463274
Short name	T875
Test name
Test status
Simulation time	14252498 ps
CPU time	0.67 seconds
Started	May 12 01:18:57 PM PDT 24
Finished	May 12 01:18:58 PM PDT 24
Peak memory	198804 kb
Host	smart-f92f0d24-3376-4be9-a63b-027a62241015
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858463274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl kmgr_intr_test.3858463274
Directory	/workspace/24.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.clkmgr_intr_test.1225500394
Short name	T894
Test name
Test status
Simulation time	11394335 ps
CPU time	0.66 seconds
Started	May 12 01:18:57 PM PDT 24
Finished	May 12 01:18:58 PM PDT 24
Peak memory	198896 kb
Host	smart-193618e5-008a-4a46-bfb3-8de6844bd1d0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225500394 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.cl kmgr_intr_test.1225500394
Directory	/workspace/25.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.clkmgr_intr_test.2457465034
Short name	T862
Test name
Test status
Simulation time	13460193 ps
CPU time	0.67 seconds
Started	May 12 01:18:56 PM PDT 24
Finished	May 12 01:18:58 PM PDT 24
Peak memory	198772 kb
Host	smart-e58d8bfd-ec12-4d7c-97f9-1f0ed0250fbe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457465034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl kmgr_intr_test.2457465034
Directory	/workspace/26.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.clkmgr_intr_test.3986819407
Short name	T908
Test name
Test status
Simulation time	22480623 ps
CPU time	0.69 seconds
Started	May 12 01:18:57 PM PDT 24
Finished	May 12 01:18:58 PM PDT 24
Peak memory	198896 kb
Host	smart-abb8e103-ed4b-441b-a3d1-4c04b4f34f29
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986819407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl kmgr_intr_test.3986819407
Directory	/workspace/27.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.clkmgr_intr_test.1462034296
Short name	T975
Test name
Test status
Simulation time	15609209 ps
CPU time	0.64 seconds
Started	May 12 01:18:58 PM PDT 24
Finished	May 12 01:18:59 PM PDT 24
Peak memory	198812 kb
Host	smart-bdb9c725-4f01-43ba-abe4-e9e4b4cb32ae
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462034296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl kmgr_intr_test.1462034296
Directory	/workspace/28.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.clkmgr_intr_test.2082871562
Short name	T953
Test name
Test status
Simulation time	20649610 ps
CPU time	0.67 seconds
Started	May 12 01:19:00 PM PDT 24
Finished	May 12 01:19:01 PM PDT 24
Peak memory	198848 kb
Host	smart-e25587b4-ea2c-4ac1-a2d4-dcdb208ca4ff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082871562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl kmgr_intr_test.2082871562
Directory	/workspace/29.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3951562717
Short name	T902
Test name
Test status
Simulation time	114805484 ps
CPU time	1.72 seconds
Started	May 12 01:18:27 PM PDT 24
Finished	May 12 01:18:29 PM PDT 24
Peak memory	200652 kb
Host	smart-d91c7d75-00e7-4cfa-b935-60f0e29051cd
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951562717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_aliasing.3951562717
Directory	/workspace/3.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.765409442
Short name	T904
Test name
Test status
Simulation time	411625524 ps
CPU time	7.44 seconds
Started	May 12 01:18:35 PM PDT 24
Finished	May 12 01:18:43 PM PDT 24
Peak memory	200592 kb
Host	smart-499c5d06-a560-4557-b354-80a378a10016
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765409442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 3.clkmgr_csr_bit_bash.765409442
Directory	/workspace/3.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2925708618
Short name	T935
Test name
Test status
Simulation time	49489405 ps
CPU time	0.83 seconds
Started	May 12 01:18:26 PM PDT 24
Finished	May 12 01:18:27 PM PDT 24
Peak memory	200372 kb
Host	smart-5dbc7877-7025-462f-8109-ab1f00a999d9
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925708618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.clkmgr_csr_hw_reset.2925708618
Directory	/workspace/3.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.83824848
Short name	T865
Test name
Test status
Simulation time	97517102 ps
CPU time	1.49 seconds
Started	May 12 01:18:27 PM PDT 24
Finished	May 12 01:18:29 PM PDT 24
Peak memory	200208 kb
Host	smart-47d77e63-ab51-4b4f-b16e-27519558346c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83824848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.83824848
Directory	/workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.790419862
Short name	T946
Test name
Test status
Simulation time	104632482 ps
CPU time	1.01 seconds
Started	May 12 01:18:25 PM PDT 24
Finished	May 12 01:18:27 PM PDT 24
Peak memory	200372 kb
Host	smart-a4b25bbc-ced5-4840-a72f-7eed5f22a6ea
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790419862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST _SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.c lkmgr_csr_rw.790419862
Directory	/workspace/3.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_intr_test.2489249426
Short name	T928
Test name
Test status
Simulation time	32807998 ps
CPU time	0.73 seconds
Started	May 12 01:18:40 PM PDT 24
Finished	May 12 01:18:41 PM PDT 24
Peak memory	198880 kb
Host	smart-e93a4e4e-6de8-481b-8db5-dca522834e1f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489249426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk mgr_intr_test.2489249426
Directory	/workspace/3.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.402926723
Short name	T883
Test name
Test status
Simulation time	47115784 ps
CPU time	1.4 seconds
Started	May 12 01:18:27 PM PDT 24
Finished	May 12 01:18:29 PM PDT 24
Peak memory	200604 kb
Host	smart-9707817d-973a-4b35-a5a4-3a572eaf635f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402926723 -assert nopostproc +UVM_TESTNAME=clkmgr_b ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 3.clkmgr_same_csr_outstanding.402926723
Directory	/workspace/3.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.765867605
Short name	T148
Test name
Test status
Simulation time	203056385 ps
CPU time	1.74 seconds
Started	May 12 01:18:26 PM PDT 24
Finished	May 12 01:18:28 PM PDT 24
Peak memory	200884 kb
Host	smart-5f6d4252-f169-4104-a5c2-ef505dca5d2e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765867605 -assert nopostproc +UVM_TESTNAME=clkmgr_base _test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.clkmgr_shadow_reg_errors.765867605
Directory	/workspace/3.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.2972398950
Short name	T135
Test name
Test status
Simulation time	55731731 ps
CPU time	1.61 seconds
Started	May 12 01:18:32 PM PDT 24
Finished	May 12 01:18:34 PM PDT 24
Peak memory	201184 kb
Host	smart-10420386-621c-4b85-b06e-1e9deedceb31
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972398950 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.2972398950
Directory	/workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.3676029887
Short name	T921
Test name
Test status
Simulation time	105294542 ps
CPU time	1.74 seconds
Started	May 12 01:18:28 PM PDT 24
Finished	May 12 01:18:30 PM PDT 24
Peak memory	200684 kb
Host	smart-08dd01f2-c5e2-4c82-9924-b93e61f95ba9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676029887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk mgr_tl_errors.3676029887
Directory	/workspace/3.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.2895118627
Short name	T118
Test name
Test status
Simulation time	176579769 ps
CPU time	2.36 seconds
Started	May 12 01:18:27 PM PDT 24
Finished	May 12 01:18:30 PM PDT 24
Peak memory	200592 kb
Host	smart-4c4be0c8-9838-4437-9228-544b5a459117
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895118627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 3.clkmgr_tl_intg_err.2895118627
Directory	/workspace/3.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.clkmgr_intr_test.1142868381
Short name	T972
Test name
Test status
Simulation time	11611632 ps
CPU time	0.67 seconds
Started	May 12 01:18:58 PM PDT 24
Finished	May 12 01:18:59 PM PDT 24
Peak memory	198840 kb
Host	smart-c27e49d2-ff6d-4068-a7b8-05e88d864197
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142868381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl kmgr_intr_test.1142868381
Directory	/workspace/30.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.clkmgr_intr_test.652839900
Short name	T933
Test name
Test status
Simulation time	14601920 ps
CPU time	0.69 seconds
Started	May 12 01:18:58 PM PDT 24
Finished	May 12 01:18:59 PM PDT 24
Peak memory	198896 kb
Host	smart-bd6f4052-d58d-4ec7-824a-89991ed24bed
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652839900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.clk mgr_intr_test.652839900
Directory	/workspace/31.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.clkmgr_intr_test.3148385176
Short name	T886
Test name
Test status
Simulation time	13031826 ps
CPU time	0.69 seconds
Started	May 12 01:18:56 PM PDT 24
Finished	May 12 01:18:57 PM PDT 24
Peak memory	198824 kb
Host	smart-b8f65c8c-c7c9-4694-81ab-c97b8f8710b0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148385176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl kmgr_intr_test.3148385176
Directory	/workspace/32.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.clkmgr_intr_test.2326340413
Short name	T911
Test name
Test status
Simulation time	30247337 ps
CPU time	0.7 seconds
Started	May 12 01:18:58 PM PDT 24
Finished	May 12 01:18:59 PM PDT 24
Peak memory	198696 kb
Host	smart-fb5266d6-f421-45b8-aa62-92399c64a388
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326340413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl kmgr_intr_test.2326340413
Directory	/workspace/33.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.clkmgr_intr_test.3180248013
Short name	T996
Test name
Test status
Simulation time	92220633 ps
CPU time	0.83 seconds
Started	May 12 01:18:55 PM PDT 24
Finished	May 12 01:18:56 PM PDT 24
Peak memory	198880 kb
Host	smart-1d2f8772-76ff-4cb1-8187-2b1ea0bb241c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180248013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl kmgr_intr_test.3180248013
Directory	/workspace/34.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.clkmgr_intr_test.31208728
Short name	T868
Test name
Test status
Simulation time	19340217 ps
CPU time	0.69 seconds
Started	May 12 01:18:57 PM PDT 24
Finished	May 12 01:18:58 PM PDT 24
Peak memory	198804 kb
Host	smart-37edcbd2-4c58-4b9c-888a-d29752d1ced5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31208728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ =clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clkm gr_intr_test.31208728
Directory	/workspace/35.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.clkmgr_intr_test.4228354977
Short name	T925
Test name
Test status
Simulation time	15225491 ps
CPU time	0.7 seconds
Started	May 12 01:18:55 PM PDT 24
Finished	May 12 01:18:56 PM PDT 24
Peak memory	198884 kb
Host	smart-f8977385-c8c9-47a4-80a1-a40421aa86e1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228354977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl kmgr_intr_test.4228354977
Directory	/workspace/36.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.clkmgr_intr_test.1208371708
Short name	T1009
Test name
Test status
Simulation time	20807912 ps
CPU time	0.7 seconds
Started	May 12 01:18:56 PM PDT 24
Finished	May 12 01:18:57 PM PDT 24
Peak memory	198972 kb
Host	smart-534fe07c-98fd-4038-a07f-728232471ac0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208371708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl kmgr_intr_test.1208371708
Directory	/workspace/37.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.clkmgr_intr_test.3674379672
Short name	T960
Test name
Test status
Simulation time	14197316 ps
CPU time	0.67 seconds
Started	May 12 01:18:56 PM PDT 24
Finished	May 12 01:18:58 PM PDT 24
Peak memory	198904 kb
Host	smart-8bfc585d-0319-44a0-9757-a30482eb4565
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674379672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl kmgr_intr_test.3674379672
Directory	/workspace/38.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.clkmgr_intr_test.794582951
Short name	T985
Test name
Test status
Simulation time	40200090 ps
CPU time	0.72 seconds
Started	May 12 01:18:56 PM PDT 24
Finished	May 12 01:18:58 PM PDT 24
Peak memory	198876 kb
Host	smart-89f7f792-b42e-4f0c-99d2-8aab44a9fa36
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794582951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clk mgr_intr_test.794582951
Directory	/workspace/39.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.2285243890
Short name	T994
Test name
Test status
Simulation time	61852783 ps
CPU time	1.2 seconds
Started	May 12 01:18:31 PM PDT 24
Finished	May 12 01:18:33 PM PDT 24
Peak memory	200284 kb
Host	smart-d5d49d7d-dd03-4714-8207-7c165662c4cc
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285243890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.clkmgr_csr_aliasing.2285243890
Directory	/workspace/4.clkmgr_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.2825211995
Short name	T890
Test name
Test status
Simulation time	1008964478 ps
CPU time	9.97 seconds
Started	May 12 01:18:30 PM PDT 24
Finished	May 12 01:18:41 PM PDT 24
Peak memory	200516 kb
Host	smart-3197cb2f-4dfe-42d4-92f8-c5e2f5a7f320
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825211995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.clkmgr_csr_bit_bash.2825211995
Directory	/workspace/4.clkmgr_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1131656811
Short name	T872
Test name
Test status
Simulation time	28390507 ps
CPU time	0.81 seconds
Started	May 12 01:18:27 PM PDT 24
Finished	May 12 01:18:29 PM PDT 24
Peak memory	200032 kb
Host	smart-5bf3ca01-ae11-46c5-8747-f5cfb46e72a7
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131656811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.clkmgr_csr_hw_reset.1131656811
Directory	/workspace/4.clkmgr_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.523127039
Short name	T878
Test name
Test status
Simulation time	34810726 ps
CPU time	1.2 seconds
Started	May 12 01:18:31 PM PDT 24
Finished	May 12 01:18:33 PM PDT 24
Peak memory	200460 kb
Host	smart-30267b35-dd50-4173-8cf4-5cdb132f2d9b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523127039 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.523127039
Directory	/workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.2968581880
Short name	T100
Test name
Test status
Simulation time	42441967 ps
CPU time	0.84 seconds
Started	May 12 01:18:29 PM PDT 24
Finished	May 12 01:18:31 PM PDT 24
Peak memory	200380 kb
Host	smart-f61c0ae9-3887-4af5-9f1f-c948d2be0527
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968581880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. clkmgr_csr_rw.2968581880
Directory	/workspace/4.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_intr_test.4020880663
Short name	T907
Test name
Test status
Simulation time	13666201 ps
CPU time	0.67 seconds
Started	May 12 01:18:28 PM PDT 24
Finished	May 12 01:18:29 PM PDT 24
Peak memory	198976 kb
Host	smart-9424088c-55a9-4f3c-b641-ca7ec29db603
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020880663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk mgr_intr_test.4020880663
Directory	/workspace/4.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3880646992
Short name	T934
Test name
Test status
Simulation time	39165943 ps
CPU time	1.27 seconds
Started	May 12 01:18:29 PM PDT 24
Finished	May 12 01:18:31 PM PDT 24
Peak memory	200564 kb
Host	smart-b2731c6c-2b23-4b9a-b5a6-8d40f95837ae
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880646992 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.clkmgr_same_csr_outstanding.3880646992
Directory	/workspace/4.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.2224630892
Short name	T140
Test name
Test status
Simulation time	125458964 ps
CPU time	2.23 seconds
Started	May 12 01:18:28 PM PDT 24
Finished	May 12 01:18:31 PM PDT 24
Peak memory	209156 kb
Host	smart-30e56af5-b40b-4a30-b183-d9daced9006a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224630892 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 4.clkmgr_shadow_reg_errors.2224630892
Directory	/workspace/4.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.4211021116
Short name	T144
Test name
Test status
Simulation time	159916436 ps
CPU time	1.84 seconds
Started	May 12 01:18:24 PM PDT 24
Finished	May 12 01:18:27 PM PDT 24
Peak memory	209264 kb
Host	smart-0baa8514-21d7-4a71-b241-6de697c26f09
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211021116 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.4211021116
Directory	/workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.2970227318
Short name	T967
Test name
Test status
Simulation time	110284790 ps
CPU time	1.93 seconds
Started	May 12 01:18:27 PM PDT 24
Finished	May 12 01:18:29 PM PDT 24
Peak memory	200652 kb
Host	smart-1be05121-6e03-4936-bf68-ac367da78ca4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970227318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk mgr_tl_errors.2970227318
Directory	/workspace/4.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1806740628
Short name	T114
Test name
Test status
Simulation time	180175367 ps
CPU time	1.98 seconds
Started	May 12 01:18:32 PM PDT 24
Finished	May 12 01:18:34 PM PDT 24
Peak memory	200576 kb
Host	smart-d139b75c-53c6-4aca-9289-ccf21c4c360a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806740628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 4.clkmgr_tl_intg_err.1806740628
Directory	/workspace/4.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.clkmgr_intr_test.4105232666
Short name	T997
Test name
Test status
Simulation time	20250803 ps
CPU time	0.69 seconds
Started	May 12 01:18:56 PM PDT 24
Finished	May 12 01:18:57 PM PDT 24
Peak memory	198876 kb
Host	smart-cc162374-30c5-457a-b2c1-24342ab71fed
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105232666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl kmgr_intr_test.4105232666
Directory	/workspace/40.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.clkmgr_intr_test.1490219843
Short name	T999
Test name
Test status
Simulation time	14056271 ps
CPU time	0.74 seconds
Started	May 12 01:19:02 PM PDT 24
Finished	May 12 01:19:04 PM PDT 24
Peak memory	198912 kb
Host	smart-4d2c3263-e795-4ce1-bdb9-4dc1840fcf1b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490219843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl kmgr_intr_test.1490219843
Directory	/workspace/41.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.clkmgr_intr_test.2057048632
Short name	T900
Test name
Test status
Simulation time	24201904 ps
CPU time	0.69 seconds
Started	May 12 01:19:02 PM PDT 24
Finished	May 12 01:19:04 PM PDT 24
Peak memory	199060 kb
Host	smart-49945ee8-08dc-430e-acf7-f6159a9422c8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057048632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl kmgr_intr_test.2057048632
Directory	/workspace/42.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1833470404
Short name	T962
Test name
Test status
Simulation time	13902127 ps
CPU time	0.66 seconds
Started	May 12 01:19:01 PM PDT 24
Finished	May 12 01:19:02 PM PDT 24
Peak memory	198772 kb
Host	smart-778a850b-4065-4eda-961c-706166f9ef7e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833470404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl kmgr_intr_test.1833470404
Directory	/workspace/43.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.clkmgr_intr_test.1064786944
Short name	T936
Test name
Test status
Simulation time	14734871 ps
CPU time	0.74 seconds
Started	May 12 01:19:05 PM PDT 24
Finished	May 12 01:19:06 PM PDT 24
Peak memory	198896 kb
Host	smart-031ec5f8-3d76-40a3-8108-67df995db469
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064786944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl kmgr_intr_test.1064786944
Directory	/workspace/44.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.clkmgr_intr_test.4134372664
Short name	T898
Test name
Test status
Simulation time	12462562 ps
CPU time	0.69 seconds
Started	May 12 01:19:03 PM PDT 24
Finished	May 12 01:19:04 PM PDT 24
Peak memory	198892 kb
Host	smart-e4f5417f-1462-4cdf-8708-67d838018bbd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134372664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl kmgr_intr_test.4134372664
Directory	/workspace/45.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.clkmgr_intr_test.3742900762
Short name	T871
Test name
Test status
Simulation time	11844497 ps
CPU time	0.68 seconds
Started	May 12 01:19:02 PM PDT 24
Finished	May 12 01:19:03 PM PDT 24
Peak memory	198980 kb
Host	smart-ddf2abdc-3006-47a7-8ede-c98aa913684b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742900762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl kmgr_intr_test.3742900762
Directory	/workspace/46.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.clkmgr_intr_test.2820385556
Short name	T947
Test name
Test status
Simulation time	133872126 ps
CPU time	0.93 seconds
Started	May 12 01:19:04 PM PDT 24
Finished	May 12 01:19:05 PM PDT 24
Peak memory	198812 kb
Host	smart-08a9ff61-6b96-4649-97bf-bc30de01430d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820385556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl kmgr_intr_test.2820385556
Directory	/workspace/47.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.clkmgr_intr_test.2955020365
Short name	T866
Test name
Test status
Simulation time	13389791 ps
CPU time	0.67 seconds
Started	May 12 01:19:01 PM PDT 24
Finished	May 12 01:19:02 PM PDT 24
Peak memory	198912 kb
Host	smart-cd0c8e15-21e9-4da0-b6d6-e0ebf35d3ff7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955020365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl kmgr_intr_test.2955020365
Directory	/workspace/48.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2460792656
Short name	T982
Test name
Test status
Simulation time	10584288 ps
CPU time	0.69 seconds
Started	May 12 01:19:01 PM PDT 24
Finished	May 12 01:19:02 PM PDT 24
Peak memory	198884 kb
Host	smart-197cd47b-2943-4477-afa3-ac0d88f58fa9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460792656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl kmgr_intr_test.2460792656
Directory	/workspace/49.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1650052955
Short name	T959
Test name
Test status
Simulation time	38697290 ps
CPU time	1.78 seconds
Started	May 12 01:18:30 PM PDT 24
Finished	May 12 01:18:32 PM PDT 24
Peak memory	208772 kb
Host	smart-5ae8cae1-9240-4ac6-97b2-ad8b3cd0fd38
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650052955 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.1650052955
Directory	/workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.3391568005
Short name	T988
Test name
Test status
Simulation time	14074409 ps
CPU time	0.79 seconds
Started	May 12 01:18:30 PM PDT 24
Finished	May 12 01:18:31 PM PDT 24
Peak memory	200620 kb
Host	smart-94ebb31e-f2ae-43f3-b22f-c3b4b9b210c2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391568005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. clkmgr_csr_rw.3391568005
Directory	/workspace/5.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_intr_test.1831621091
Short name	T978
Test name
Test status
Simulation time	15520004 ps
CPU time	0.66 seconds
Started	May 12 01:18:31 PM PDT 24
Finished	May 12 01:18:32 PM PDT 24
Peak memory	198888 kb
Host	smart-c7f39d1d-ae54-4339-8a88-6a9158f76375
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831621091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk mgr_intr_test.1831621091
Directory	/workspace/5.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.3029881186
Short name	T101
Test name
Test status
Simulation time	33212254 ps
CPU time	1.04 seconds
Started	May 12 01:18:35 PM PDT 24
Finished	May 12 01:18:37 PM PDT 24
Peak memory	200388 kb
Host	smart-7441b7d3-6dbc-4c50-b714-6bc06a18d415
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029881186 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.clkmgr_same_csr_outstanding.3029881186
Directory	/workspace/5.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.3653255229
Short name	T146
Test name
Test status
Simulation time	319580838 ps
CPU time	2.42 seconds
Started	May 12 01:18:33 PM PDT 24
Finished	May 12 01:18:36 PM PDT 24
Peak memory	201068 kb
Host	smart-7178bdbb-14eb-4847-a3f7-5581aec6a005
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653255229 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.clkmgr_shadow_reg_errors.3653255229
Directory	/workspace/5.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.4163842910
Short name	T1007
Test name
Test status
Simulation time	137549060 ps
CPU time	3.44 seconds
Started	May 12 01:18:33 PM PDT 24
Finished	May 12 01:18:36 PM PDT 24
Peak memory	200640 kb
Host	smart-ec5f52a0-96c6-4f08-884c-88e3fa53a4c9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163842910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk mgr_tl_errors.4163842910
Directory	/workspace/5.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2759695320
Short name	T965
Test name
Test status
Simulation time	69206592 ps
CPU time	1.43 seconds
Started	May 12 01:18:34 PM PDT 24
Finished	May 12 01:18:36 PM PDT 24
Peak memory	200440 kb
Host	smart-b6946fe2-511e-4ed1-9416-5ec698ddcb28
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759695320 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.2759695320
Directory	/workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.2554397477
Short name	T979
Test name
Test status
Simulation time	20439055 ps
CPU time	0.87 seconds
Started	May 12 01:18:30 PM PDT 24
Finished	May 12 01:18:31 PM PDT 24
Peak memory	200312 kb
Host	smart-60bb209d-c9ca-4628-92a7-f8862d725f50
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554397477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. clkmgr_csr_rw.2554397477
Directory	/workspace/6.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3406607871
Short name	T1006
Test name
Test status
Simulation time	12754480 ps
CPU time	0.67 seconds
Started	May 12 01:18:32 PM PDT 24
Finished	May 12 01:18:33 PM PDT 24
Peak memory	198896 kb
Host	smart-74cba50a-8825-495e-a249-723aee7c03e3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406607871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk mgr_intr_test.3406607871
Directory	/workspace/6.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.4288067016
Short name	T884
Test name
Test status
Simulation time	90438287 ps
CPU time	1.38 seconds
Started	May 12 01:18:33 PM PDT 24
Finished	May 12 01:18:35 PM PDT 24
Peak memory	200588 kb
Host	smart-8691db79-2b9e-474e-a7be-29136029e48c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288067016 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.clkmgr_same_csr_outstanding.4288067016
Directory	/workspace/6.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.3350750583
Short name	T152
Test name
Test status
Simulation time	277724140 ps
CPU time	2.28 seconds
Started	May 12 01:18:33 PM PDT 24
Finished	May 12 01:18:36 PM PDT 24
Peak memory	200956 kb
Host	smart-44d606aa-b61b-45f7-af35-de056d87f068
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350750583 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 6.clkmgr_shadow_reg_errors.3350750583
Directory	/workspace/6.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.2037429593
Short name	T989
Test name
Test status
Simulation time	73082251 ps
CPU time	1.82 seconds
Started	May 12 01:18:29 PM PDT 24
Finished	May 12 01:18:31 PM PDT 24
Peak memory	209272 kb
Host	smart-b86af217-da57-4cb7-a37f-febb99c2cd7f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037429593 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.2037429593
Directory	/workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.556891074
Short name	T930
Test name
Test status
Simulation time	458470825 ps
CPU time	4.31 seconds
Started	May 12 01:18:31 PM PDT 24
Finished	May 12 01:18:36 PM PDT 24
Peak memory	200668 kb
Host	smart-6e39a27d-5207-4417-9963-5ab0672708ed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556891074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkm gr_tl_errors.556891074
Directory	/workspace/6.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1581071347
Short name	T914
Test name
Test status
Simulation time	93319720 ps
CPU time	1.81 seconds
Started	May 12 01:18:35 PM PDT 24
Finished	May 12 01:18:38 PM PDT 24
Peak memory	200580 kb
Host	smart-513d2cd3-765c-4d7e-8f0d-a314f89fa9bb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581071347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 6.clkmgr_tl_intg_err.1581071347
Directory	/workspace/6.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1300012485
Short name	T958
Test name
Test status
Simulation time	112996856 ps
CPU time	1.47 seconds
Started	May 12 01:18:38 PM PDT 24
Finished	May 12 01:18:40 PM PDT 24
Peak memory	200360 kb
Host	smart-7ecac442-1370-409a-bb89-56628f00636d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300012485 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.1300012485
Directory	/workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.3150231974
Short name	T918
Test name
Test status
Simulation time	30401742 ps
CPU time	0.78 seconds
Started	May 12 01:18:30 PM PDT 24
Finished	May 12 01:18:32 PM PDT 24
Peak memory	200308 kb
Host	smart-70b5ee73-cad3-4563-86f7-d0c18e1446cb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150231974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. clkmgr_csr_rw.3150231974
Directory	/workspace/7.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3407051887
Short name	T867
Test name
Test status
Simulation time	15092847 ps
CPU time	0.68 seconds
Started	May 12 01:18:30 PM PDT 24
Finished	May 12 01:18:31 PM PDT 24
Peak memory	198812 kb
Host	smart-02d77a41-dfea-4f35-8ad7-cb47aee977b1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407051887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk mgr_intr_test.3407051887
Directory	/workspace/7.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.54190758
Short name	T938
Test name
Test status
Simulation time	65848230 ps
CPU time	1.02 seconds
Started	May 12 01:18:35 PM PDT 24
Finished	May 12 01:18:37 PM PDT 24
Peak memory	200364 kb
Host	smart-e7342b9e-bbf9-4e5c-8820-0be24a471cb9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54190758 -assert nopostproc +UVM_TESTNAME=clkmgr_ba se_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.clkmgr_same_csr_outstanding.54190758
Directory	/workspace/7.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.3719079853
Short name	T71
Test name
Test status
Simulation time	614046069 ps
CPU time	3.04 seconds
Started	May 12 01:18:35 PM PDT 24
Finished	May 12 01:18:38 PM PDT 24
Peak memory	201092 kb
Host	smart-711ddede-7f0c-4089-8e24-e8e42ce0e92e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719079853 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 7.clkmgr_shadow_reg_errors.3719079853
Directory	/workspace/7.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.2158820338
Short name	T141
Test name
Test status
Simulation time	57515152 ps
CPU time	1.51 seconds
Started	May 12 01:18:30 PM PDT 24
Finished	May 12 01:18:33 PM PDT 24
Peak memory	209192 kb
Host	smart-02fc9956-3514-4050-82bf-42764fc53279
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158820338 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.2158820338
Directory	/workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.605186363
Short name	T964
Test name
Test status
Simulation time	1555570730 ps
CPU time	7.4 seconds
Started	May 12 01:18:32 PM PDT 24
Finished	May 12 01:18:40 PM PDT 24
Peak memory	200588 kb
Host	smart-51f404de-8baf-445e-8ec8-b244f7094096
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605186363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkm gr_tl_errors.605186363
Directory	/workspace/7.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2596057301
Short name	T899
Test name
Test status
Simulation time	94248264 ps
CPU time	1.39 seconds
Started	May 12 01:18:37 PM PDT 24
Finished	May 12 01:18:39 PM PDT 24
Peak memory	200448 kb
Host	smart-e4a8df80-b1b4-4e7e-a7f4-bbf21a943123
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596057301 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.2596057301
Directory	/workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3232094530
Short name	T966
Test name
Test status
Simulation time	20675067 ps
CPU time	0.82 seconds
Started	May 12 01:18:37 PM PDT 24
Finished	May 12 01:18:38 PM PDT 24
Peak memory	200384 kb
Host	smart-89db556a-61fb-46a4-b1e7-0f8022d451a2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232094530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. clkmgr_csr_rw.3232094530
Directory	/workspace/8.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_intr_test.2791139491
Short name	T916
Test name
Test status
Simulation time	19424246 ps
CPU time	0.7 seconds
Started	May 12 01:18:37 PM PDT 24
Finished	May 12 01:18:39 PM PDT 24
Peak memory	198892 kb
Host	smart-868fb93b-c10b-4234-87fe-6657eb6d220d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791139491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk mgr_intr_test.2791139491
Directory	/workspace/8.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.2955544105
Short name	T984
Test name
Test status
Simulation time	173346434 ps
CPU time	1.57 seconds
Started	May 12 01:18:37 PM PDT 24
Finished	May 12 01:18:39 PM PDT 24
Peak memory	200684 kb
Host	smart-eb978d93-ff81-41c1-b3a4-c830f1a9398d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955544105 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.clkmgr_same_csr_outstanding.2955544105
Directory	/workspace/8.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.4091901657
Short name	T73
Test name
Test status
Simulation time	336246790 ps
CPU time	2.38 seconds
Started	May 12 01:18:37 PM PDT 24
Finished	May 12 01:18:39 PM PDT 24
Peak memory	201092 kb
Host	smart-5d436238-12d4-463a-8492-be3934082743
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091901657 -assert nopostproc +UVM_TESTNAME=clkmgr_bas e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 8.clkmgr_shadow_reg_errors.4091901657
Directory	/workspace/8.clkmgr_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.1104912511
Short name	T903
Test name
Test status
Simulation time	186177802 ps
CPU time	1.8 seconds
Started	May 12 01:18:38 PM PDT 24
Finished	May 12 01:18:40 PM PDT 24
Peak memory	200632 kb
Host	smart-68db4f6e-763e-40da-9eb1-0c1e57d1785c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104912511 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.1104912511
Directory	/workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.1523133732
Short name	T915
Test name
Test status
Simulation time	448181133 ps
CPU time	3.39 seconds
Started	May 12 01:18:35 PM PDT 24
Finished	May 12 01:18:39 PM PDT 24
Peak memory	200688 kb
Host	smart-5daa07fe-90f9-4578-bb9a-7886c9117fe7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523133732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk mgr_tl_errors.1523133732
Directory	/workspace/8.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.648057580
Short name	T115
Test name
Test status
Simulation time	111520176 ps
CPU time	1.77 seconds
Started	May 12 01:18:38 PM PDT 24
Finished	May 12 01:18:40 PM PDT 24
Peak memory	200648 kb
Host	smart-9e53427a-c0ce-42e9-8cf3-ee4e9538093f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648057580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 8.clkmgr_tl_intg_err.648057580
Directory	/workspace/8.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.3163989944
Short name	T889
Test name
Test status
Simulation time	17115996 ps
CPU time	0.92 seconds
Started	May 12 01:18:41 PM PDT 24
Finished	May 12 01:18:43 PM PDT 24
Peak memory	200384 kb
Host	smart-60be6c2b-0454-4920-a71b-124b1adbbee2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163989944 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.3163989944
Directory	/workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.2730798141
Short name	T937
Test name
Test status
Simulation time	23681714 ps
CPU time	0.8 seconds
Started	May 12 01:18:42 PM PDT 24
Finished	May 12 01:18:43 PM PDT 24
Peak memory	200372 kb
Host	smart-690f13f2-122e-4f03-a879-4de89ad02e0b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730798141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. clkmgr_csr_rw.2730798141
Directory	/workspace/9.clkmgr_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_intr_test.3912181687
Short name	T870
Test name
Test status
Simulation time	19761180 ps
CPU time	0.69 seconds
Started	May 12 01:18:36 PM PDT 24
Finished	May 12 01:18:37 PM PDT 24
Peak memory	198852 kb
Host	smart-a57f2c50-1ce3-4efc-bd8d-ab00a31e1be7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912181687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk mgr_intr_test.3912181687
Directory	/workspace/9.clkmgr_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.2130286520
Short name	T104
Test name
Test status
Simulation time	106553622 ps
CPU time	1.18 seconds
Started	May 12 01:18:41 PM PDT 24
Finished	May 12 01:18:43 PM PDT 24
Peak memory	200416 kb
Host	smart-c12f2a9d-75e6-47ed-a65a-5538c6bda4f4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130286520 -assert nopostproc +UVM_TESTNAME=clkmgr_ base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.clkmgr_same_csr_outstanding.2130286520
Directory	/workspace/9.clkmgr_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.1407975097
Short name	T143
Test name
Test status
Simulation time	68350670 ps
CPU time	1.67 seconds
Started	May 12 01:18:38 PM PDT 24
Finished	May 12 01:18:40 PM PDT 24
Peak memory	209216 kb
Host	smart-48c0d6e1-227a-4e4a-82e7-c59e83677587
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407975097 -assert nopostproc +UVM_TESTNAM E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.1407975097
Directory	/workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.3603705804
Short name	T880
Test name
Test status
Simulation time	232299794 ps
CPU time	3.1 seconds
Started	May 12 01:18:37 PM PDT 24
Finished	May 12 01:18:41 PM PDT 24
Peak memory	200924 kb
Host	smart-5f4a8e42-bd3f-46cf-b987-67eb2131a46e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603705804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk mgr_tl_errors.3603705804
Directory	/workspace/9.clkmgr_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.3395072546
Short name	T123
Test name
Test status
Simulation time	147768946 ps
CPU time	1.86 seconds
Started	May 12 01:18:39 PM PDT 24
Finished	May 12 01:18:41 PM PDT 24
Peak memory	200616 kb
Host	smart-d30b55b6-e8f1-40f2-a5a5-f659b7e9a980
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395072546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 9.clkmgr_tl_intg_err.3395072546
Directory	/workspace/9.clkmgr_tl_intg_err/latest

Test location	/workspace/coverage/default/0.clkmgr_alert_test.4278789917
Short name	T810
Test name
Test status
Simulation time	14592441 ps
CPU time	0.73 seconds
Started	May 12 01:21:15 PM PDT 24
Finished	May 12 01:21:16 PM PDT 24
Peak memory	200596 kb
Host	smart-c49a3ac6-fdb0-4fb0-b0ae-d0a75293871b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278789917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm gr_alert_test.4278789917
Directory	/workspace/0.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/0.clkmgr_clk_status.3834993969
Short name	T857
Test name
Test status
Simulation time	13861689 ps
CPU time	0.68 seconds
Started	May 12 01:21:15 PM PDT 24
Finished	May 12 01:21:16 PM PDT 24
Peak memory	200236 kb
Host	smart-14e4298d-76b7-4b07-948c-88c474075cd5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834993969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.3834993969
Directory	/workspace/0.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/0.clkmgr_div_intersig_mubi.2350416081
Short name	T305
Test name
Test status
Simulation time	55882589 ps
CPU time	0.87 seconds
Started	May 12 01:21:14 PM PDT 24
Finished	May 12 01:21:15 PM PDT 24
Peak memory	200444 kb
Host	smart-65d55d77-9c22-4bc0-a3c1-348b4920dbfb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350416081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_div_intersig_mubi.2350416081
Directory	/workspace/0.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_extclk.857596844
Short name	T592
Test name
Test status
Simulation time	85867261 ps
CPU time	0.94 seconds
Started	May 12 01:21:09 PM PDT 24
Finished	May 12 01:21:11 PM PDT 24
Peak memory	200480 kb
Host	smart-3e0f8886-d229-4239-afd8-4555b5bd2b8c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857596844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.857596844
Directory	/workspace/0.clkmgr_extclk/latest

Test location	/workspace/coverage/default/0.clkmgr_frequency.3571636203
Short name	T304
Test name
Test status
Simulation time	1399054405 ps
CPU time	10.69 seconds
Started	May 12 01:21:07 PM PDT 24
Finished	May 12 01:21:18 PM PDT 24
Peak memory	200520 kb
Host	smart-0c571b7f-8b7f-444f-ab54-a9f06a3727da
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571636203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.3571636203
Directory	/workspace/0.clkmgr_frequency/latest

Test location	/workspace/coverage/default/0.clkmgr_frequency_timeout.2948978543
Short name	T346
Test name
Test status
Simulation time	1214291209 ps
CPU time	8.56 seconds
Started	May 12 01:21:09 PM PDT 24
Finished	May 12 01:21:18 PM PDT 24
Peak memory	200572 kb
Host	smart-c44f9e00-d73a-421c-bcb3-2ea664154999
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948978543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti meout.2948978543
Directory	/workspace/0.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/0.clkmgr_idle_intersig_mubi.969240854
Short name	T660
Test name
Test status
Simulation time	66207497 ps
CPU time	0.89 seconds
Started	May 12 01:21:15 PM PDT 24
Finished	May 12 01:21:17 PM PDT 24
Peak memory	200504 kb
Host	smart-f4f8e7df-5a1a-4eb8-8a38-b761d4517b9a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969240854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .clkmgr_idle_intersig_mubi.969240854
Directory	/workspace/0.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.1994761632
Short name	T195
Test name
Test status
Simulation time	231745110 ps
CPU time	1.35 seconds
Started	May 12 01:21:16 PM PDT 24
Finished	May 12 01:21:18 PM PDT 24
Peak memory	200476 kb
Host	smart-da141ead-30c8-4c4c-9a7c-f6fd96269cc6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994761632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.clkmgr_lc_clk_byp_req_intersig_mubi.1994761632
Directory	/workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.3704950436
Short name	T266
Test name
Test status
Simulation time	38218761 ps
CPU time	0.77 seconds
Started	May 12 01:21:14 PM PDT 24
Finished	May 12 01:21:16 PM PDT 24
Peak memory	200532 kb
Host	smart-e69049f7-76f8-40a3-9cf7-75e9c92febda
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704950436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.clkmgr_lc_ctrl_intersig_mubi.3704950436
Directory	/workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/0.clkmgr_peri.2850248067
Short name	T209
Test name
Test status
Simulation time	14778647 ps
CPU time	0.73 seconds
Started	May 12 01:21:08 PM PDT 24
Finished	May 12 01:21:09 PM PDT 24
Peak memory	200260 kb
Host	smart-28c2b20b-4ac1-49e7-9cc1-0b7c71843599
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850248067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.2850248067
Directory	/workspace/0.clkmgr_peri/latest

Test location	/workspace/coverage/default/0.clkmgr_regwen.31170660
Short name	T480
Test name
Test status
Simulation time	397556486 ps
CPU time	1.81 seconds
Started	May 12 01:21:14 PM PDT 24
Finished	May 12 01:21:17 PM PDT 24
Peak memory	200424 kb
Host	smart-82897407-2eed-4a7f-a283-960a6bfa3e36
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31170660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.31170660
Directory	/workspace/0.clkmgr_regwen/latest

Test location	/workspace/coverage/default/0.clkmgr_sec_cm.600221018
Short name	T59
Test name
Test status
Simulation time	306889983 ps
CPU time	2.24 seconds
Started	May 12 01:21:15 PM PDT 24
Finished	May 12 01:21:18 PM PDT 24
Peak memory	215920 kb
Host	smart-c7fce3c6-7f7b-4146-b3dc-cdb1188b8870
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600221018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr _sec_cm.600221018
Directory	/workspace/0.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/0.clkmgr_smoke.526761868
Short name	T315
Test name
Test status
Simulation time	20941630 ps
CPU time	0.84 seconds
Started	May 12 01:21:08 PM PDT 24
Finished	May 12 01:21:10 PM PDT 24
Peak memory	200524 kb
Host	smart-363f2511-e09e-459e-9db4-5f3e370650ce
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526761868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.526761868
Directory	/workspace/0.clkmgr_smoke/latest

Test location	/workspace/coverage/default/0.clkmgr_stress_all.221685037
Short name	T622
Test name
Test status
Simulation time	1277872812 ps
CPU time	9.84 seconds
Started	May 12 01:21:15 PM PDT 24
Finished	May 12 01:21:26 PM PDT 24
Peak memory	200852 kb
Host	smart-0e2487a5-aeec-42be-a72a-712c19ecec29
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221685037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all.221685037
Directory	/workspace/0.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/0.clkmgr_stress_all_with_rand_reset.309978214
Short name	T414
Test name
Test status
Simulation time	39196364689 ps
CPU time	433.78 seconds
Started	May 12 01:21:14 PM PDT 24
Finished	May 12 01:28:29 PM PDT 24
Peak memory	209192 kb
Host	smart-27b2eb5a-3fc9-4878-9a98-bdb4c4746c8d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=309978214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.309978214
Directory	/workspace/0.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/0.clkmgr_trans.227740036
Short name	T704
Test name
Test status
Simulation time	19724811 ps
CPU time	0.87 seconds
Started	May 12 01:21:15 PM PDT 24
Finished	May 12 01:21:17 PM PDT 24
Peak memory	200452 kb
Host	smart-693e2b16-2971-4643-b3cf-932673a1d742
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227740036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.227740036
Directory	/workspace/0.clkmgr_trans/latest

Test location	/workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.722170327
Short name	T551
Test name
Test status
Simulation time	29901465 ps
CPU time	0.92 seconds
Started	May 12 01:21:16 PM PDT 24
Finished	May 12 01:21:17 PM PDT 24
Peak memory	200532 kb
Host	smart-ff0529c8-e9a9-4e1b-aa47-12daffdb22d6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722170327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_handshake_intersig_mubi.722170327
Directory	/workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_clk_status.671062216
Short name	T306
Test name
Test status
Simulation time	41282350 ps
CPU time	0.76 seconds
Started	May 12 01:21:17 PM PDT 24
Finished	May 12 01:21:18 PM PDT 24
Peak memory	199528 kb
Host	smart-d6c26fa2-1b08-4659-ad5e-28a6b3955518
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671062216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.671062216
Directory	/workspace/1.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/1.clkmgr_div_intersig_mubi.3369028247
Short name	T68
Test name
Test status
Simulation time	55845092 ps
CPU time	0.91 seconds
Started	May 12 01:21:18 PM PDT 24
Finished	May 12 01:21:20 PM PDT 24
Peak memory	200504 kb
Host	smart-0bb1fbe2-13ad-44b4-89c0-0f05a9237726
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369028247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_div_intersig_mubi.3369028247
Directory	/workspace/1.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_extclk.512420266
Short name	T701
Test name
Test status
Simulation time	216986384 ps
CPU time	1.35 seconds
Started	May 12 01:21:14 PM PDT 24
Finished	May 12 01:21:16 PM PDT 24
Peak memory	200480 kb
Host	smart-ef442c5e-a29c-47ee-885b-628caefdab0a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512420266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.512420266
Directory	/workspace/1.clkmgr_extclk/latest

Test location	/workspace/coverage/default/1.clkmgr_frequency.2630559651
Short name	T15
Test name
Test status
Simulation time	2810418766 ps
CPU time	10.49 seconds
Started	May 12 01:21:15 PM PDT 24
Finished	May 12 01:21:26 PM PDT 24
Peak memory	200796 kb
Host	smart-bb33bc10-ade1-4478-83fb-ab597f1cd176
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630559651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.2630559651
Directory	/workspace/1.clkmgr_frequency/latest

Test location	/workspace/coverage/default/1.clkmgr_frequency_timeout.1737413659
Short name	T218
Test name
Test status
Simulation time	409853018 ps
CPU time	2.09 seconds
Started	May 12 01:21:17 PM PDT 24
Finished	May 12 01:21:19 PM PDT 24
Peak memory	200584 kb
Host	smart-e869eb7d-edf4-488f-8f7b-ec6153abe1f2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737413659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti meout.1737413659
Directory	/workspace/1.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/1.clkmgr_idle_intersig_mubi.3059131792
Short name	T299
Test name
Test status
Simulation time	30238721 ps
CPU time	0.96 seconds
Started	May 12 01:21:19 PM PDT 24
Finished	May 12 01:21:20 PM PDT 24
Peak memory	200644 kb
Host	smart-c5bf3a86-d6c9-43fa-8af7-940b4c22603c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059131792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_idle_intersig_mubi.3059131792
Directory	/workspace/1.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.1234051882
Short name	T539
Test name
Test status
Simulation time	26761761 ps
CPU time	0.87 seconds
Started	May 12 01:21:18 PM PDT 24
Finished	May 12 01:21:19 PM PDT 24
Peak memory	200504 kb
Host	smart-46477dc4-7f8b-412d-a36c-7825813368cf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234051882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.clkmgr_lc_clk_byp_req_intersig_mubi.1234051882
Directory	/workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.1507605009
Short name	T232
Test name
Test status
Simulation time	196444818 ps
CPU time	1.21 seconds
Started	May 12 01:21:18 PM PDT 24
Finished	May 12 01:21:20 PM PDT 24
Peak memory	200500 kb
Host	smart-50756b8c-b958-46b7-a378-211bd8597f60
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507605009 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.clkmgr_lc_ctrl_intersig_mubi.1507605009
Directory	/workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/1.clkmgr_peri.3104479108
Short name	T503
Test name
Test status
Simulation time	16711572 ps
CPU time	0.77 seconds
Started	May 12 01:21:17 PM PDT 24
Finished	May 12 01:21:18 PM PDT 24
Peak memory	200232 kb
Host	smart-421b83d8-085b-412b-a7a7-f28af6b79b30
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104479108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.3104479108
Directory	/workspace/1.clkmgr_peri/latest

Test location	/workspace/coverage/default/1.clkmgr_regwen.760634135
Short name	T836
Test name
Test status
Simulation time	309023506 ps
CPU time	1.7 seconds
Started	May 12 01:21:18 PM PDT 24
Finished	May 12 01:21:20 PM PDT 24
Peak memory	200488 kb
Host	smart-e169da31-f6ea-4d78-95cb-a9f45daff287
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760634135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.760634135
Directory	/workspace/1.clkmgr_regwen/latest

Test location	/workspace/coverage/default/1.clkmgr_smoke.1417024962
Short name	T386
Test name
Test status
Simulation time	24059948 ps
CPU time	0.83 seconds
Started	May 12 01:21:16 PM PDT 24
Finished	May 12 01:21:17 PM PDT 24
Peak memory	200444 kb
Host	smart-3b5ac777-d110-4e3b-9add-606d179692cb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417024962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.1417024962
Directory	/workspace/1.clkmgr_smoke/latest

Test location	/workspace/coverage/default/1.clkmgr_stress_all.3302525057
Short name	T794
Test name
Test status
Simulation time	4339901335 ps
CPU time	18.69 seconds
Started	May 12 01:21:19 PM PDT 24
Finished	May 12 01:21:38 PM PDT 24
Peak memory	200856 kb
Host	smart-6f4e10a7-d04c-4401-86c5-36656d24e77c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302525057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all.3302525057
Directory	/workspace/1.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.3469440599
Short name	T171
Test name
Test status
Simulation time	52157866745 ps
CPU time	328.84 seconds
Started	May 12 01:21:19 PM PDT 24
Finished	May 12 01:26:49 PM PDT 24
Peak memory	209176 kb
Host	smart-0f9ce2ac-c619-4394-bd2e-40c983602c81
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3469440599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.3469440599
Directory	/workspace/1.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.clkmgr_trans.3072801368
Short name	T740
Test name
Test status
Simulation time	92723189 ps
CPU time	1.01 seconds
Started	May 12 01:21:17 PM PDT 24
Finished	May 12 01:21:19 PM PDT 24
Peak memory	200524 kb
Host	smart-6b6bc46b-6e00-4315-b995-ea13db53553d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072801368 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.3072801368
Directory	/workspace/1.clkmgr_trans/latest

Test location	/workspace/coverage/default/10.clkmgr_alert_test.1970019231
Short name	T821
Test name
Test status
Simulation time	26162652 ps
CPU time	0.86 seconds
Started	May 12 01:22:01 PM PDT 24
Finished	May 12 01:22:02 PM PDT 24
Peak memory	200572 kb
Host	smart-9288f4a7-c2aa-4f9d-8927-b747bf0d1d91
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970019231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk mgr_alert_test.1970019231
Directory	/workspace/10.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.3732054712
Short name	T243
Test name
Test status
Simulation time	45558931 ps
CPU time	0.97 seconds
Started	May 12 01:22:00 PM PDT 24
Finished	May 12 01:22:02 PM PDT 24
Peak memory	200456 kb
Host	smart-4692b01c-69b1-4523-9312-ff7b64fa1772
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732054712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_handshake_intersig_mubi.3732054712
Directory	/workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_clk_status.459885020
Short name	T743
Test name
Test status
Simulation time	28828959 ps
CPU time	0.73 seconds
Started	May 12 01:21:57 PM PDT 24
Finished	May 12 01:21:58 PM PDT 24
Peak memory	200228 kb
Host	smart-11087052-9333-43a0-a97c-6b6926bdb2c2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459885020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.459885020
Directory	/workspace/10.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/10.clkmgr_div_intersig_mubi.214000797
Short name	T412
Test name
Test status
Simulation time	22970022 ps
CPU time	0.74 seconds
Started	May 12 01:22:00 PM PDT 24
Finished	May 12 01:22:01 PM PDT 24
Peak memory	200448 kb
Host	smart-2f334252-f6e7-480c-8656-c866a7aa5ee5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214000797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.clkmgr_div_intersig_mubi.214000797
Directory	/workspace/10.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_extclk.1974741087
Short name	T800
Test name
Test status
Simulation time	23841083 ps
CPU time	0.81 seconds
Started	May 12 01:21:57 PM PDT 24
Finished	May 12 01:21:59 PM PDT 24
Peak memory	200532 kb
Host	smart-4ab39ab7-d4dd-4180-9749-67c8dbc5beda
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974741087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.1974741087
Directory	/workspace/10.clkmgr_extclk/latest

Test location	/workspace/coverage/default/10.clkmgr_frequency.1547827200
Short name	T382
Test name
Test status
Simulation time	916876003 ps
CPU time	7.36 seconds
Started	May 12 01:21:57 PM PDT 24
Finished	May 12 01:22:05 PM PDT 24
Peak memory	200524 kb
Host	smart-55ca6ba5-f00b-469d-8e62-c47eefab6cfb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547827200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.1547827200
Directory	/workspace/10.clkmgr_frequency/latest

Test location	/workspace/coverage/default/10.clkmgr_frequency_timeout.1277882861
Short name	T325
Test name
Test status
Simulation time	2416038145 ps
CPU time	17.21 seconds
Started	May 12 01:21:57 PM PDT 24
Finished	May 12 01:22:15 PM PDT 24
Peak memory	200852 kb
Host	smart-16aabf17-cab3-4daa-963f-1137635d0314
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277882861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t imeout.1277882861
Directory	/workspace/10.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/10.clkmgr_idle_intersig_mubi.2582883399
Short name	T691
Test name
Test status
Simulation time	44472513 ps
CPU time	1.03 seconds
Started	May 12 01:21:57 PM PDT 24
Finished	May 12 01:21:59 PM PDT 24
Peak memory	200440 kb
Host	smart-3cf1f645-c6ef-44d4-88b6-ad4990a99672
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582883399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_idle_intersig_mubi.2582883399
Directory	/workspace/10.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.1472311243
Short name	T722
Test name
Test status
Simulation time	108713758 ps
CPU time	1.01 seconds
Started	May 12 01:22:01 PM PDT 24
Finished	May 12 01:22:03 PM PDT 24
Peak memory	200552 kb
Host	smart-4a5ff4c6-4d15-48e0-a9a8-066f76ecb3fc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472311243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.clkmgr_lc_clk_byp_req_intersig_mubi.1472311243
Directory	/workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.3434503259
Short name	T483
Test name
Test status
Simulation time	18099441 ps
CPU time	0.75 seconds
Started	May 12 01:21:58 PM PDT 24
Finished	May 12 01:21:59 PM PDT 24
Peak memory	200500 kb
Host	smart-2b4f7bea-cae2-473e-ae8f-6956ba84250f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434503259 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 10.clkmgr_lc_ctrl_intersig_mubi.3434503259
Directory	/workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/10.clkmgr_peri.955324820
Short name	T233
Test name
Test status
Simulation time	34425455 ps
CPU time	0.82 seconds
Started	May 12 01:21:57 PM PDT 24
Finished	May 12 01:21:58 PM PDT 24
Peak memory	200244 kb
Host	smart-bffffc1f-023d-4dab-8546-f996d8aff046
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955324820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.955324820
Directory	/workspace/10.clkmgr_peri/latest

Test location	/workspace/coverage/default/10.clkmgr_regwen.4199252593
Short name	T127
Test name
Test status
Simulation time	98507230 ps
CPU time	1.11 seconds
Started	May 12 01:22:00 PM PDT 24
Finished	May 12 01:22:02 PM PDT 24
Peak memory	200468 kb
Host	smart-576c8d13-4fb3-4382-afc7-3f5738ab5584
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199252593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.4199252593
Directory	/workspace/10.clkmgr_regwen/latest

Test location	/workspace/coverage/default/10.clkmgr_smoke.743149407
Short name	T250
Test name
Test status
Simulation time	146140088 ps
CPU time	1.17 seconds
Started	May 12 01:21:59 PM PDT 24
Finished	May 12 01:22:00 PM PDT 24
Peak memory	200492 kb
Host	smart-9671be98-8be4-4620-b8e9-535b3b907e1c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743149407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.743149407
Directory	/workspace/10.clkmgr_smoke/latest

Test location	/workspace/coverage/default/10.clkmgr_stress_all.3824405581
Short name	T454
Test name
Test status
Simulation time	122991966 ps
CPU time	1.3 seconds
Started	May 12 01:22:01 PM PDT 24
Finished	May 12 01:22:03 PM PDT 24
Peak memory	200484 kb
Host	smart-46b07bb8-58b2-40d2-90e3-6e8d458bd8e8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824405581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all.3824405581
Directory	/workspace/10.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.3626892828
Short name	T729
Test name
Test status
Simulation time	61882169146 ps
CPU time	352.93 seconds
Started	May 12 01:22:00 PM PDT 24
Finished	May 12 01:27:53 PM PDT 24
Peak memory	209176 kb
Host	smart-d7a0605d-5526-4ef9-9a41-ce778d470de9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3626892828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.3626892828
Directory	/workspace/10.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.clkmgr_trans.2040846170
Short name	T401
Test name
Test status
Simulation time	30021052 ps
CPU time	0.92 seconds
Started	May 12 01:21:56 PM PDT 24
Finished	May 12 01:21:58 PM PDT 24
Peak memory	200484 kb
Host	smart-b6f4ac77-7e91-47bf-b6d8-6e59d7e6e854
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040846170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.2040846170
Directory	/workspace/10.clkmgr_trans/latest

Test location	/workspace/coverage/default/11.clkmgr_alert_test.354480571
Short name	T828
Test name
Test status
Simulation time	22993918 ps
CPU time	0.88 seconds
Started	May 12 01:22:03 PM PDT 24
Finished	May 12 01:22:04 PM PDT 24
Peak memory	200528 kb
Host	smart-95fbd99e-cd32-46bf-9263-1e924d299616
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354480571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkm gr_alert_test.354480571
Directory	/workspace/11.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.1306167909
Short name	T549
Test name
Test status
Simulation time	55702931 ps
CPU time	0.96 seconds
Started	May 12 01:22:02 PM PDT 24
Finished	May 12 01:22:03 PM PDT 24
Peak memory	200504 kb
Host	smart-2ff63a7a-461b-46cf-9d37-7c909df83c33
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306167909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_handshake_intersig_mubi.1306167909
Directory	/workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_clk_status.1781682503
Short name	T411
Test name
Test status
Simulation time	16465899 ps
CPU time	0.69 seconds
Started	May 12 01:21:59 PM PDT 24
Finished	May 12 01:22:00 PM PDT 24
Peak memory	200228 kb
Host	smart-05b0f4f6-f14e-4f05-b25b-bb40d3518645
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781682503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.1781682503
Directory	/workspace/11.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/11.clkmgr_div_intersig_mubi.1127365971
Short name	T555
Test name
Test status
Simulation time	13287311 ps
CPU time	0.74 seconds
Started	May 12 01:22:06 PM PDT 24
Finished	May 12 01:22:08 PM PDT 24
Peak memory	200480 kb
Host	smart-92eb2b01-9d54-47b3-a529-5ac5e4a62f38
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127365971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_div_intersig_mubi.1127365971
Directory	/workspace/11.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_extclk.240318042
Short name	T534
Test name
Test status
Simulation time	25229571 ps
CPU time	0.85 seconds
Started	May 12 01:22:03 PM PDT 24
Finished	May 12 01:22:04 PM PDT 24
Peak memory	200520 kb
Host	smart-916754da-3088-4dc7-8b2b-6bae15abe302
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240318042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.240318042
Directory	/workspace/11.clkmgr_extclk/latest

Test location	/workspace/coverage/default/11.clkmgr_frequency.902281813
Short name	T282
Test name
Test status
Simulation time	2358977494 ps
CPU time	17.87 seconds
Started	May 12 01:21:59 PM PDT 24
Finished	May 12 01:22:17 PM PDT 24
Peak memory	200760 kb
Host	smart-9112dd8a-bad7-4748-a1c7-85a9ad5212ab
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902281813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.902281813
Directory	/workspace/11.clkmgr_frequency/latest

Test location	/workspace/coverage/default/11.clkmgr_frequency_timeout.4138151254
Short name	T614
Test name
Test status
Simulation time	1615360644 ps
CPU time	7.37 seconds
Started	May 12 01:22:00 PM PDT 24
Finished	May 12 01:22:07 PM PDT 24
Peak memory	200540 kb
Host	smart-b452d8ae-1235-4b11-ac28-8092f8fdf2e4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138151254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t imeout.4138151254
Directory	/workspace/11.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/11.clkmgr_idle_intersig_mubi.2724152329
Short name	T42
Test name
Test status
Simulation time	93771543 ps
CPU time	1.15 seconds
Started	May 12 01:22:02 PM PDT 24
Finished	May 12 01:22:04 PM PDT 24
Peak memory	200492 kb
Host	smart-5fb1d29f-285b-4868-ae8f-e8674ff01a15
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724152329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_idle_intersig_mubi.2724152329
Directory	/workspace/11.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.2726530333
Short name	T319
Test name
Test status
Simulation time	25653705 ps
CPU time	0.76 seconds
Started	May 12 01:21:58 PM PDT 24
Finished	May 12 01:22:00 PM PDT 24
Peak memory	200512 kb
Host	smart-ab9c9735-402f-4c8d-92ff-4811fea38029
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726530333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 11.clkmgr_lc_clk_byp_req_intersig_mubi.2726530333
Directory	/workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.1816244241
Short name	T827
Test name
Test status
Simulation time	26842600 ps
CPU time	0.93 seconds
Started	May 12 01:22:01 PM PDT 24
Finished	May 12 01:22:03 PM PDT 24
Peak memory	200456 kb
Host	smart-5eb51aee-cb78-4548-9bfb-3ae8bc0f30b5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816244241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 11.clkmgr_lc_ctrl_intersig_mubi.1816244241
Directory	/workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/11.clkmgr_peri.895474828
Short name	T650
Test name
Test status
Simulation time	23569108 ps
CPU time	0.78 seconds
Started	May 12 01:22:01 PM PDT 24
Finished	May 12 01:22:02 PM PDT 24
Peak memory	200296 kb
Host	smart-0eb001fd-efd1-4951-9d0e-0104218b5f84
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895474828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.895474828
Directory	/workspace/11.clkmgr_peri/latest

Test location	/workspace/coverage/default/11.clkmgr_regwen.224708322
Short name	T595
Test name
Test status
Simulation time	895474721 ps
CPU time	5.42 seconds
Started	May 12 01:22:13 PM PDT 24
Finished	May 12 01:22:19 PM PDT 24
Peak memory	200672 kb
Host	smart-3b3f66b8-324a-4a95-9099-83e297b9161d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224708322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.224708322
Directory	/workspace/11.clkmgr_regwen/latest

Test location	/workspace/coverage/default/11.clkmgr_smoke.2415548526
Short name	T239
Test name
Test status
Simulation time	72362264 ps
CPU time	1 seconds
Started	May 12 01:22:02 PM PDT 24
Finished	May 12 01:22:04 PM PDT 24
Peak memory	200440 kb
Host	smart-05ab2206-5de6-41e8-8bde-4fdf58df2a8b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415548526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.2415548526
Directory	/workspace/11.clkmgr_smoke/latest

Test location	/workspace/coverage/default/11.clkmgr_trans.1699886352
Short name	T223
Test name
Test status
Simulation time	25063900 ps
CPU time	0.91 seconds
Started	May 12 01:22:00 PM PDT 24
Finished	May 12 01:22:01 PM PDT 24
Peak memory	200500 kb
Host	smart-c1b35f73-09a3-4349-b9db-ed96df3a118b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699886352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.1699886352
Directory	/workspace/11.clkmgr_trans/latest

Test location	/workspace/coverage/default/12.clkmgr_alert_test.2548695767
Short name	T719
Test name
Test status
Simulation time	42351676 ps
CPU time	0.82 seconds
Started	May 12 01:22:05 PM PDT 24
Finished	May 12 01:22:06 PM PDT 24
Peak memory	200588 kb
Host	smart-3eff7ca2-3b8b-478b-a876-0c35bf239052
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548695767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk mgr_alert_test.2548695767
Directory	/workspace/12.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.3908406636
Short name	T106
Test name
Test status
Simulation time	35940074 ps
CPU time	0.88 seconds
Started	May 12 01:22:13 PM PDT 24
Finished	May 12 01:22:15 PM PDT 24
Peak memory	200512 kb
Host	smart-b1339baf-3dd0-409d-a802-47864ed78003
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908406636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_handshake_intersig_mubi.3908406636
Directory	/workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_div_intersig_mubi.1892330142
Short name	T736
Test name
Test status
Simulation time	73917853 ps
CPU time	1.01 seconds
Started	May 12 01:22:06 PM PDT 24
Finished	May 12 01:22:08 PM PDT 24
Peak memory	200480 kb
Host	smart-1017ea30-3922-4ebe-b9d4-f5d5fdd860fd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892330142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_div_intersig_mubi.1892330142
Directory	/workspace/12.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_extclk.1531069173
Short name	T163
Test name
Test status
Simulation time	31866295 ps
CPU time	0.84 seconds
Started	May 12 01:22:08 PM PDT 24
Finished	May 12 01:22:09 PM PDT 24
Peak memory	200468 kb
Host	smart-642327c6-6ed4-480c-b5f6-d447f989838a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531069173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.1531069173
Directory	/workspace/12.clkmgr_extclk/latest

Test location	/workspace/coverage/default/12.clkmgr_frequency.2174110897
Short name	T130
Test name
Test status
Simulation time	1528496970 ps
CPU time	8.43 seconds
Started	May 12 01:22:13 PM PDT 24
Finished	May 12 01:22:22 PM PDT 24
Peak memory	200588 kb
Host	smart-8d27c5f9-6f9e-4ed4-a793-37304e1896f6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174110897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.2174110897
Directory	/workspace/12.clkmgr_frequency/latest

Test location	/workspace/coverage/default/12.clkmgr_frequency_timeout.2672927534
Short name	T596
Test name
Test status
Simulation time	664266298 ps
CPU time	2.67 seconds
Started	May 12 01:22:07 PM PDT 24
Finished	May 12 01:22:10 PM PDT 24
Peak memory	200628 kb
Host	smart-0765a768-7837-4fea-ab50-110523c0a9cf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672927534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t imeout.2672927534
Directory	/workspace/12.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.1494873622
Short name	T755
Test name
Test status
Simulation time	177851884 ps
CPU time	1.29 seconds
Started	May 12 01:23:02 PM PDT 24
Finished	May 12 01:23:03 PM PDT 24
Peak memory	200532 kb
Host	smart-4785dc7d-b0d0-4a05-b99d-c1743b896cba
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494873622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.clkmgr_lc_clk_byp_req_intersig_mubi.1494873622
Directory	/workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.1785659948
Short name	T207
Test name
Test status
Simulation time	12791659 ps
CPU time	0.75 seconds
Started	May 12 01:22:06 PM PDT 24
Finished	May 12 01:22:07 PM PDT 24
Peak memory	200536 kb
Host	smart-33ce1ce9-aa3e-4421-be95-b035051bbca5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785659948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 12.clkmgr_lc_ctrl_intersig_mubi.1785659948
Directory	/workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/12.clkmgr_peri.3171443704
Short name	T761
Test name
Test status
Simulation time	29574016 ps
CPU time	0.77 seconds
Started	May 12 01:22:14 PM PDT 24
Finished	May 12 01:22:16 PM PDT 24
Peak memory	200316 kb
Host	smart-afe3cf0a-a98f-4fea-9cb1-eab7ad8caa01
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171443704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.3171443704
Directory	/workspace/12.clkmgr_peri/latest

Test location	/workspace/coverage/default/12.clkmgr_regwen.586045970
Short name	T356
Test name
Test status
Simulation time	308975914 ps
CPU time	1.83 seconds
Started	May 12 01:22:06 PM PDT 24
Finished	May 12 01:22:08 PM PDT 24
Peak memory	200412 kb
Host	smart-3f0bb512-feaa-415f-95f4-a37602012e8b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586045970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.586045970
Directory	/workspace/12.clkmgr_regwen/latest

Test location	/workspace/coverage/default/12.clkmgr_smoke.3818942494
Short name	T597
Test name
Test status
Simulation time	18526117 ps
CPU time	0.82 seconds
Started	May 12 01:22:06 PM PDT 24
Finished	May 12 01:22:07 PM PDT 24
Peak memory	200512 kb
Host	smart-06effe15-024a-499c-a1c2-823c592bf7e8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818942494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.3818942494
Directory	/workspace/12.clkmgr_smoke/latest

Test location	/workspace/coverage/default/12.clkmgr_stress_all.1520238237
Short name	T415
Test name
Test status
Simulation time	5955807589 ps
CPU time	32.28 seconds
Started	May 12 01:22:13 PM PDT 24
Finished	May 12 01:22:46 PM PDT 24
Peak memory	200948 kb
Host	smart-689d6686-324e-41fb-a0b7-a9e39ad586b3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520238237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all.1520238237
Directory	/workspace/12.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/12.clkmgr_stress_all_with_rand_reset.2530097257
Short name	T524
Test name
Test status
Simulation time	27049410908 ps
CPU time	469.34 seconds
Started	May 12 01:22:04 PM PDT 24
Finished	May 12 01:29:54 PM PDT 24
Peak memory	209148 kb
Host	smart-03f81072-10e2-43df-b27a-1f8dc4945a12
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2530097257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.2530097257
Directory	/workspace/12.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.clkmgr_trans.2633861748
Short name	T286
Test name
Test status
Simulation time	52327790 ps
CPU time	1.07 seconds
Started	May 12 01:22:11 PM PDT 24
Finished	May 12 01:22:12 PM PDT 24
Peak memory	200476 kb
Host	smart-d1da1f9d-1da2-49e8-b3fd-36a43796fde4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633861748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.2633861748
Directory	/workspace/12.clkmgr_trans/latest

Test location	/workspace/coverage/default/13.clkmgr_alert_test.3453965659
Short name	T824
Test name
Test status
Simulation time	18188045 ps
CPU time	0.76 seconds
Started	May 12 01:22:04 PM PDT 24
Finished	May 12 01:22:05 PM PDT 24
Peak memory	200576 kb
Host	smart-f1039e12-a14c-4406-82ea-3b05b0768733
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453965659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk mgr_alert_test.3453965659
Directory	/workspace/13.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.2465433495
Short name	T95
Test name
Test status
Simulation time	25255340 ps
CPU time	0.91 seconds
Started	May 12 01:22:13 PM PDT 24
Finished	May 12 01:22:15 PM PDT 24
Peak memory	200508 kb
Host	smart-7c7b08db-8397-4c77-9903-67b6fc62180b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465433495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_handshake_intersig_mubi.2465433495
Directory	/workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_clk_status.2518936610
Short name	T86
Test name
Test status
Simulation time	15470435 ps
CPU time	0.71 seconds
Started	May 12 01:22:06 PM PDT 24
Finished	May 12 01:22:08 PM PDT 24
Peak memory	199520 kb
Host	smart-500c4c1d-c7fc-4f3f-a214-90d2ffb27e0a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518936610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.2518936610
Directory	/workspace/13.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/13.clkmgr_div_intersig_mubi.1131398726
Short name	T576
Test name
Test status
Simulation time	22407097 ps
CPU time	0.84 seconds
Started	May 12 01:22:06 PM PDT 24
Finished	May 12 01:22:07 PM PDT 24
Peak memory	200448 kb
Host	smart-cfe54986-46eb-4479-b635-7de57e24aaa3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131398726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_div_intersig_mubi.1131398726
Directory	/workspace/13.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_extclk.3703508139
Short name	T678
Test name
Test status
Simulation time	74667923 ps
CPU time	0.97 seconds
Started	May 12 01:22:13 PM PDT 24
Finished	May 12 01:22:15 PM PDT 24
Peak memory	200516 kb
Host	smart-364c86ac-f156-4fee-9d38-dfe62ac555c5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703508139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.3703508139
Directory	/workspace/13.clkmgr_extclk/latest

Test location	/workspace/coverage/default/13.clkmgr_frequency.3310571896
Short name	T434
Test name
Test status
Simulation time	316771857 ps
CPU time	2.86 seconds
Started	May 12 01:22:12 PM PDT 24
Finished	May 12 01:22:16 PM PDT 24
Peak memory	200544 kb
Host	smart-7798e9e8-a5ca-4904-9908-2bfba91564b3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310571896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.3310571896
Directory	/workspace/13.clkmgr_frequency/latest

Test location	/workspace/coverage/default/13.clkmgr_frequency_timeout.786509086
Short name	T634
Test name
Test status
Simulation time	497704470 ps
CPU time	4.01 seconds
Started	May 12 01:22:08 PM PDT 24
Finished	May 12 01:22:13 PM PDT 24
Peak memory	200660 kb
Host	smart-cf34bf92-9483-44b7-bdb3-f29c7c2184ca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786509086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_ti meout.786509086
Directory	/workspace/13.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/13.clkmgr_idle_intersig_mubi.3559033294
Short name	T849
Test name
Test status
Simulation time	21006600 ps
CPU time	0.82 seconds
Started	May 12 01:22:04 PM PDT 24
Finished	May 12 01:22:05 PM PDT 24
Peak memory	200512 kb
Host	smart-7c9bb681-96a6-406a-b5b3-57cef237fce2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559033294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_idle_intersig_mubi.3559033294
Directory	/workspace/13.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.1343697825
Short name	T203
Test name
Test status
Simulation time	87694087 ps
CPU time	1.07 seconds
Started	May 12 01:22:10 PM PDT 24
Finished	May 12 01:22:12 PM PDT 24
Peak memory	200492 kb
Host	smart-154738a8-5e26-45e0-9bce-a5a3c60b7788
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343697825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 13.clkmgr_lc_clk_byp_req_intersig_mubi.1343697825
Directory	/workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.2217361248
Short name	T699
Test name
Test status
Simulation time	24990018 ps
CPU time	0.88 seconds
Started	May 12 01:22:13 PM PDT 24
Finished	May 12 01:22:15 PM PDT 24
Peak memory	200524 kb
Host	smart-01d2e4cd-df1f-4cb8-ae23-72139425fc6c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217361248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 13.clkmgr_lc_ctrl_intersig_mubi.2217361248
Directory	/workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/13.clkmgr_peri.1633240276
Short name	T55
Test name
Test status
Simulation time	11592525 ps
CPU time	0.7 seconds
Started	May 12 01:22:05 PM PDT 24
Finished	May 12 01:22:06 PM PDT 24
Peak memory	200248 kb
Host	smart-7471afb2-309c-4339-9247-4a1a43c48b7e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633240276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.1633240276
Directory	/workspace/13.clkmgr_peri/latest

Test location	/workspace/coverage/default/13.clkmgr_regwen.3329669936
Short name	T527
Test name
Test status
Simulation time	1096005233 ps
CPU time	5.62 seconds
Started	May 12 01:22:05 PM PDT 24
Finished	May 12 01:22:11 PM PDT 24
Peak memory	200652 kb
Host	smart-0f58350c-53ed-43ee-a447-7635d9facb7b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329669936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.3329669936
Directory	/workspace/13.clkmgr_regwen/latest

Test location	/workspace/coverage/default/13.clkmgr_smoke.1249608414
Short name	T579
Test name
Test status
Simulation time	17237478 ps
CPU time	0.79 seconds
Started	May 12 01:22:06 PM PDT 24
Finished	May 12 01:22:07 PM PDT 24
Peak memory	200480 kb
Host	smart-9323d3cc-d4d4-4b83-82c4-43d0eac8aae6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249608414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.1249608414
Directory	/workspace/13.clkmgr_smoke/latest

Test location	/workspace/coverage/default/13.clkmgr_stress_all.369123824
Short name	T154
Test name
Test status
Simulation time	11426770763 ps
CPU time	84.53 seconds
Started	May 12 01:22:05 PM PDT 24
Finished	May 12 01:23:29 PM PDT 24
Peak memory	200964 kb
Host	smart-35548e82-5d39-402e-bd96-4ff496591fc9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369123824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all.369123824
Directory	/workspace/13.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.2937749488
Short name	T385
Test name
Test status
Simulation time	130108806997 ps
CPU time	718.22 seconds
Started	May 12 01:22:04 PM PDT 24
Finished	May 12 01:34:03 PM PDT 24
Peak memory	212948 kb
Host	smart-0f06b28e-cc21-4143-bcbd-3e171e5f8374
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2937749488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.2937749488
Directory	/workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.clkmgr_trans.496008324
Short name	T837
Test name
Test status
Simulation time	41441962 ps
CPU time	1.09 seconds
Started	May 12 01:22:07 PM PDT 24
Finished	May 12 01:22:08 PM PDT 24
Peak memory	200476 kb
Host	smart-cf121ad2-86fd-4850-9786-f492b4356fb3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496008324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.496008324
Directory	/workspace/13.clkmgr_trans/latest

Test location	/workspace/coverage/default/14.clkmgr_alert_test.1533487286
Short name	T226
Test name
Test status
Simulation time	19998224 ps
CPU time	0.74 seconds
Started	May 12 01:22:11 PM PDT 24
Finished	May 12 01:22:12 PM PDT 24
Peak memory	200524 kb
Host	smart-c89a2ccc-cfc1-4d9a-8997-2d4a079d361c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533487286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk mgr_alert_test.1533487286
Directory	/workspace/14.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.659568780
Short name	T110
Test name
Test status
Simulation time	24914438 ps
CPU time	0.9 seconds
Started	May 12 01:22:08 PM PDT 24
Finished	May 12 01:22:09 PM PDT 24
Peak memory	200512 kb
Host	smart-abb86e86-b340-49f4-83ab-bd8611599aee
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659568780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_handshake_intersig_mubi.659568780
Directory	/workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_clk_status.4052983628
Short name	T788
Test name
Test status
Simulation time	19527524 ps
CPU time	0.73 seconds
Started	May 12 01:22:10 PM PDT 24
Finished	May 12 01:22:11 PM PDT 24
Peak memory	199528 kb
Host	smart-9bdba028-1c8c-4cb2-8b4c-be30069c8319
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052983628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.4052983628
Directory	/workspace/14.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/14.clkmgr_div_intersig_mubi.3426700127
Short name	T220
Test name
Test status
Simulation time	16187142 ps
CPU time	0.84 seconds
Started	May 12 01:22:10 PM PDT 24
Finished	May 12 01:22:11 PM PDT 24
Peak memory	200472 kb
Host	smart-dc4ac499-4904-438d-873e-77d317241bd2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426700127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_div_intersig_mubi.3426700127
Directory	/workspace/14.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_extclk.264177502
Short name	T90
Test name
Test status
Simulation time	30314565 ps
CPU time	1.01 seconds
Started	May 12 01:22:11 PM PDT 24
Finished	May 12 01:22:13 PM PDT 24
Peak memory	200432 kb
Host	smart-2a8c61d3-e7cf-4dd4-848c-2247fb1b5984
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264177502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.264177502
Directory	/workspace/14.clkmgr_extclk/latest

Test location	/workspace/coverage/default/14.clkmgr_frequency.3474556774
Short name	T326
Test name
Test status
Simulation time	563139526 ps
CPU time	3.5 seconds
Started	May 12 01:22:10 PM PDT 24
Finished	May 12 01:22:14 PM PDT 24
Peak memory	200544 kb
Host	smart-cc400f9f-1bff-4de5-841a-656e06d4f29f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474556774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.3474556774
Directory	/workspace/14.clkmgr_frequency/latest

Test location	/workspace/coverage/default/14.clkmgr_idle_intersig_mubi.2533594466
Short name	T461
Test name
Test status
Simulation time	12597755 ps
CPU time	0.74 seconds
Started	May 12 01:22:11 PM PDT 24
Finished	May 12 01:22:12 PM PDT 24
Peak memory	200360 kb
Host	smart-5ea3fa63-db3e-414a-af9f-535f99469b29
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533594466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_idle_intersig_mubi.2533594466
Directory	/workspace/14.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.2334670911
Short name	T599
Test name
Test status
Simulation time	24045958 ps
CPU time	0.88 seconds
Started	May 12 01:22:09 PM PDT 24
Finished	May 12 01:22:10 PM PDT 24
Peak memory	200476 kb
Host	smart-752e3560-287b-45fd-993e-3a56736aaefe
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334670911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 14.clkmgr_lc_clk_byp_req_intersig_mubi.2334670911
Directory	/workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.2982946848
Short name	T213
Test name
Test status
Simulation time	13881943 ps
CPU time	0.74 seconds
Started	May 12 01:22:12 PM PDT 24
Finished	May 12 01:22:14 PM PDT 24
Peak memory	200500 kb
Host	smart-e03d2320-1dfc-4333-b6b3-08de1c90e4c3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982946848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 14.clkmgr_lc_ctrl_intersig_mubi.2982946848
Directory	/workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/14.clkmgr_peri.2341307265
Short name	T832
Test name
Test status
Simulation time	16775955 ps
CPU time	0.74 seconds
Started	May 12 01:22:10 PM PDT 24
Finished	May 12 01:22:12 PM PDT 24
Peak memory	200276 kb
Host	smart-beaa6f9d-8a38-4146-b501-bfe7b9d6119c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341307265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.2341307265
Directory	/workspace/14.clkmgr_peri/latest

Test location	/workspace/coverage/default/14.clkmgr_regwen.589629760
Short name	T612
Test name
Test status
Simulation time	679218307 ps
CPU time	4.28 seconds
Started	May 12 01:22:09 PM PDT 24
Finished	May 12 01:22:14 PM PDT 24
Peak memory	200632 kb
Host	smart-a1c04956-7e99-4aac-9ddc-e373fab64ea1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589629760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.589629760
Directory	/workspace/14.clkmgr_regwen/latest

Test location	/workspace/coverage/default/14.clkmgr_smoke.3589256880
Short name	T620
Test name
Test status
Simulation time	61022501 ps
CPU time	0.94 seconds
Started	May 12 01:22:09 PM PDT 24
Finished	May 12 01:22:11 PM PDT 24
Peak memory	200480 kb
Host	smart-d3c5c839-948c-4baf-9e73-1b6e905f6a42
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589256880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.3589256880
Directory	/workspace/14.clkmgr_smoke/latest

Test location	/workspace/coverage/default/14.clkmgr_stress_all.2820130886
Short name	T456
Test name
Test status
Simulation time	5199413579 ps
CPU time	21.11 seconds
Started	May 12 01:22:09 PM PDT 24
Finished	May 12 01:22:31 PM PDT 24
Peak memory	200984 kb
Host	smart-634dafbf-f0a8-4ebf-98bc-daea40823ed1
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820130886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all.2820130886
Directory	/workspace/14.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/14.clkmgr_trans.3021987936
Short name	T192
Test name
Test status
Simulation time	58164693 ps
CPU time	0.92 seconds
Started	May 12 01:22:09 PM PDT 24
Finished	May 12 01:22:10 PM PDT 24
Peak memory	200472 kb
Host	smart-facaf1ee-fe50-4ff3-b43f-128473c16cce
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021987936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.3021987936
Directory	/workspace/14.clkmgr_trans/latest

Test location	/workspace/coverage/default/15.clkmgr_alert_test.2378615378
Short name	T270
Test name
Test status
Simulation time	15773452 ps
CPU time	0.75 seconds
Started	May 12 01:22:14 PM PDT 24
Finished	May 12 01:22:16 PM PDT 24
Peak memory	200484 kb
Host	smart-5cf8545e-57fc-452f-af94-a2633a7d1f8b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378615378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk mgr_alert_test.2378615378
Directory	/workspace/15.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.1046171742
Short name	T748
Test name
Test status
Simulation time	19171564 ps
CPU time	0.8 seconds
Started	May 12 01:22:13 PM PDT 24
Finished	May 12 01:22:15 PM PDT 24
Peak memory	200440 kb
Host	smart-f56981c7-2a0c-46a7-84df-e45119aad306
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046171742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_handshake_intersig_mubi.1046171742
Directory	/workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_clk_status.1295878233
Short name	T516
Test name
Test status
Simulation time	50325575 ps
CPU time	0.78 seconds
Started	May 12 01:22:13 PM PDT 24
Finished	May 12 01:22:14 PM PDT 24
Peak memory	199504 kb
Host	smart-fcdf5d10-3c84-4b53-8509-a76593c5d4f8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295878233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.1295878233
Directory	/workspace/15.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/15.clkmgr_div_intersig_mubi.100940684
Short name	T406
Test name
Test status
Simulation time	15050357 ps
CPU time	0.74 seconds
Started	May 12 01:22:13 PM PDT 24
Finished	May 12 01:22:15 PM PDT 24
Peak memory	200508 kb
Host	smart-11eaf6b0-0ba9-411e-a7af-456818e38429
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100940684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.clkmgr_div_intersig_mubi.100940684
Directory	/workspace/15.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_extclk.3272711913
Short name	T667
Test name
Test status
Simulation time	21368343 ps
CPU time	0.83 seconds
Started	May 12 01:22:12 PM PDT 24
Finished	May 12 01:22:13 PM PDT 24
Peak memory	200504 kb
Host	smart-6d4263d5-0c8f-4868-b6c9-8c347db549d8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272711913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.3272711913
Directory	/workspace/15.clkmgr_extclk/latest

Test location	/workspace/coverage/default/15.clkmgr_frequency.3355329730
Short name	T309
Test name
Test status
Simulation time	383247288 ps
CPU time	1.92 seconds
Started	May 12 01:22:09 PM PDT 24
Finished	May 12 01:22:11 PM PDT 24
Peak memory	200528 kb
Host	smart-1e1f593a-0460-4782-948a-3f526773511c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355329730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.3355329730
Directory	/workspace/15.clkmgr_frequency/latest

Test location	/workspace/coverage/default/15.clkmgr_frequency_timeout.2902841194
Short name	T638
Test name
Test status
Simulation time	1816878202 ps
CPU time	12.49 seconds
Started	May 12 01:22:15 PM PDT 24
Finished	May 12 01:22:28 PM PDT 24
Peak memory	200652 kb
Host	smart-b1e24c51-6451-45af-ab21-e6688acda9ee
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902841194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t imeout.2902841194
Directory	/workspace/15.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/15.clkmgr_idle_intersig_mubi.996382822
Short name	T188
Test name
Test status
Simulation time	19421106 ps
CPU time	0.82 seconds
Started	May 12 01:22:16 PM PDT 24
Finished	May 12 01:22:17 PM PDT 24
Peak memory	200436 kb
Host	smart-b58a5275-5815-4470-b269-38e6b722bccd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996382822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.clkmgr_idle_intersig_mubi.996382822
Directory	/workspace/15.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.4106030852
Short name	T284
Test name
Test status
Simulation time	104158298 ps
CPU time	1.09 seconds
Started	May 12 01:22:15 PM PDT 24
Finished	May 12 01:22:17 PM PDT 24
Peak memory	200508 kb
Host	smart-9a599ef6-6f9d-4afe-a907-c397a014fed5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106030852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.clkmgr_lc_clk_byp_req_intersig_mubi.4106030852
Directory	/workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.2794605665
Short name	T570
Test name
Test status
Simulation time	53692334 ps
CPU time	0.87 seconds
Started	May 12 01:22:15 PM PDT 24
Finished	May 12 01:22:16 PM PDT 24
Peak memory	200524 kb
Host	smart-5d4ec819-ccd2-4d1e-938b-9e934fb73f02
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794605665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 15.clkmgr_lc_ctrl_intersig_mubi.2794605665
Directory	/workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/15.clkmgr_peri.2657503851
Short name	T687
Test name
Test status
Simulation time	25693198 ps
CPU time	0.82 seconds
Started	May 12 01:22:14 PM PDT 24
Finished	May 12 01:22:16 PM PDT 24
Peak memory	200324 kb
Host	smart-c8b8c32b-00b8-4577-91b5-176f39f3afcd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657503851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.2657503851
Directory	/workspace/15.clkmgr_peri/latest

Test location	/workspace/coverage/default/15.clkmgr_regwen.1334291646
Short name	T819
Test name
Test status
Simulation time	1237510259 ps
CPU time	5.02 seconds
Started	May 12 01:22:15 PM PDT 24
Finished	May 12 01:22:20 PM PDT 24
Peak memory	200656 kb
Host	smart-467cf3d2-c3b7-4ea6-baf2-f05e2a46b674
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334291646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.1334291646
Directory	/workspace/15.clkmgr_regwen/latest

Test location	/workspace/coverage/default/15.clkmgr_smoke.1779209330
Short name	T222
Test name
Test status
Simulation time	18990449 ps
CPU time	0.81 seconds
Started	May 12 01:22:08 PM PDT 24
Finished	May 12 01:22:10 PM PDT 24
Peak memory	200492 kb
Host	smart-45b339bb-d85b-431b-83eb-5bf48ab773b1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779209330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.1779209330
Directory	/workspace/15.clkmgr_smoke/latest

Test location	/workspace/coverage/default/15.clkmgr_stress_all.2207432346
Short name	T507
Test name
Test status
Simulation time	5381921926 ps
CPU time	22.33 seconds
Started	May 12 01:22:17 PM PDT 24
Finished	May 12 01:22:40 PM PDT 24
Peak memory	201140 kb
Host	smart-73d96715-1f05-45b2-8f4a-953247ef73b9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207432346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all.2207432346
Directory	/workspace/15.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.1638335502
Short name	T764
Test name
Test status
Simulation time	171717571600 ps
CPU time	1013.77 seconds
Started	May 12 01:22:14 PM PDT 24
Finished	May 12 01:39:09 PM PDT 24
Peak memory	217340 kb
Host	smart-e623b23f-0ce1-4b29-8f86-6379bc87cef3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1638335502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.1638335502
Directory	/workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.clkmgr_trans.936665054
Short name	T437
Test name
Test status
Simulation time	33912003 ps
CPU time	1.05 seconds
Started	May 12 01:22:14 PM PDT 24
Finished	May 12 01:22:15 PM PDT 24
Peak memory	200456 kb
Host	smart-27ce3a51-fc21-4c80-9a23-ff4539a2450c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936665054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.936665054
Directory	/workspace/15.clkmgr_trans/latest

Test location	/workspace/coverage/default/16.clkmgr_alert_test.3993424008
Short name	T290
Test name
Test status
Simulation time	47150377 ps
CPU time	0.86 seconds
Started	May 12 01:22:24 PM PDT 24
Finished	May 12 01:22:26 PM PDT 24
Peak memory	200536 kb
Host	smart-fd7cdcb0-156b-43f4-b783-ca60622e230b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993424008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk mgr_alert_test.3993424008
Directory	/workspace/16.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.1765958082
Short name	T277
Test name
Test status
Simulation time	15912009 ps
CPU time	0.73 seconds
Started	May 12 01:22:16 PM PDT 24
Finished	May 12 01:22:17 PM PDT 24
Peak memory	200508 kb
Host	smart-455eb849-058c-4b8c-9d77-4f8721edec50
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765958082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_handshake_intersig_mubi.1765958082
Directory	/workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_clk_status.2736595383
Short name	T855
Test name
Test status
Simulation time	14745065 ps
CPU time	0.69 seconds
Started	May 12 01:22:17 PM PDT 24
Finished	May 12 01:22:18 PM PDT 24
Peak memory	199556 kb
Host	smart-9dd288c2-c4d1-4b0a-aa17-b14676439669
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736595383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.2736595383
Directory	/workspace/16.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/16.clkmgr_div_intersig_mubi.682408696
Short name	T252
Test name
Test status
Simulation time	84122599 ps
CPU time	1.14 seconds
Started	May 12 01:22:15 PM PDT 24
Finished	May 12 01:22:17 PM PDT 24
Peak memory	200516 kb
Host	smart-357b268e-abc5-49f9-b5f1-4b2af9bf7c2f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682408696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.clkmgr_div_intersig_mubi.682408696
Directory	/workspace/16.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_extclk.317488409
Short name	T211
Test name
Test status
Simulation time	166909288 ps
CPU time	1.26 seconds
Started	May 12 01:22:16 PM PDT 24
Finished	May 12 01:22:17 PM PDT 24
Peak memory	200508 kb
Host	smart-057c53c4-0d28-475a-bd1d-106de4904702
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317488409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.317488409
Directory	/workspace/16.clkmgr_extclk/latest

Test location	/workspace/coverage/default/16.clkmgr_frequency.1292144831
Short name	T750
Test name
Test status
Simulation time	2594265337 ps
CPU time	11.99 seconds
Started	May 12 01:22:14 PM PDT 24
Finished	May 12 01:22:27 PM PDT 24
Peak memory	200820 kb
Host	smart-bfccff93-7696-4b44-a708-09ac677c52bd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292144831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.1292144831
Directory	/workspace/16.clkmgr_frequency/latest

Test location	/workspace/coverage/default/16.clkmgr_frequency_timeout.725262051
Short name	T577
Test name
Test status
Simulation time	1587649847 ps
CPU time	8.29 seconds
Started	May 12 01:22:15 PM PDT 24
Finished	May 12 01:22:24 PM PDT 24
Peak memory	200660 kb
Host	smart-f4ae1537-561f-44fb-9e24-fa0a0569b6d6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725262051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_ti meout.725262051
Directory	/workspace/16.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/16.clkmgr_idle_intersig_mubi.1793026966
Short name	T447
Test name
Test status
Simulation time	47671210 ps
CPU time	0.81 seconds
Started	May 12 01:22:16 PM PDT 24
Finished	May 12 01:22:18 PM PDT 24
Peak memory	200448 kb
Host	smart-8f1202a6-a775-4e33-973c-1c32a358e593
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793026966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_idle_intersig_mubi.1793026966
Directory	/workspace/16.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.1785609767
Short name	T746
Test name
Test status
Simulation time	71855631 ps
CPU time	0.93 seconds
Started	May 12 01:22:15 PM PDT 24
Finished	May 12 01:22:16 PM PDT 24
Peak memory	200464 kb
Host	smart-d90a6420-4410-4c97-a398-680cb8d680c0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785609767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 16.clkmgr_lc_clk_byp_req_intersig_mubi.1785609767
Directory	/workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.194146552
Short name	T301
Test name
Test status
Simulation time	26705584 ps
CPU time	0.88 seconds
Started	May 12 01:22:18 PM PDT 24
Finished	May 12 01:22:19 PM PDT 24
Peak memory	200460 kb
Host	smart-ad3259c4-d4a5-4181-824e-317b0347cbd1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194146552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.clkmgr_lc_ctrl_intersig_mubi.194146552
Directory	/workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/16.clkmgr_peri.2607849133
Short name	T457
Test name
Test status
Simulation time	40037567 ps
CPU time	0.78 seconds
Started	May 12 01:22:16 PM PDT 24
Finished	May 12 01:22:17 PM PDT 24
Peak memory	200248 kb
Host	smart-c4106b4f-128c-48e1-a995-1b7a0178cb30
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607849133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.2607849133
Directory	/workspace/16.clkmgr_peri/latest

Test location	/workspace/coverage/default/16.clkmgr_regwen.2163788494
Short name	T662
Test name
Test status
Simulation time	678082470 ps
CPU time	3.14 seconds
Started	May 12 01:22:14 PM PDT 24
Finished	May 12 01:22:17 PM PDT 24
Peak memory	200676 kb
Host	smart-ad66f80e-2974-44d0-bf46-46c4e66f11a9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163788494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.2163788494
Directory	/workspace/16.clkmgr_regwen/latest

Test location	/workspace/coverage/default/16.clkmgr_smoke.352020610
Short name	T251
Test name
Test status
Simulation time	37471231 ps
CPU time	0.87 seconds
Started	May 12 01:22:14 PM PDT 24
Finished	May 12 01:22:15 PM PDT 24
Peak memory	200480 kb
Host	smart-8226fcc9-9fe9-4706-b787-d57249009b6c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352020610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.352020610
Directory	/workspace/16.clkmgr_smoke/latest

Test location	/workspace/coverage/default/16.clkmgr_stress_all.3179772764
Short name	T707
Test name
Test status
Simulation time	9252023490 ps
CPU time	46 seconds
Started	May 12 01:22:17 PM PDT 24
Finished	May 12 01:23:03 PM PDT 24
Peak memory	201184 kb
Host	smart-80f94586-7b54-4561-a189-1f84bcc449e3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179772764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all.3179772764
Directory	/workspace/16.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.1171774014
Short name	T698
Test name
Test status
Simulation time	32058932052 ps
CPU time	424.32 seconds
Started	May 12 01:22:13 PM PDT 24
Finished	May 12 01:29:18 PM PDT 24
Peak memory	217352 kb
Host	smart-d8e468b3-3c17-429b-b6c3-ec49c92eadd4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1171774014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.1171774014
Directory	/workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.clkmgr_trans.3465649017
Short name	T606
Test name
Test status
Simulation time	17764639 ps
CPU time	0.77 seconds
Started	May 12 01:22:12 PM PDT 24
Finished	May 12 01:22:13 PM PDT 24
Peak memory	200420 kb
Host	smart-2856e7d9-30c7-4f5c-9010-26093ad7a3d7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465649017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.3465649017
Directory	/workspace/16.clkmgr_trans/latest

Test location	/workspace/coverage/default/17.clkmgr_alert_test.3410173335
Short name	T727
Test name
Test status
Simulation time	67689164 ps
CPU time	0.85 seconds
Started	May 12 01:22:23 PM PDT 24
Finished	May 12 01:22:24 PM PDT 24
Peak memory	200584 kb
Host	smart-4b59a110-ebef-40b8-bb4c-18d83d7fd3cc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410173335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk mgr_alert_test.3410173335
Directory	/workspace/17.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.1923458450
Short name	T111
Test name
Test status
Simulation time	25957107 ps
CPU time	0.86 seconds
Started	May 12 01:22:24 PM PDT 24
Finished	May 12 01:22:26 PM PDT 24
Peak memory	200480 kb
Host	smart-42acbecf-ea82-40fb-945b-d3d4a60f223e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923458450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_handshake_intersig_mubi.1923458450
Directory	/workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_clk_status.1712083179
Short name	T757
Test name
Test status
Simulation time	38926820 ps
CPU time	0.77 seconds
Started	May 12 01:22:25 PM PDT 24
Finished	May 12 01:22:27 PM PDT 24
Peak memory	199508 kb
Host	smart-3f8d6a60-ec01-4e62-88d8-641ab0e0d4f7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712083179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.1712083179
Directory	/workspace/17.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/17.clkmgr_div_intersig_mubi.1764935874
Short name	T518
Test name
Test status
Simulation time	29032114 ps
CPU time	1 seconds
Started	May 12 01:22:26 PM PDT 24
Finished	May 12 01:22:28 PM PDT 24
Peak memory	200508 kb
Host	smart-d4083075-a77f-4059-aea2-088dd30d5de4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764935874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_div_intersig_mubi.1764935874
Directory	/workspace/17.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_extclk.4046257751
Short name	T574
Test name
Test status
Simulation time	12412301 ps
CPU time	0.7 seconds
Started	May 12 01:22:26 PM PDT 24
Finished	May 12 01:22:28 PM PDT 24
Peak memory	200460 kb
Host	smart-31cfe541-82a2-4a9e-bf2e-3e62606eb0b3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046257751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.4046257751
Directory	/workspace/17.clkmgr_extclk/latest

Test location	/workspace/coverage/default/17.clkmgr_frequency.4119644994
Short name	T278
Test name
Test status
Simulation time	2252599918 ps
CPU time	9.79 seconds
Started	May 12 01:22:25 PM PDT 24
Finished	May 12 01:22:36 PM PDT 24
Peak memory	200784 kb
Host	smart-ad0c341a-728b-402a-9328-03e3ea7c297b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119644994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.4119644994
Directory	/workspace/17.clkmgr_frequency/latest

Test location	/workspace/coverage/default/17.clkmgr_frequency_timeout.2749755755
Short name	T313
Test name
Test status
Simulation time	263478491 ps
CPU time	1.94 seconds
Started	May 12 01:22:24 PM PDT 24
Finished	May 12 01:22:27 PM PDT 24
Peak memory	200480 kb
Host	smart-c3420cd3-a9bc-4de0-8ebd-7502ee7a0fe3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749755755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t imeout.2749755755
Directory	/workspace/17.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/17.clkmgr_idle_intersig_mubi.3113553637
Short name	T373
Test name
Test status
Simulation time	92601602 ps
CPU time	0.97 seconds
Started	May 12 01:22:25 PM PDT 24
Finished	May 12 01:22:27 PM PDT 24
Peak memory	200480 kb
Host	smart-16c0afa9-c56b-4582-9483-82a55deea138
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113553637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_idle_intersig_mubi.3113553637
Directory	/workspace/17.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.4162390946
Short name	T403
Test name
Test status
Simulation time	23693071 ps
CPU time	0.83 seconds
Started	May 12 01:22:24 PM PDT 24
Finished	May 12 01:22:26 PM PDT 24
Peak memory	200504 kb
Host	smart-8fc80ed3-c9f2-4999-95f4-9e7f291c5483
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162390946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 17.clkmgr_lc_clk_byp_req_intersig_mubi.4162390946
Directory	/workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.3318763227
Short name	T731
Test name
Test status
Simulation time	101680877 ps
CPU time	1.08 seconds
Started	May 12 01:22:25 PM PDT 24
Finished	May 12 01:22:27 PM PDT 24
Peak memory	200476 kb
Host	smart-6802b65b-a416-48bb-a17e-7f06939ab218
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318763227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 17.clkmgr_lc_ctrl_intersig_mubi.3318763227
Directory	/workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/17.clkmgr_peri.3604491538
Short name	T658
Test name
Test status
Simulation time	27482588 ps
CPU time	0.8 seconds
Started	May 12 01:22:23 PM PDT 24
Finished	May 12 01:22:25 PM PDT 24
Peak memory	200228 kb
Host	smart-936657fa-a009-432a-8147-3fdfd6f499ca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604491538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.3604491538
Directory	/workspace/17.clkmgr_peri/latest

Test location	/workspace/coverage/default/17.clkmgr_regwen.3207557157
Short name	T852
Test name
Test status
Simulation time	1131197250 ps
CPU time	4.83 seconds
Started	May 12 01:22:27 PM PDT 24
Finished	May 12 01:22:33 PM PDT 24
Peak memory	200688 kb
Host	smart-77394d65-6794-4670-b435-4dfebe85bf6e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207557157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.3207557157
Directory	/workspace/17.clkmgr_regwen/latest

Test location	/workspace/coverage/default/17.clkmgr_smoke.2004670005
Short name	T710
Test name
Test status
Simulation time	102552473 ps
CPU time	1.05 seconds
Started	May 12 01:22:23 PM PDT 24
Finished	May 12 01:22:24 PM PDT 24
Peak memory	200480 kb
Host	smart-b5ba0926-8bd7-4bf1-9961-162f0ffe5a91
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004670005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.2004670005
Directory	/workspace/17.clkmgr_smoke/latest

Test location	/workspace/coverage/default/17.clkmgr_stress_all.3268606177
Short name	T712
Test name
Test status
Simulation time	4394070932 ps
CPU time	29.01 seconds
Started	May 12 01:22:24 PM PDT 24
Finished	May 12 01:22:54 PM PDT 24
Peak memory	200864 kb
Host	smart-c4a4ffe7-92a7-4a4f-a288-4b6842349809
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268606177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all.3268606177
Directory	/workspace/17.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.1670271496
Short name	T806
Test name
Test status
Simulation time	58829848649 ps
CPU time	615.12 seconds
Started	May 12 01:22:25 PM PDT 24
Finished	May 12 01:32:41 PM PDT 24
Peak memory	209176 kb
Host	smart-79ebf71c-dde2-46b1-8c58-82dd28252a8c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1670271496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.1670271496
Directory	/workspace/17.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.clkmgr_trans.4060986798
Short name	T66
Test name
Test status
Simulation time	23202552 ps
CPU time	0.86 seconds
Started	May 12 01:22:24 PM PDT 24
Finished	May 12 01:22:26 PM PDT 24
Peak memory	200472 kb
Host	smart-2452c379-25fb-4599-ba07-8e06bcd01967
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060986798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.4060986798
Directory	/workspace/17.clkmgr_trans/latest

Test location	/workspace/coverage/default/18.clkmgr_alert_test.3186677853
Short name	T61
Test name
Test status
Simulation time	49672688 ps
CPU time	0.8 seconds
Started	May 12 01:22:22 PM PDT 24
Finished	May 12 01:22:24 PM PDT 24
Peak memory	200596 kb
Host	smart-eda203a1-c8c1-48cd-939c-2b44ff0a0cbf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186677853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk mgr_alert_test.3186677853
Directory	/workspace/18.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.90026503
Short name	T361
Test name
Test status
Simulation time	14560408 ps
CPU time	0.74 seconds
Started	May 12 01:22:23 PM PDT 24
Finished	May 12 01:22:24 PM PDT 24
Peak memory	200452 kb
Host	smart-0c471812-7b9e-48f7-878b-49e20f681cd8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90026503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.clkmgr_clk_handshake_intersig_mubi.90026503
Directory	/workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_clk_status.2486626998
Short name	T8
Test name
Test status
Simulation time	23893687 ps
CPU time	0.71 seconds
Started	May 12 01:22:25 PM PDT 24
Finished	May 12 01:22:26 PM PDT 24
Peak memory	199552 kb
Host	smart-d2c1cefa-38ea-4149-be25-969b93b700c0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486626998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.2486626998
Directory	/workspace/18.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/18.clkmgr_div_intersig_mubi.726445191
Short name	T381
Test name
Test status
Simulation time	35124520 ps
CPU time	0.87 seconds
Started	May 12 01:22:24 PM PDT 24
Finished	May 12 01:22:26 PM PDT 24
Peak memory	200400 kb
Host	smart-7efd2b1e-205b-424f-a338-644b960aa499
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726445191 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.clkmgr_div_intersig_mubi.726445191
Directory	/workspace/18.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_extclk.104198593
Short name	T348
Test name
Test status
Simulation time	38041904 ps
CPU time	0.87 seconds
Started	May 12 01:22:23 PM PDT 24
Finished	May 12 01:22:25 PM PDT 24
Peak memory	200452 kb
Host	smart-22bb7e7c-d23a-4ad5-8012-c9d4434b1a10
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104198593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.104198593
Directory	/workspace/18.clkmgr_extclk/latest

Test location	/workspace/coverage/default/18.clkmgr_frequency.3374658453
Short name	T405
Test name
Test status
Simulation time	917327237 ps
CPU time	7.15 seconds
Started	May 12 01:22:26 PM PDT 24
Finished	May 12 01:22:34 PM PDT 24
Peak memory	200552 kb
Host	smart-573c33aa-7fd2-4c0a-9a64-e3966ffa6c17
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374658453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.3374658453
Directory	/workspace/18.clkmgr_frequency/latest

Test location	/workspace/coverage/default/18.clkmgr_frequency_timeout.3923698902
Short name	T768
Test name
Test status
Simulation time	2182113929 ps
CPU time	11.29 seconds
Started	May 12 01:22:24 PM PDT 24
Finished	May 12 01:22:37 PM PDT 24
Peak memory	200912 kb
Host	smart-53b4968d-b819-41b7-8065-e4a00698af69
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923698902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t imeout.3923698902
Directory	/workspace/18.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/18.clkmgr_idle_intersig_mubi.1447328826
Short name	T345
Test name
Test status
Simulation time	34744695 ps
CPU time	1.03 seconds
Started	May 12 01:22:26 PM PDT 24
Finished	May 12 01:22:28 PM PDT 24
Peak memory	200380 kb
Host	smart-b7f9eddf-3fe5-4224-8cea-f1bc0edb9981
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447328826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_idle_intersig_mubi.1447328826
Directory	/workspace/18.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.88203152
Short name	T217
Test name
Test status
Simulation time	21755852 ps
CPU time	0.88 seconds
Started	May 12 01:22:24 PM PDT 24
Finished	May 12 01:22:26 PM PDT 24
Peak memory	200504 kb
Host	smart-f3f3bf2a-4e1a-4025-a771-99c3bb29a99c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88203152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_clk_byp_req_intersig_mubi.88203152
Directory	/workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.4284059317
Short name	T550
Test name
Test status
Simulation time	60305857 ps
CPU time	0.88 seconds
Started	May 12 01:22:26 PM PDT 24
Finished	May 12 01:22:28 PM PDT 24
Peak memory	200524 kb
Host	smart-a3b8fc69-e15d-45bb-baa3-c7957215564e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284059317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 18.clkmgr_lc_ctrl_intersig_mubi.4284059317
Directory	/workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/18.clkmgr_peri.703928783
Short name	T198
Test name
Test status
Simulation time	47609563 ps
CPU time	0.82 seconds
Started	May 12 01:22:24 PM PDT 24
Finished	May 12 01:22:26 PM PDT 24
Peak memory	200332 kb
Host	smart-91282af4-6d61-4875-bb4a-936d03d0cc37
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703928783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.703928783
Directory	/workspace/18.clkmgr_peri/latest

Test location	/workspace/coverage/default/18.clkmgr_regwen.3162687574
Short name	T165
Test name
Test status
Simulation time	1490398358 ps
CPU time	4.95 seconds
Started	May 12 01:22:25 PM PDT 24
Finished	May 12 01:22:31 PM PDT 24
Peak memory	200656 kb
Host	smart-e7aaadea-78fa-47ba-aa8a-bd6e421a28bc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162687574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.3162687574
Directory	/workspace/18.clkmgr_regwen/latest

Test location	/workspace/coverage/default/18.clkmgr_smoke.3221906455
Short name	T157
Test name
Test status
Simulation time	80493441 ps
CPU time	1.02 seconds
Started	May 12 01:22:25 PM PDT 24
Finished	May 12 01:22:27 PM PDT 24
Peak memory	200512 kb
Host	smart-a37e1168-4342-4e7a-9a9e-15ed333ece36
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221906455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.3221906455
Directory	/workspace/18.clkmgr_smoke/latest

Test location	/workspace/coverage/default/18.clkmgr_stress_all.183076404
Short name	T718
Test name
Test status
Simulation time	40922352 ps
CPU time	0.84 seconds
Started	May 12 01:22:26 PM PDT 24
Finished	May 12 01:22:27 PM PDT 24
Peak memory	200312 kb
Host	smart-74d0acb0-df8b-4fb6-9e45-ad024a76837c
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183076404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all.183076404
Directory	/workspace/18.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.374341263
Short name	T780
Test name
Test status
Simulation time	24063302970 ps
CPU time	345.39 seconds
Started	May 12 01:22:27 PM PDT 24
Finished	May 12 01:28:14 PM PDT 24
Peak memory	209208 kb
Host	smart-1f1d372e-7e92-4470-9db8-d194dd50bbfc
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=374341263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.374341263
Directory	/workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.clkmgr_trans.2994092054
Short name	T815
Test name
Test status
Simulation time	51849723 ps
CPU time	0.93 seconds
Started	May 12 01:22:25 PM PDT 24
Finished	May 12 01:22:27 PM PDT 24
Peak memory	200428 kb
Host	smart-be624de8-570f-4ba6-bea5-1f0a7f869db9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994092054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.2994092054
Directory	/workspace/18.clkmgr_trans/latest

Test location	/workspace/coverage/default/19.clkmgr_alert_test.825173720
Short name	T725
Test name
Test status
Simulation time	22291019 ps
CPU time	0.8 seconds
Started	May 12 01:22:29 PM PDT 24
Finished	May 12 01:22:30 PM PDT 24
Peak memory	200580 kb
Host	smart-4a81d7ab-3432-4b1a-999d-651df636210a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825173720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkm gr_alert_test.825173720
Directory	/workspace/19.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.1288822500
Short name	T330
Test name
Test status
Simulation time	135824505 ps
CPU time	1.07 seconds
Started	May 12 01:22:29 PM PDT 24
Finished	May 12 01:22:31 PM PDT 24
Peak memory	200700 kb
Host	smart-57b24c31-7b7b-43cc-832f-faf31588cd88
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288822500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_handshake_intersig_mubi.1288822500
Directory	/workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_clk_status.364278558
Short name	T178
Test name
Test status
Simulation time	12918654 ps
CPU time	0.68 seconds
Started	May 12 01:22:26 PM PDT 24
Finished	May 12 01:22:27 PM PDT 24
Peak memory	199556 kb
Host	smart-76f98b8f-6d5c-4d23-8484-74bcd76f2469
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364278558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.364278558
Directory	/workspace/19.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/19.clkmgr_div_intersig_mubi.2161151706
Short name	T656
Test name
Test status
Simulation time	22649379 ps
CPU time	0.82 seconds
Started	May 12 01:22:28 PM PDT 24
Finished	May 12 01:22:29 PM PDT 24
Peak memory	200484 kb
Host	smart-8c6eb0b8-35b7-4e15-9039-ab16e730cd99
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161151706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_div_intersig_mubi.2161151706
Directory	/workspace/19.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_extclk.1606797113
Short name	T257
Test name
Test status
Simulation time	23121060 ps
CPU time	0.8 seconds
Started	May 12 01:22:24 PM PDT 24
Finished	May 12 01:22:26 PM PDT 24
Peak memory	200512 kb
Host	smart-6f4ed8ab-ee8b-4d51-a74d-4a2d9f7c0dbd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606797113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.1606797113
Directory	/workspace/19.clkmgr_extclk/latest

Test location	/workspace/coverage/default/19.clkmgr_frequency.1343096945
Short name	T668
Test name
Test status
Simulation time	858286922 ps
CPU time	4.11 seconds
Started	May 12 01:22:27 PM PDT 24
Finished	May 12 01:22:32 PM PDT 24
Peak memory	200524 kb
Host	smart-d5502639-fb15-42d1-a0b6-5ccdab562958
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343096945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.1343096945
Directory	/workspace/19.clkmgr_frequency/latest

Test location	/workspace/coverage/default/19.clkmgr_frequency_timeout.2546189990
Short name	T777
Test name
Test status
Simulation time	753878380 ps
CPU time	3.57 seconds
Started	May 12 01:22:27 PM PDT 24
Finished	May 12 01:22:31 PM PDT 24
Peak memory	200580 kb
Host	smart-14ab6144-7477-47dc-95e1-925977c4c193
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546189990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t imeout.2546189990
Directory	/workspace/19.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/19.clkmgr_idle_intersig_mubi.1299221195
Short name	T448
Test name
Test status
Simulation time	78543777 ps
CPU time	1.13 seconds
Started	May 12 01:22:24 PM PDT 24
Finished	May 12 01:22:26 PM PDT 24
Peak memory	200424 kb
Host	smart-6f66c054-d0d2-4bfc-81e5-8960b516188f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299221195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_idle_intersig_mubi.1299221195
Directory	/workspace/19.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.678303896
Short name	T353
Test name
Test status
Simulation time	60387396 ps
CPU time	0.93 seconds
Started	May 12 01:22:23 PM PDT 24
Finished	May 12 01:22:25 PM PDT 24
Peak memory	200488 kb
Host	smart-3b8be181-0c24-4fe0-a501-d500316adc7b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678303896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.clkmgr_lc_clk_byp_req_intersig_mubi.678303896
Directory	/workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.3447099458
Short name	T805
Test name
Test status
Simulation time	26440242 ps
CPU time	0.88 seconds
Started	May 12 01:22:28 PM PDT 24
Finished	May 12 01:22:29 PM PDT 24
Peak memory	200464 kb
Host	smart-4adc64c1-1c35-43c5-a6ff-f8897917bf71
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447099458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 19.clkmgr_lc_ctrl_intersig_mubi.3447099458
Directory	/workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/19.clkmgr_peri.3585995652
Short name	T752
Test name
Test status
Simulation time	18195523 ps
CPU time	0.77 seconds
Started	May 12 01:22:24 PM PDT 24
Finished	May 12 01:22:26 PM PDT 24
Peak memory	200316 kb
Host	smart-76680eac-7549-4862-b2eb-64fb7917d4fc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585995652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.3585995652
Directory	/workspace/19.clkmgr_peri/latest

Test location	/workspace/coverage/default/19.clkmgr_regwen.524355484
Short name	T730
Test name
Test status
Simulation time	924535985 ps
CPU time	5.43 seconds
Started	May 12 01:22:28 PM PDT 24
Finished	May 12 01:22:34 PM PDT 24
Peak memory	200600 kb
Host	smart-4e6b295d-5c8d-4b90-beb3-6e5aef3f1120
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524355484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.524355484
Directory	/workspace/19.clkmgr_regwen/latest

Test location	/workspace/coverage/default/19.clkmgr_smoke.1834019786
Short name	T762
Test name
Test status
Simulation time	22897979 ps
CPU time	0.81 seconds
Started	May 12 01:22:27 PM PDT 24
Finished	May 12 01:22:29 PM PDT 24
Peak memory	200532 kb
Host	smart-11263e6f-3c5f-4249-8943-f9f063d13ce1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834019786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.1834019786
Directory	/workspace/19.clkmgr_smoke/latest

Test location	/workspace/coverage/default/19.clkmgr_stress_all.450507754
Short name	T587
Test name
Test status
Simulation time	11900950056 ps
CPU time	39.38 seconds
Started	May 12 01:22:29 PM PDT 24
Finished	May 12 01:23:10 PM PDT 24
Peak memory	200904 kb
Host	smart-d84234f6-98a9-4f8d-99d2-36b0585c0bbb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450507754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all.450507754
Directory	/workspace/19.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/19.clkmgr_stress_all_with_rand_reset.133042031
Short name	T39
Test name
Test status
Simulation time	245897127830 ps
CPU time	1364.06 seconds
Started	May 12 01:22:31 PM PDT 24
Finished	May 12 01:45:16 PM PDT 24
Peak memory	209452 kb
Host	smart-3d1c621c-7c39-41af-a711-065a39706edd
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=133042031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.133042031
Directory	/workspace/19.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.clkmgr_trans.3282935541
Short name	T244
Test name
Test status
Simulation time	34862007 ps
CPU time	0.95 seconds
Started	May 12 01:22:24 PM PDT 24
Finished	May 12 01:22:26 PM PDT 24
Peak memory	200448 kb
Host	smart-72e1b29e-bc79-48ca-b1e9-4a2295ceaf7e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282935541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.3282935541
Directory	/workspace/19.clkmgr_trans/latest

Test location	/workspace/coverage/default/2.clkmgr_alert_test.1469305642
Short name	T369
Test name
Test status
Simulation time	53916250 ps
CPU time	0.89 seconds
Started	May 12 01:21:27 PM PDT 24
Finished	May 12 01:21:28 PM PDT 24
Peak memory	200524 kb
Host	smart-e1079baa-883c-496a-be5f-973081dcf90b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469305642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm gr_alert_test.1469305642
Directory	/workspace/2.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.2528048772
Short name	T300
Test name
Test status
Simulation time	22482997 ps
CPU time	0.74 seconds
Started	May 12 01:21:31 PM PDT 24
Finished	May 12 01:21:33 PM PDT 24
Peak memory	200516 kb
Host	smart-ec41b865-6e59-4f15-91cf-d9c35fa21eee
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528048772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_handshake_intersig_mubi.2528048772
Directory	/workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_clk_status.4185076135
Short name	T27
Test name
Test status
Simulation time	109727757 ps
CPU time	0.93 seconds
Started	May 12 01:21:21 PM PDT 24
Finished	May 12 01:21:22 PM PDT 24
Peak memory	200244 kb
Host	smart-63c0e8ad-de85-4cf9-a1e7-2bf7018d6c89
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185076135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.4185076135
Directory	/workspace/2.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/2.clkmgr_div_intersig_mubi.1514416575
Short name	T342
Test name
Test status
Simulation time	24391327 ps
CPU time	0.88 seconds
Started	May 12 01:21:31 PM PDT 24
Finished	May 12 01:21:32 PM PDT 24
Peak memory	200508 kb
Host	smart-30784bfb-b9b0-4a35-80aa-dc47648d093c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514416575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_div_intersig_mubi.1514416575
Directory	/workspace/2.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_extclk.3222935183
Short name	T432
Test name
Test status
Simulation time	48202888 ps
CPU time	0.84 seconds
Started	May 12 01:21:19 PM PDT 24
Finished	May 12 01:21:20 PM PDT 24
Peak memory	200700 kb
Host	smart-cfdebef1-fb42-45eb-80c0-208b690ee056
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222935183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.3222935183
Directory	/workspace/2.clkmgr_extclk/latest

Test location	/workspace/coverage/default/2.clkmgr_frequency.745790177
Short name	T492
Test name
Test status
Simulation time	1062068045 ps
CPU time	4.87 seconds
Started	May 12 01:21:22 PM PDT 24
Finished	May 12 01:21:27 PM PDT 24
Peak memory	200512 kb
Host	smart-9849451c-3946-4b8b-ac18-d136d0dfb31f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745790177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.745790177
Directory	/workspace/2.clkmgr_frequency/latest

Test location	/workspace/coverage/default/2.clkmgr_frequency_timeout.2219860701
Short name	T245
Test name
Test status
Simulation time	2056454882 ps
CPU time	14.41 seconds
Started	May 12 01:21:22 PM PDT 24
Finished	May 12 01:21:37 PM PDT 24
Peak memory	200800 kb
Host	smart-ddc632b1-94e1-4bf0-b60c-6bf0b94a7a15
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219860701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti meout.2219860701
Directory	/workspace/2.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/2.clkmgr_idle_intersig_mubi.1922731731
Short name	T708
Test name
Test status
Simulation time	15494341 ps
CPU time	0.74 seconds
Started	May 12 01:21:20 PM PDT 24
Finished	May 12 01:21:21 PM PDT 24
Peak memory	200448 kb
Host	smart-9d4a0ee8-87b9-48de-854f-9a554500ab5f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922731731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_idle_intersig_mubi.1922731731
Directory	/workspace/2.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.1069687921
Short name	T334
Test name
Test status
Simulation time	111632413 ps
CPU time	1.13 seconds
Started	May 12 01:21:31 PM PDT 24
Finished	May 12 01:21:33 PM PDT 24
Peak memory	200508 kb
Host	smart-4d33db56-ca41-4214-bfa3-447b43258920
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069687921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.clkmgr_lc_clk_byp_req_intersig_mubi.1069687921
Directory	/workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.2880612550
Short name	T202
Test name
Test status
Simulation time	41277703 ps
CPU time	0.84 seconds
Started	May 12 01:21:23 PM PDT 24
Finished	May 12 01:21:24 PM PDT 24
Peak memory	200552 kb
Host	smart-bbd0df12-5502-48ff-a51f-849431354c1b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880612550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.clkmgr_lc_ctrl_intersig_mubi.2880612550
Directory	/workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/2.clkmgr_peri.1816141092
Short name	T798
Test name
Test status
Simulation time	17477176 ps
CPU time	0.73 seconds
Started	May 12 01:21:22 PM PDT 24
Finished	May 12 01:21:23 PM PDT 24
Peak memory	200296 kb
Host	smart-70e6f683-1c37-4e52-b257-3479f38f4c80
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816141092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.1816141092
Directory	/workspace/2.clkmgr_peri/latest

Test location	/workspace/coverage/default/2.clkmgr_regwen.2309914163
Short name	T169
Test name
Test status
Simulation time	1302034753 ps
CPU time	4.82 seconds
Started	May 12 01:21:26 PM PDT 24
Finished	May 12 01:21:31 PM PDT 24
Peak memory	200620 kb
Host	smart-6d8eda7e-993c-4dda-905b-2215dc544aad
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309914163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.2309914163
Directory	/workspace/2.clkmgr_regwen/latest

Test location	/workspace/coverage/default/2.clkmgr_smoke.3686225713
Short name	T45
Test name
Test status
Simulation time	17172492 ps
CPU time	0.8 seconds
Started	May 12 01:21:18 PM PDT 24
Finished	May 12 01:21:19 PM PDT 24
Peak memory	200440 kb
Host	smart-6ea5f2ac-54e0-4ae9-bb48-974135851afd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686225713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.3686225713
Directory	/workspace/2.clkmgr_smoke/latest

Test location	/workspace/coverage/default/2.clkmgr_stress_all.3695278870
Short name	T517
Test name
Test status
Simulation time	2783627586 ps
CPU time	9.94 seconds
Started	May 12 01:21:29 PM PDT 24
Finished	May 12 01:21:39 PM PDT 24
Peak memory	200852 kb
Host	smart-21e8361d-c8ad-4eb6-b4f0-f78870e34653
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695278870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all.3695278870
Directory	/workspace/2.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/2.clkmgr_stress_all_with_rand_reset.118914751
Short name	T17
Test name
Test status
Simulation time	18004024121 ps
CPU time	282.11 seconds
Started	May 12 01:21:26 PM PDT 24
Finished	May 12 01:26:08 PM PDT 24
Peak memory	209252 kb
Host	smart-7403972f-6bf1-43de-b7e8-4ada21933b69
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=118914751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.118914751
Directory	/workspace/2.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.clkmgr_trans.2064260821
Short name	T586
Test name
Test status
Simulation time	94889511 ps
CPU time	1.17 seconds
Started	May 12 01:21:22 PM PDT 24
Finished	May 12 01:21:24 PM PDT 24
Peak memory	200388 kb
Host	smart-b00b419a-97ed-43a7-94be-dd01d935ee60
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064260821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.2064260821
Directory	/workspace/2.clkmgr_trans/latest

Test location	/workspace/coverage/default/20.clkmgr_alert_test.3872932624
Short name	T511
Test name
Test status
Simulation time	135835905 ps
CPU time	1.02 seconds
Started	May 12 01:22:26 PM PDT 24
Finished	May 12 01:22:28 PM PDT 24
Peak memory	200580 kb
Host	smart-a8d391ec-f3e9-492a-8690-d51f04c1bfc5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872932624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk mgr_alert_test.3872932624
Directory	/workspace/20.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.1422594176
Short name	T617
Test name
Test status
Simulation time	12518805 ps
CPU time	0.74 seconds
Started	May 12 01:22:36 PM PDT 24
Finished	May 12 01:22:38 PM PDT 24
Peak memory	200716 kb
Host	smart-221e1e78-d62a-491d-98bf-c02822aa2c8f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422594176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_handshake_intersig_mubi.1422594176
Directory	/workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_clk_status.4144766211
Short name	T291
Test name
Test status
Simulation time	71513612 ps
CPU time	0.8 seconds
Started	May 12 01:22:30 PM PDT 24
Finished	May 12 01:22:31 PM PDT 24
Peak memory	199516 kb
Host	smart-0c0fb803-372e-4000-b065-3046429f523c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144766211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.4144766211
Directory	/workspace/20.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/20.clkmgr_div_intersig_mubi.1377709185
Short name	T292
Test name
Test status
Simulation time	38718025 ps
CPU time	0.81 seconds
Started	May 12 01:22:29 PM PDT 24
Finished	May 12 01:22:30 PM PDT 24
Peak memory	200516 kb
Host	smart-b26224e0-3bbc-42a8-90a3-8457000ad7f3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377709185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_div_intersig_mubi.1377709185
Directory	/workspace/20.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_extclk.1510554013
Short name	T695
Test name
Test status
Simulation time	130904259 ps
CPU time	1.17 seconds
Started	May 12 01:22:29 PM PDT 24
Finished	May 12 01:22:30 PM PDT 24
Peak memory	200536 kb
Host	smart-76862cd3-8a75-4d61-915c-99f58b4a5b12
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510554013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.1510554013
Directory	/workspace/20.clkmgr_extclk/latest

Test location	/workspace/coverage/default/20.clkmgr_frequency.3083217353
Short name	T505
Test name
Test status
Simulation time	1640393902 ps
CPU time	12.83 seconds
Started	May 12 01:22:32 PM PDT 24
Finished	May 12 01:22:45 PM PDT 24
Peak memory	200568 kb
Host	smart-8cb8bad3-af33-4d61-a07a-df8fd623cec2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083217353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.3083217353
Directory	/workspace/20.clkmgr_frequency/latest

Test location	/workspace/coverage/default/20.clkmgr_frequency_timeout.2575795492
Short name	T703
Test name
Test status
Simulation time	2296887994 ps
CPU time	15.34 seconds
Started	May 12 01:22:31 PM PDT 24
Finished	May 12 01:22:47 PM PDT 24
Peak memory	201072 kb
Host	smart-e7978f62-40f5-49fa-8bca-de16c84d8e5a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575795492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t imeout.2575795492
Directory	/workspace/20.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/20.clkmgr_idle_intersig_mubi.2637515829
Short name	T20
Test name
Test status
Simulation time	77298680 ps
CPU time	0.96 seconds
Started	May 12 01:22:26 PM PDT 24
Finished	May 12 01:22:28 PM PDT 24
Peak memory	200500 kb
Host	smart-63ea76c3-e872-4ec6-932d-6cb73265d5dc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637515829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_idle_intersig_mubi.2637515829
Directory	/workspace/20.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.3967498674
Short name	T409
Test name
Test status
Simulation time	66093070 ps
CPU time	0.96 seconds
Started	May 12 01:22:30 PM PDT 24
Finished	May 12 01:22:32 PM PDT 24
Peak memory	200488 kb
Host	smart-f35c0d3c-a06b-4cd2-9aba-495bd3cfe2d0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967498674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 20.clkmgr_lc_clk_byp_req_intersig_mubi.3967498674
Directory	/workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.1926283234
Short name	T399
Test name
Test status
Simulation time	77597193 ps
CPU time	1.01 seconds
Started	May 12 01:22:36 PM PDT 24
Finished	May 12 01:22:38 PM PDT 24
Peak memory	200708 kb
Host	smart-aaf40ca9-3d19-406c-8092-9985e2211467
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926283234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 20.clkmgr_lc_ctrl_intersig_mubi.1926283234
Directory	/workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/20.clkmgr_peri.3547131334
Short name	T627
Test name
Test status
Simulation time	19920170 ps
CPU time	0.76 seconds
Started	May 12 01:22:30 PM PDT 24
Finished	May 12 01:22:31 PM PDT 24
Peak memory	200320 kb
Host	smart-19d7d915-62b8-4017-ac5d-aff7ae9e3b7e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547131334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.3547131334
Directory	/workspace/20.clkmgr_peri/latest

Test location	/workspace/coverage/default/20.clkmgr_regwen.3580009148
Short name	T564
Test name
Test status
Simulation time	748857627 ps
CPU time	3.02 seconds
Started	May 12 01:22:36 PM PDT 24
Finished	May 12 01:22:40 PM PDT 24
Peak memory	200776 kb
Host	smart-85303025-9cc2-4f6f-ab63-698d2106b1cc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580009148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.3580009148
Directory	/workspace/20.clkmgr_regwen/latest

Test location	/workspace/coverage/default/20.clkmgr_smoke.3687960464
Short name	T745
Test name
Test status
Simulation time	32870808 ps
CPU time	0.89 seconds
Started	May 12 01:22:35 PM PDT 24
Finished	May 12 01:22:36 PM PDT 24
Peak memory	200716 kb
Host	smart-b0bf0108-f612-4212-ac67-964fb4376b45
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687960464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.3687960464
Directory	/workspace/20.clkmgr_smoke/latest

Test location	/workspace/coverage/default/20.clkmgr_stress_all.3996795282
Short name	T391
Test name
Test status
Simulation time	7817526793 ps
CPU time	56.81 seconds
Started	May 12 01:22:31 PM PDT 24
Finished	May 12 01:23:28 PM PDT 24
Peak memory	200980 kb
Host	smart-6ee71faa-a654-4943-a3fd-ee163ff4224a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996795282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all.3996795282
Directory	/workspace/20.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.4281659370
Short name	T444
Test name
Test status
Simulation time	20709695716 ps
CPU time	368.78 seconds
Started	May 12 01:22:29 PM PDT 24
Finished	May 12 01:28:38 PM PDT 24
Peak memory	209172 kb
Host	smart-2b8af3a4-f53c-4c9d-8584-ddcbed5788a4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4281659370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.4281659370
Directory	/workspace/20.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.clkmgr_trans.1957536932
Short name	T671
Test name
Test status
Simulation time	61868854 ps
CPU time	0.89 seconds
Started	May 12 01:22:27 PM PDT 24
Finished	May 12 01:22:29 PM PDT 24
Peak memory	200432 kb
Host	smart-44321ada-25b8-4f4f-bc71-efab44212b39
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957536932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.1957536932
Directory	/workspace/20.clkmgr_trans/latest

Test location	/workspace/coverage/default/21.clkmgr_alert_test.2767813702
Short name	T318
Test name
Test status
Simulation time	17160290 ps
CPU time	0.78 seconds
Started	May 12 01:22:35 PM PDT 24
Finished	May 12 01:22:37 PM PDT 24
Peak memory	200552 kb
Host	smart-9d0bdaf3-9a5c-4078-93fb-dc128e3220af
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767813702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk mgr_alert_test.2767813702
Directory	/workspace/21.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.2832812831
Short name	T376
Test name
Test status
Simulation time	29100231 ps
CPU time	0.85 seconds
Started	May 12 01:22:34 PM PDT 24
Finished	May 12 01:22:36 PM PDT 24
Peak memory	200500 kb
Host	smart-e16b3513-ce73-4742-9f3d-cd6af3d954c0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832812831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_handshake_intersig_mubi.2832812831
Directory	/workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_clk_status.2689450864
Short name	T408
Test name
Test status
Simulation time	16519425 ps
CPU time	0.7 seconds
Started	May 12 01:22:29 PM PDT 24
Finished	May 12 01:22:31 PM PDT 24
Peak memory	199508 kb
Host	smart-d714c18d-bd33-49b3-82c8-151022ce7e48
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689450864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.2689450864
Directory	/workspace/21.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/21.clkmgr_div_intersig_mubi.4042709734
Short name	T44
Test name
Test status
Simulation time	148064676 ps
CPU time	1.18 seconds
Started	May 12 01:22:36 PM PDT 24
Finished	May 12 01:22:38 PM PDT 24
Peak memory	200488 kb
Host	smart-6ba73035-b255-4c56-9a78-bfafc80a7c3a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042709734 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_div_intersig_mubi.4042709734
Directory	/workspace/21.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_extclk.899462886
Short name	T685
Test name
Test status
Simulation time	22114847 ps
CPU time	0.82 seconds
Started	May 12 01:22:36 PM PDT 24
Finished	May 12 01:22:38 PM PDT 24
Peak memory	200708 kb
Host	smart-4c2797f3-57f8-4b41-8dd5-add738fc9f12
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899462886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.899462886
Directory	/workspace/21.clkmgr_extclk/latest

Test location	/workspace/coverage/default/21.clkmgr_frequency.1905244195
Short name	T335
Test name
Test status
Simulation time	563812308 ps
CPU time	3.42 seconds
Started	May 12 01:22:32 PM PDT 24
Finished	May 12 01:22:36 PM PDT 24
Peak memory	200800 kb
Host	smart-2701297b-2a65-4b8a-8969-9dac35b19d2f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905244195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.1905244195
Directory	/workspace/21.clkmgr_frequency/latest

Test location	/workspace/coverage/default/21.clkmgr_frequency_timeout.2499897439
Short name	T813
Test name
Test status
Simulation time	1221792018 ps
CPU time	9.45 seconds
Started	May 12 01:22:29 PM PDT 24
Finished	May 12 01:22:39 PM PDT 24
Peak memory	200808 kb
Host	smart-1caeb14c-316a-43ca-bb3c-9504affc4073
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499897439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t imeout.2499897439
Directory	/workspace/21.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/21.clkmgr_idle_intersig_mubi.3347416005
Short name	T240
Test name
Test status
Simulation time	19355570 ps
CPU time	0.72 seconds
Started	May 12 01:22:29 PM PDT 24
Finished	May 12 01:22:31 PM PDT 24
Peak memory	200412 kb
Host	smart-098db288-d236-41c8-857a-e9e99bda4faa
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347416005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_idle_intersig_mubi.3347416005
Directory	/workspace/21.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.1735413157
Short name	T696
Test name
Test status
Simulation time	41424662 ps
CPU time	0.91 seconds
Started	May 12 01:22:38 PM PDT 24
Finished	May 12 01:22:40 PM PDT 24
Peak memory	200496 kb
Host	smart-8318d088-ecaa-44be-9e50-2817839d18de
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735413157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 21.clkmgr_lc_clk_byp_req_intersig_mubi.1735413157
Directory	/workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.3238046575
Short name	T368
Test name
Test status
Simulation time	21159529 ps
CPU time	0.74 seconds
Started	May 12 01:22:34 PM PDT 24
Finished	May 12 01:22:35 PM PDT 24
Peak memory	200496 kb
Host	smart-3d94834c-7eaa-4ab9-b365-5bf156f2125f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238046575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 21.clkmgr_lc_ctrl_intersig_mubi.3238046575
Directory	/workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/21.clkmgr_peri.1372493691
Short name	T826
Test name
Test status
Simulation time	23136336 ps
CPU time	0.71 seconds
Started	May 12 01:22:29 PM PDT 24
Finished	May 12 01:22:31 PM PDT 24
Peak memory	200544 kb
Host	smart-566b4a90-dfe8-40b7-bbb2-e0fa511939ef
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372493691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.1372493691
Directory	/workspace/21.clkmgr_peri/latest

Test location	/workspace/coverage/default/21.clkmgr_regwen.3303246574
Short name	T525
Test name
Test status
Simulation time	1057699040 ps
CPU time	3.96 seconds
Started	May 12 01:22:36 PM PDT 24
Finished	May 12 01:22:41 PM PDT 24
Peak memory	200560 kb
Host	smart-3f92d582-0bdd-4b54-a0b2-6070989ffd43
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303246574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.3303246574
Directory	/workspace/21.clkmgr_regwen/latest

Test location	/workspace/coverage/default/21.clkmgr_smoke.4250876321
Short name	T787
Test name
Test status
Simulation time	26792898 ps
CPU time	0.84 seconds
Started	May 12 01:22:29 PM PDT 24
Finished	May 12 01:22:30 PM PDT 24
Peak memory	200500 kb
Host	smart-3ce95139-41f6-4e3a-9a58-8f408b38cddb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250876321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.4250876321
Directory	/workspace/21.clkmgr_smoke/latest

Test location	/workspace/coverage/default/21.clkmgr_stress_all.780961185
Short name	T803
Test name
Test status
Simulation time	5343816800 ps
CPU time	18.76 seconds
Started	May 12 01:22:34 PM PDT 24
Finished	May 12 01:22:53 PM PDT 24
Peak memory	200952 kb
Host	smart-23501708-7c59-4eef-b86f-0c4665fb0ff0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780961185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all.780961185
Directory	/workspace/21.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.506385118
Short name	T471
Test name
Test status
Simulation time	74064988237 ps
CPU time	476.26 seconds
Started	May 12 01:22:33 PM PDT 24
Finished	May 12 01:30:30 PM PDT 24
Peak memory	211208 kb
Host	smart-fbf4cf6a-c130-4519-9589-89f30b2cded0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=506385118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.506385118
Directory	/workspace/21.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.clkmgr_trans.3669287777
Short name	T479
Test name
Test status
Simulation time	315389987 ps
CPU time	1.71 seconds
Started	May 12 01:22:28 PM PDT 24
Finished	May 12 01:22:30 PM PDT 24
Peak memory	200412 kb
Host	smart-e3a0f713-cabd-4a7d-8915-f6b16f3f03cf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669287777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.3669287777
Directory	/workspace/21.clkmgr_trans/latest

Test location	/workspace/coverage/default/22.clkmgr_alert_test.3887590783
Short name	T295
Test name
Test status
Simulation time	12788584 ps
CPU time	0.73 seconds
Started	May 12 01:22:34 PM PDT 24
Finished	May 12 01:22:36 PM PDT 24
Peak memory	200488 kb
Host	smart-9413e8ea-e3d3-43d9-b0a8-24be4dea6909
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887590783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk mgr_alert_test.3887590783
Directory	/workspace/22.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.1314842078
Short name	T107
Test name
Test status
Simulation time	37702895 ps
CPU time	0.9 seconds
Started	May 12 01:22:34 PM PDT 24
Finished	May 12 01:22:36 PM PDT 24
Peak memory	200516 kb
Host	smart-44cb0fb7-4b40-4938-b961-8812879f19be
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314842078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_handshake_intersig_mubi.1314842078
Directory	/workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_clk_status.3966215901
Short name	T744
Test name
Test status
Simulation time	38989190 ps
CPU time	0.73 seconds
Started	May 12 01:22:36 PM PDT 24
Finished	May 12 01:22:38 PM PDT 24
Peak memory	199476 kb
Host	smart-f2330a8f-f288-464e-96f2-a5c8bea2cd6b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966215901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.3966215901
Directory	/workspace/22.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/22.clkmgr_div_intersig_mubi.3397053952
Short name	T311
Test name
Test status
Simulation time	29615817 ps
CPU time	0.87 seconds
Started	May 12 01:22:33 PM PDT 24
Finished	May 12 01:22:35 PM PDT 24
Peak memory	200440 kb
Host	smart-301daad6-91f0-4c05-bcf0-6cb62ea51215
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397053952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_div_intersig_mubi.3397053952
Directory	/workspace/22.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_extclk.2291094578
Short name	T726
Test name
Test status
Simulation time	24154827 ps
CPU time	0.9 seconds
Started	May 12 01:22:34 PM PDT 24
Finished	May 12 01:22:36 PM PDT 24
Peak memory	200452 kb
Host	smart-1de9199a-b4f3-4993-9ced-c265daf30ff3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291094578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.2291094578
Directory	/workspace/22.clkmgr_extclk/latest

Test location	/workspace/coverage/default/22.clkmgr_frequency.3137944072
Short name	T817
Test name
Test status
Simulation time	1754455738 ps
CPU time	13.04 seconds
Started	May 12 01:22:33 PM PDT 24
Finished	May 12 01:22:47 PM PDT 24
Peak memory	200720 kb
Host	smart-ecec7d97-7b4f-4c25-b5f2-07662b30f00d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137944072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.3137944072
Directory	/workspace/22.clkmgr_frequency/latest

Test location	/workspace/coverage/default/22.clkmgr_frequency_timeout.939771579
Short name	T818
Test name
Test status
Simulation time	1406123160 ps
CPU time	5.86 seconds
Started	May 12 01:22:36 PM PDT 24
Finished	May 12 01:22:43 PM PDT 24
Peak memory	200580 kb
Host	smart-9816abc9-a000-4074-b475-7d8932da1b21
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939771579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_ti meout.939771579
Directory	/workspace/22.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/22.clkmgr_idle_intersig_mubi.1873623757
Short name	T384
Test name
Test status
Simulation time	67634330 ps
CPU time	0.98 seconds
Started	May 12 01:22:35 PM PDT 24
Finished	May 12 01:22:37 PM PDT 24
Peak memory	200480 kb
Host	smart-6f8a5eeb-e4ee-49e6-9856-c799d6a93d47
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873623757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_idle_intersig_mubi.1873623757
Directory	/workspace/22.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.3503233133
Short name	T196
Test name
Test status
Simulation time	22400528 ps
CPU time	0.84 seconds
Started	May 12 01:22:35 PM PDT 24
Finished	May 12 01:22:37 PM PDT 24
Peak memory	200516 kb
Host	smart-a051346d-b579-47cb-b209-cc6e782cfe12
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503233133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 22.clkmgr_lc_clk_byp_req_intersig_mubi.3503233133
Directory	/workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.215867777
Short name	T364
Test name
Test status
Simulation time	31155176 ps
CPU time	0.8 seconds
Started	May 12 01:22:32 PM PDT 24
Finished	May 12 01:22:33 PM PDT 24
Peak memory	200556 kb
Host	smart-b8fcb898-193e-4e4f-822d-2246d3c844fc
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215867777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.clkmgr_lc_ctrl_intersig_mubi.215867777
Directory	/workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/22.clkmgr_peri.4126498729
Short name	T234
Test name
Test status
Simulation time	38236977 ps
CPU time	0.8 seconds
Started	May 12 01:22:33 PM PDT 24
Finished	May 12 01:22:35 PM PDT 24
Peak memory	200320 kb
Host	smart-35182c39-1686-4926-9e86-79819eed7c88
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126498729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.4126498729
Directory	/workspace/22.clkmgr_peri/latest

Test location	/workspace/coverage/default/22.clkmgr_regwen.1498609693
Short name	T419
Test name
Test status
Simulation time	978832862 ps
CPU time	5.62 seconds
Started	May 12 01:22:33 PM PDT 24
Finished	May 12 01:22:40 PM PDT 24
Peak memory	200616 kb
Host	smart-53d41f51-c977-43ba-9402-8d4e23f0d3ba
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498609693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.1498609693
Directory	/workspace/22.clkmgr_regwen/latest

Test location	/workspace/coverage/default/22.clkmgr_smoke.3451241917
Short name	T713
Test name
Test status
Simulation time	16476988 ps
CPU time	0.8 seconds
Started	May 12 01:22:33 PM PDT 24
Finished	May 12 01:22:34 PM PDT 24
Peak memory	200516 kb
Host	smart-148954a9-bde3-4cb7-8ab8-f590cae6a518
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451241917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.3451241917
Directory	/workspace/22.clkmgr_smoke/latest

Test location	/workspace/coverage/default/22.clkmgr_stress_all.450139492
Short name	T554
Test name
Test status
Simulation time	5809350534 ps
CPU time	34.35 seconds
Started	May 12 01:22:33 PM PDT 24
Finished	May 12 01:23:09 PM PDT 24
Peak memory	200932 kb
Host	smart-ce29684c-9a02-4bd2-952d-9c6b0f681f85
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450139492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all.450139492
Directory	/workspace/22.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.1130116940
Short name	T501
Test name
Test status
Simulation time	130092931061 ps
CPU time	745.42 seconds
Started	May 12 01:22:34 PM PDT 24
Finished	May 12 01:35:00 PM PDT 24
Peak memory	217388 kb
Host	smart-d88bc0d9-e3ac-4ae4-9f59-69d51c5a9589
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1130116940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.1130116940
Directory	/workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.clkmgr_trans.577694129
Short name	T246
Test name
Test status
Simulation time	33809354 ps
CPU time	0.78 seconds
Started	May 12 01:22:35 PM PDT 24
Finished	May 12 01:22:36 PM PDT 24
Peak memory	200356 kb
Host	smart-792a85c9-b74a-4d20-8228-c1da690fccfe
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577694129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.577694129
Directory	/workspace/22.clkmgr_trans/latest

Test location	/workspace/coverage/default/23.clkmgr_alert_test.2006100360
Short name	T665
Test name
Test status
Simulation time	15921349 ps
CPU time	0.73 seconds
Started	May 12 01:22:38 PM PDT 24
Finished	May 12 01:22:40 PM PDT 24
Peak memory	200520 kb
Host	smart-595074dd-732c-452d-88fa-2cb64959479c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006100360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk mgr_alert_test.2006100360
Directory	/workspace/23.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.1111927725
Short name	T296
Test name
Test status
Simulation time	14634800 ps
CPU time	0.7 seconds
Started	May 12 01:22:37 PM PDT 24
Finished	May 12 01:22:38 PM PDT 24
Peak memory	200476 kb
Host	smart-7c1268ff-3365-4760-9f0b-3283f618e374
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111927725 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_handshake_intersig_mubi.1111927725
Directory	/workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_clk_status.2586036754
Short name	T681
Test name
Test status
Simulation time	24923150 ps
CPU time	0.72 seconds
Started	May 12 01:22:36 PM PDT 24
Finished	May 12 01:22:38 PM PDT 24
Peak memory	199532 kb
Host	smart-f8253c0c-ffd3-48a7-83c2-ad5d82ccd7e5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586036754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.2586036754
Directory	/workspace/23.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/23.clkmgr_div_intersig_mubi.3492768789
Short name	T646
Test name
Test status
Simulation time	17434108 ps
CPU time	0.77 seconds
Started	May 12 01:22:39 PM PDT 24
Finished	May 12 01:22:41 PM PDT 24
Peak memory	200472 kb
Host	smart-69585cbb-120d-4e73-8a11-90e8bbae3dd8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492768789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_div_intersig_mubi.3492768789
Directory	/workspace/23.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_extclk.253148640
Short name	T684
Test name
Test status
Simulation time	50803713 ps
CPU time	0.98 seconds
Started	May 12 01:22:36 PM PDT 24
Finished	May 12 01:22:39 PM PDT 24
Peak memory	200528 kb
Host	smart-a9e9fc20-f2aa-4680-a6bb-6d6853bd669d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253148640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.253148640
Directory	/workspace/23.clkmgr_extclk/latest

Test location	/workspace/coverage/default/23.clkmgr_frequency.3381503068
Short name	T273
Test name
Test status
Simulation time	206302028 ps
CPU time	2.12 seconds
Started	May 12 01:22:38 PM PDT 24
Finished	May 12 01:22:41 PM PDT 24
Peak memory	200492 kb
Host	smart-34ae7a6a-cfb7-4d45-b259-5e12b41cee97
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381503068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.3381503068
Directory	/workspace/23.clkmgr_frequency/latest

Test location	/workspace/coverage/default/23.clkmgr_frequency_timeout.2836506842
Short name	T839
Test name
Test status
Simulation time	378425369 ps
CPU time	2.95 seconds
Started	May 12 01:22:40 PM PDT 24
Finished	May 12 01:22:43 PM PDT 24
Peak memory	200652 kb
Host	smart-a35b87e2-d467-40ab-ad03-d79746cf9161
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836506842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t imeout.2836506842
Directory	/workspace/23.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/23.clkmgr_idle_intersig_mubi.2769262332
Short name	T260
Test name
Test status
Simulation time	69401988 ps
CPU time	1.1 seconds
Started	May 12 01:22:38 PM PDT 24
Finished	May 12 01:22:40 PM PDT 24
Peak memory	200472 kb
Host	smart-ba527bdd-4b46-4a9a-af88-b707bf6e3ae1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769262332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_idle_intersig_mubi.2769262332
Directory	/workspace/23.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.1603923233
Short name	T560
Test name
Test status
Simulation time	90461066 ps
CPU time	0.98 seconds
Started	May 12 01:22:37 PM PDT 24
Finished	May 12 01:22:39 PM PDT 24
Peak memory	200508 kb
Host	smart-8a329f00-95c9-4be3-a765-ff8f2f54a4df
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603923233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 23.clkmgr_lc_clk_byp_req_intersig_mubi.1603923233
Directory	/workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.3654575507
Short name	T67
Test name
Test status
Simulation time	26116638 ps
CPU time	0.9 seconds
Started	May 12 01:22:37 PM PDT 24
Finished	May 12 01:22:39 PM PDT 24
Peak memory	200472 kb
Host	smart-c0c1a479-d327-45c8-910f-9ef36692ca10
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654575507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 23.clkmgr_lc_ctrl_intersig_mubi.3654575507
Directory	/workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/23.clkmgr_peri.412177068
Short name	T499
Test name
Test status
Simulation time	39682184 ps
CPU time	0.83 seconds
Started	May 12 01:22:39 PM PDT 24
Finished	May 12 01:22:40 PM PDT 24
Peak memory	200328 kb
Host	smart-be26c041-e030-43a9-b44e-6fd6c3f37708
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412177068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.412177068
Directory	/workspace/23.clkmgr_peri/latest

Test location	/workspace/coverage/default/23.clkmgr_regwen.3169533742
Short name	T431
Test name
Test status
Simulation time	408984165 ps
CPU time	1.87 seconds
Started	May 12 01:22:46 PM PDT 24
Finished	May 12 01:22:48 PM PDT 24
Peak memory	200644 kb
Host	smart-5e206260-56ca-4c42-ac16-be5d0bded6dc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169533742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.3169533742
Directory	/workspace/23.clkmgr_regwen/latest

Test location	/workspace/coverage/default/23.clkmgr_smoke.2319033987
Short name	T664
Test name
Test status
Simulation time	21946634 ps
CPU time	0.82 seconds
Started	May 12 01:22:34 PM PDT 24
Finished	May 12 01:22:36 PM PDT 24
Peak memory	200532 kb
Host	smart-28146866-5036-44a8-94cc-e66bebd0e14c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319033987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.2319033987
Directory	/workspace/23.clkmgr_smoke/latest

Test location	/workspace/coverage/default/23.clkmgr_stress_all.3189692929
Short name	T34
Test name
Test status
Simulation time	1087003315 ps
CPU time	5.62 seconds
Started	May 12 01:22:38 PM PDT 24
Finished	May 12 01:22:44 PM PDT 24
Peak memory	200776 kb
Host	smart-d9ee271c-db5a-4b7d-956c-9b672e24f407
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189692929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all.3189692929
Directory	/workspace/23.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.3545740463
Short name	T624
Test name
Test status
Simulation time	53520251861 ps
CPU time	783.27 seconds
Started	May 12 01:22:38 PM PDT 24
Finished	May 12 01:35:42 PM PDT 24
Peak memory	213316 kb
Host	smart-4f022c51-eea2-4f58-b867-b3fdb92ebfc1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3545740463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.3545740463
Directory	/workspace/23.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/23.clkmgr_trans.3020467038
Short name	T770
Test name
Test status
Simulation time	49697153 ps
CPU time	0.87 seconds
Started	May 12 01:22:38 PM PDT 24
Finished	May 12 01:22:40 PM PDT 24
Peak memory	200500 kb
Host	smart-f61fd12f-16d5-4988-b904-cd5915ad820b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020467038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.3020467038
Directory	/workspace/23.clkmgr_trans/latest

Test location	/workspace/coverage/default/24.clkmgr_alert_test.3508346947
Short name	T200
Test name
Test status
Simulation time	16748389 ps
CPU time	0.85 seconds
Started	May 12 01:22:40 PM PDT 24
Finished	May 12 01:22:41 PM PDT 24
Peak memory	200588 kb
Host	smart-324c4592-d6b1-44b9-b07b-2ab187b033fd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508346947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk mgr_alert_test.3508346947
Directory	/workspace/24.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.3278282235
Short name	T201
Test name
Test status
Simulation time	61551990 ps
CPU time	0.96 seconds
Started	May 12 01:22:46 PM PDT 24
Finished	May 12 01:22:47 PM PDT 24
Peak memory	200716 kb
Host	smart-8d552766-f8f6-4bf4-ac35-14cbae6524a5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278282235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_handshake_intersig_mubi.3278282235
Directory	/workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_clk_status.2873037022
Short name	T365
Test name
Test status
Simulation time	17065219 ps
CPU time	0.76 seconds
Started	May 12 01:22:45 PM PDT 24
Finished	May 12 01:22:46 PM PDT 24
Peak memory	200424 kb
Host	smart-9e3a7ae2-413d-4d30-9138-89ddedaebd9d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873037022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.2873037022
Directory	/workspace/24.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/24.clkmgr_div_intersig_mubi.3016628361
Short name	T289
Test name
Test status
Simulation time	19985461 ps
CPU time	0.82 seconds
Started	May 12 01:22:37 PM PDT 24
Finished	May 12 01:22:38 PM PDT 24
Peak memory	200504 kb
Host	smart-52a00800-08e2-4c33-ad84-60f0a931cdb0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016628361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_div_intersig_mubi.3016628361
Directory	/workspace/24.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_extclk.121018499
Short name	T177
Test name
Test status
Simulation time	52070400 ps
CPU time	0.83 seconds
Started	May 12 01:22:36 PM PDT 24
Finished	May 12 01:22:38 PM PDT 24
Peak memory	200508 kb
Host	smart-1101c4a1-73fd-46a7-8625-4501bc390568
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121018499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.121018499
Directory	/workspace/24.clkmgr_extclk/latest

Test location	/workspace/coverage/default/24.clkmgr_frequency.3914247796
Short name	T724
Test name
Test status
Simulation time	441992702 ps
CPU time	2.94 seconds
Started	May 12 01:22:39 PM PDT 24
Finished	May 12 01:22:42 PM PDT 24
Peak memory	200516 kb
Host	smart-eeb35cb1-b6a2-4354-9c1c-a02a68557b61
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914247796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.3914247796
Directory	/workspace/24.clkmgr_frequency/latest

Test location	/workspace/coverage/default/24.clkmgr_frequency_timeout.4072281270
Short name	T628
Test name
Test status
Simulation time	161188700 ps
CPU time	1.25 seconds
Started	May 12 01:22:40 PM PDT 24
Finished	May 12 01:22:42 PM PDT 24
Peak memory	200644 kb
Host	smart-d2feac73-2d90-43a5-96e5-4855bfd058a7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072281270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t imeout.4072281270
Directory	/workspace/24.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/24.clkmgr_idle_intersig_mubi.2741311883
Short name	T358
Test name
Test status
Simulation time	30806729 ps
CPU time	0.98 seconds
Started	May 12 01:22:38 PM PDT 24
Finished	May 12 01:22:40 PM PDT 24
Peak memory	200424 kb
Host	smart-a9597547-6c40-4a2e-b2d4-f310e1e11226
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741311883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_idle_intersig_mubi.2741311883
Directory	/workspace/24.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.1135812511
Short name	T43
Test name
Test status
Simulation time	29831783 ps
CPU time	0.8 seconds
Started	May 12 01:22:41 PM PDT 24
Finished	May 12 01:22:42 PM PDT 24
Peak memory	200504 kb
Host	smart-7e52a322-b3e0-4d12-a907-f0731815fa0f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135812511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 24.clkmgr_lc_clk_byp_req_intersig_mubi.1135812511
Directory	/workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.2540869428
Short name	T377
Test name
Test status
Simulation time	20057459 ps
CPU time	0.8 seconds
Started	May 12 01:22:36 PM PDT 24
Finished	May 12 01:22:38 PM PDT 24
Peak memory	200536 kb
Host	smart-3706d59c-24cf-4e92-9aea-bd171da69a7f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540869428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 24.clkmgr_lc_ctrl_intersig_mubi.2540869428
Directory	/workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/24.clkmgr_peri.3178122852
Short name	T840
Test name
Test status
Simulation time	78968388 ps
CPU time	0.91 seconds
Started	May 12 01:22:38 PM PDT 24
Finished	May 12 01:22:39 PM PDT 24
Peak memory	200288 kb
Host	smart-1c3ac6fb-3351-4deb-8d2d-e6531c654fdb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178122852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.3178122852
Directory	/workspace/24.clkmgr_peri/latest

Test location	/workspace/coverage/default/24.clkmgr_regwen.3581575799
Short name	T94
Test name
Test status
Simulation time	529925065 ps
CPU time	2.23 seconds
Started	May 12 01:22:37 PM PDT 24
Finished	May 12 01:22:40 PM PDT 24
Peak memory	200524 kb
Host	smart-ba2f3046-8c28-45ec-a554-5087ffcad8c5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581575799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.3581575799
Directory	/workspace/24.clkmgr_regwen/latest

Test location	/workspace/coverage/default/24.clkmgr_smoke.2517580897
Short name	T21
Test name
Test status
Simulation time	29118540 ps
CPU time	0.91 seconds
Started	May 12 01:22:37 PM PDT 24
Finished	May 12 01:22:39 PM PDT 24
Peak memory	200508 kb
Host	smart-2a94d2d8-5e63-429c-ac56-f02d8f108f45
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517580897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.2517580897
Directory	/workspace/24.clkmgr_smoke/latest

Test location	/workspace/coverage/default/24.clkmgr_stress_all.497865048
Short name	T97
Test name
Test status
Simulation time	9254547106 ps
CPU time	47.72 seconds
Started	May 12 01:22:40 PM PDT 24
Finished	May 12 01:23:29 PM PDT 24
Peak memory	200908 kb
Host	smart-990ec9b3-6fe1-4312-bd70-686def978258
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497865048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all.497865048
Directory	/workspace/24.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.3402987499
Short name	T367
Test name
Test status
Simulation time	119385110587 ps
CPU time	779.35 seconds
Started	May 12 01:22:38 PM PDT 24
Finished	May 12 01:35:39 PM PDT 24
Peak memory	217360 kb
Host	smart-9c42b2d9-9cde-45b9-aaec-fe7a5f90412f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3402987499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.3402987499
Directory	/workspace/24.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.clkmgr_trans.1782030732
Short name	T690
Test name
Test status
Simulation time	71296855 ps
CPU time	1.12 seconds
Started	May 12 01:22:37 PM PDT 24
Finished	May 12 01:22:39 PM PDT 24
Peak memory	200540 kb
Host	smart-369ae44e-29f4-46d1-a304-4c139544b620
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782030732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.1782030732
Directory	/workspace/24.clkmgr_trans/latest

Test location	/workspace/coverage/default/25.clkmgr_alert_test.2238825508
Short name	T228
Test name
Test status
Simulation time	144942501 ps
CPU time	1.06 seconds
Started	May 12 01:22:40 PM PDT 24
Finished	May 12 01:22:41 PM PDT 24
Peak memory	200596 kb
Host	smart-8b8a83c2-4c41-4b6d-b5fe-2b818c3cd44f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238825508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk mgr_alert_test.2238825508
Directory	/workspace/25.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.3907769202
Short name	T711
Test name
Test status
Simulation time	89917090 ps
CPU time	0.98 seconds
Started	May 12 01:22:42 PM PDT 24
Finished	May 12 01:22:43 PM PDT 24
Peak memory	200496 kb
Host	smart-39c07220-b91d-4480-b4da-a0fcdc552db2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907769202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_handshake_intersig_mubi.3907769202
Directory	/workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_clk_status.1204661408
Short name	T785
Test name
Test status
Simulation time	44327713 ps
CPU time	0.77 seconds
Started	May 12 01:22:45 PM PDT 24
Finished	May 12 01:22:46 PM PDT 24
Peak memory	199500 kb
Host	smart-bdd23503-f3ae-4beb-8fe2-388bad8b8ae3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204661408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.1204661408
Directory	/workspace/25.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/25.clkmgr_div_intersig_mubi.3130379745
Short name	T418
Test name
Test status
Simulation time	46009727 ps
CPU time	0.97 seconds
Started	May 12 01:22:44 PM PDT 24
Finished	May 12 01:22:45 PM PDT 24
Peak memory	200504 kb
Host	smart-35f468fe-fba1-441f-bc90-f725c89de41c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130379745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_div_intersig_mubi.3130379745
Directory	/workspace/25.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_extclk.2800651723
Short name	T531
Test name
Test status
Simulation time	76515056 ps
CPU time	1.09 seconds
Started	May 12 01:22:44 PM PDT 24
Finished	May 12 01:22:46 PM PDT 24
Peak memory	200520 kb
Host	smart-f2e1dbfb-e532-4bfa-955e-7f7a53ec9239
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800651723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.2800651723
Directory	/workspace/25.clkmgr_extclk/latest

Test location	/workspace/coverage/default/25.clkmgr_frequency.347142021
Short name	T12
Test name
Test status
Simulation time	1555664196 ps
CPU time	5.33 seconds
Started	May 12 01:22:46 PM PDT 24
Finished	May 12 01:22:52 PM PDT 24
Peak memory	200576 kb
Host	smart-dd739a0d-ccb5-4870-862c-620766300cee
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347142021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.347142021
Directory	/workspace/25.clkmgr_frequency/latest

Test location	/workspace/coverage/default/25.clkmgr_frequency_timeout.1494022355
Short name	T496
Test name
Test status
Simulation time	1112921778 ps
CPU time	4.84 seconds
Started	May 12 01:22:43 PM PDT 24
Finished	May 12 01:22:48 PM PDT 24
Peak memory	200624 kb
Host	smart-361b490d-e87a-43c8-9cdd-b28de61e4952
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494022355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t imeout.1494022355
Directory	/workspace/25.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/25.clkmgr_idle_intersig_mubi.1272025942
Short name	T600
Test name
Test status
Simulation time	95702992 ps
CPU time	0.94 seconds
Started	May 12 01:22:42 PM PDT 24
Finished	May 12 01:22:44 PM PDT 24
Peak memory	200436 kb
Host	smart-5a490154-1bdd-4968-8f2e-119fc3700e68
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272025942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_idle_intersig_mubi.1272025942
Directory	/workspace/25.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.3303812031
Short name	T129
Test name
Test status
Simulation time	45142083 ps
CPU time	0.84 seconds
Started	May 12 01:22:44 PM PDT 24
Finished	May 12 01:22:46 PM PDT 24
Peak memory	200456 kb
Host	smart-74e1ce03-e0b3-41b5-a9ce-97da5900e09b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303812031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 25.clkmgr_lc_clk_byp_req_intersig_mubi.3303812031
Directory	/workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.1479050207
Short name	T265
Test name
Test status
Simulation time	20745999 ps
CPU time	0.78 seconds
Started	May 12 01:22:45 PM PDT 24
Finished	May 12 01:22:46 PM PDT 24
Peak memory	200528 kb
Host	smart-d02ff955-1ab7-4813-a44d-ed37cb1a42c7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479050207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 25.clkmgr_lc_ctrl_intersig_mubi.1479050207
Directory	/workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/25.clkmgr_peri.2218138087
Short name	T225
Test name
Test status
Simulation time	32536469 ps
CPU time	0.75 seconds
Started	May 12 01:22:41 PM PDT 24
Finished	May 12 01:22:42 PM PDT 24
Peak memory	200308 kb
Host	smart-a2feb8d0-fb2d-43f6-9b26-b2b9bfd8e91b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218138087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.2218138087
Directory	/workspace/25.clkmgr_peri/latest

Test location	/workspace/coverage/default/25.clkmgr_regwen.3575607053
Short name	T847
Test name
Test status
Simulation time	759051254 ps
CPU time	2.92 seconds
Started	May 12 01:22:42 PM PDT 24
Finished	May 12 01:22:45 PM PDT 24
Peak memory	200672 kb
Host	smart-63ab7003-e650-4afc-b542-83e4dfcee3f1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575607053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.3575607053
Directory	/workspace/25.clkmgr_regwen/latest

Test location	/workspace/coverage/default/25.clkmgr_smoke.2454360751
Short name	T208
Test name
Test status
Simulation time	73941264 ps
CPU time	1 seconds
Started	May 12 01:22:45 PM PDT 24
Finished	May 12 01:22:46 PM PDT 24
Peak memory	200436 kb
Host	smart-e68e8131-3484-4b18-aa74-975d925f0881
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454360751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.2454360751
Directory	/workspace/25.clkmgr_smoke/latest

Test location	/workspace/coverage/default/25.clkmgr_stress_all.2983675003
Short name	T314
Test name
Test status
Simulation time	4589500537 ps
CPU time	18.13 seconds
Started	May 12 01:22:47 PM PDT 24
Finished	May 12 01:23:07 PM PDT 24
Peak memory	201116 kb
Host	smart-20638026-6dfd-49ad-b4b4-ab1802e1a7f0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983675003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all.2983675003
Directory	/workspace/25.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.1669727329
Short name	T568
Test name
Test status
Simulation time	9754449294 ps
CPU time	133.19 seconds
Started	May 12 01:22:45 PM PDT 24
Finished	May 12 01:24:59 PM PDT 24
Peak memory	213132 kb
Host	smart-1bc50450-3dfb-4c57-91ef-c32613c26149
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1669727329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.1669727329
Directory	/workspace/25.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.clkmgr_trans.1072739472
Short name	T644
Test name
Test status
Simulation time	71350067 ps
CPU time	0.92 seconds
Started	May 12 01:22:45 PM PDT 24
Finished	May 12 01:22:46 PM PDT 24
Peak memory	200504 kb
Host	smart-a3c0018c-7d47-4800-a7a4-01079a757257
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072739472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.1072739472
Directory	/workspace/25.clkmgr_trans/latest

Test location	/workspace/coverage/default/26.clkmgr_alert_test.2167216886
Short name	T572
Test name
Test status
Simulation time	31669386 ps
CPU time	0.77 seconds
Started	May 12 01:22:52 PM PDT 24
Finished	May 12 01:22:54 PM PDT 24
Peak memory	200448 kb
Host	smart-82eb3c20-6247-4f29-8306-1601f5e37fa0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167216886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk mgr_alert_test.2167216886
Directory	/workspace/26.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.3919617084
Short name	T254
Test name
Test status
Simulation time	137236440 ps
CPU time	1.24 seconds
Started	May 12 01:22:47 PM PDT 24
Finished	May 12 01:22:49 PM PDT 24
Peak memory	200488 kb
Host	smart-9cdd2596-b8e0-41a2-9d6b-c9df68624e18
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919617084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_handshake_intersig_mubi.3919617084
Directory	/workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_clk_status.2908074509
Short name	T532
Test name
Test status
Simulation time	12227918 ps
CPU time	0.69 seconds
Started	May 12 01:22:43 PM PDT 24
Finished	May 12 01:22:44 PM PDT 24
Peak memory	199520 kb
Host	smart-0d96a3b0-428b-42fd-b558-b879190317da
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908074509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.2908074509
Directory	/workspace/26.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/26.clkmgr_div_intersig_mubi.1002820572
Short name	T588
Test name
Test status
Simulation time	24382893 ps
CPU time	0.86 seconds
Started	May 12 01:22:47 PM PDT 24
Finished	May 12 01:22:49 PM PDT 24
Peak memory	200488 kb
Host	smart-8616b3d3-cd18-4e5b-ad90-c5e15333b3a7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002820572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_div_intersig_mubi.1002820572
Directory	/workspace/26.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_extclk.1137373343
Short name	T673
Test name
Test status
Simulation time	40101370 ps
CPU time	0.81 seconds
Started	May 12 01:22:41 PM PDT 24
Finished	May 12 01:22:42 PM PDT 24
Peak memory	200516 kb
Host	smart-1a7deed4-3301-441f-84e3-29079365a35d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137373343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.1137373343
Directory	/workspace/26.clkmgr_extclk/latest

Test location	/workspace/coverage/default/26.clkmgr_frequency.2570725376
Short name	T33
Test name
Test status
Simulation time	467595515 ps
CPU time	2.5 seconds
Started	May 12 01:22:42 PM PDT 24
Finished	May 12 01:22:45 PM PDT 24
Peak memory	200548 kb
Host	smart-aaedbb92-dad3-4c42-b2f2-d92bfca6af7e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570725376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.2570725376
Directory	/workspace/26.clkmgr_frequency/latest

Test location	/workspace/coverage/default/26.clkmgr_frequency_timeout.2323486596
Short name	T675
Test name
Test status
Simulation time	395547022 ps
CPU time	2.03 seconds
Started	May 12 01:22:42 PM PDT 24
Finished	May 12 01:22:45 PM PDT 24
Peak memory	200624 kb
Host	smart-8fb6b58e-a17a-4e79-b981-b50a9d84f4e0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323486596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t imeout.2323486596
Directory	/workspace/26.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/26.clkmgr_idle_intersig_mubi.820396541
Short name	T598
Test name
Test status
Simulation time	22532531 ps
CPU time	0.85 seconds
Started	May 12 01:22:47 PM PDT 24
Finished	May 12 01:22:49 PM PDT 24
Peak memory	200516 kb
Host	smart-e9ae41c0-11bf-4417-95d7-5350a8e6528a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820396541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.clkmgr_idle_intersig_mubi.820396541
Directory	/workspace/26.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.4012072975
Short name	T303
Test name
Test status
Simulation time	19189399 ps
CPU time	0.79 seconds
Started	May 12 01:22:47 PM PDT 24
Finished	May 12 01:22:48 PM PDT 24
Peak memory	200464 kb
Host	smart-6cc436e7-d510-4593-917b-f435d2874a04
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012072975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 26.clkmgr_lc_clk_byp_req_intersig_mubi.4012072975
Directory	/workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.1979073101
Short name	T842
Test name
Test status
Simulation time	65967381 ps
CPU time	0.96 seconds
Started	May 12 01:22:52 PM PDT 24
Finished	May 12 01:22:54 PM PDT 24
Peak memory	200520 kb
Host	smart-11ad4220-1457-4139-abcd-183f17286b37
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979073101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 26.clkmgr_lc_ctrl_intersig_mubi.1979073101
Directory	/workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/26.clkmgr_peri.2043533383
Short name	T654
Test name
Test status
Simulation time	160825904 ps
CPU time	1.11 seconds
Started	May 12 01:22:42 PM PDT 24
Finished	May 12 01:22:44 PM PDT 24
Peak memory	200292 kb
Host	smart-4638d260-3492-4bd2-9ad1-4bd660e17fcf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043533383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.2043533383
Directory	/workspace/26.clkmgr_peri/latest

Test location	/workspace/coverage/default/26.clkmgr_regwen.1678988157
Short name	T344
Test name
Test status
Simulation time	522011671 ps
CPU time	2.44 seconds
Started	May 12 01:22:47 PM PDT 24
Finished	May 12 01:22:51 PM PDT 24
Peak memory	200408 kb
Host	smart-7b541ef0-617b-4ce5-9244-5970eff9ffd6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678988157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.1678988157
Directory	/workspace/26.clkmgr_regwen/latest

Test location	/workspace/coverage/default/26.clkmgr_smoke.3930830076
Short name	T161
Test name
Test status
Simulation time	24546153 ps
CPU time	0.87 seconds
Started	May 12 01:22:41 PM PDT 24
Finished	May 12 01:22:42 PM PDT 24
Peak memory	200484 kb
Host	smart-5c914e74-7dc9-4915-bad7-8390b03d9de0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930830076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.3930830076
Directory	/workspace/26.clkmgr_smoke/latest

Test location	/workspace/coverage/default/26.clkmgr_stress_all.1608292266
Short name	T451
Test name
Test status
Simulation time	2709076267 ps
CPU time	11.52 seconds
Started	May 12 01:22:48 PM PDT 24
Finished	May 12 01:23:01 PM PDT 24
Peak memory	200932 kb
Host	smart-c4151efe-ec13-49a2-80a2-1aa78341aec4
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608292266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all.1608292266
Directory	/workspace/26.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.2168763179
Short name	T320
Test name
Test status
Simulation time	158086063615 ps
CPU time	1074.42 seconds
Started	May 12 01:22:46 PM PDT 24
Finished	May 12 01:40:41 PM PDT 24
Peak memory	215368 kb
Host	smart-62a1038d-00df-4e80-8e1b-3388496b711f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2168763179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.2168763179
Directory	/workspace/26.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/26.clkmgr_trans.2065033320
Short name	T274
Test name
Test status
Simulation time	20054031 ps
CPU time	0.84 seconds
Started	May 12 01:22:42 PM PDT 24
Finished	May 12 01:22:43 PM PDT 24
Peak memory	200496 kb
Host	smart-04e2e45d-eff2-4305-b4d6-861a35310407
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065033320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.2065033320
Directory	/workspace/26.clkmgr_trans/latest

Test location	/workspace/coverage/default/27.clkmgr_alert_test.3508610888
Short name	T474
Test name
Test status
Simulation time	28672450 ps
CPU time	0.81 seconds
Started	May 12 01:22:48 PM PDT 24
Finished	May 12 01:22:50 PM PDT 24
Peak memory	200560 kb
Host	smart-8606dda6-6327-4ac0-8bc7-d0be1c34ca4e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508610888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk mgr_alert_test.3508610888
Directory	/workspace/27.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.4054486008
Short name	T510
Test name
Test status
Simulation time	23646414 ps
CPU time	0.88 seconds
Started	May 12 01:22:52 PM PDT 24
Finished	May 12 01:22:54 PM PDT 24
Peak memory	200492 kb
Host	smart-ba3d231a-05e2-4541-8b84-44c64bc2275b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054486008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_handshake_intersig_mubi.4054486008
Directory	/workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_clk_status.498023784
Short name	T366
Test name
Test status
Simulation time	34612522 ps
CPU time	0.73 seconds
Started	May 12 01:22:49 PM PDT 24
Finished	May 12 01:22:50 PM PDT 24
Peak memory	200208 kb
Host	smart-a33c6b8d-2f58-4ae1-a7a7-15766bc38d8a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498023784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.498023784
Directory	/workspace/27.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/27.clkmgr_div_intersig_mubi.3356753246
Short name	T18
Test name
Test status
Simulation time	22884763 ps
CPU time	0.81 seconds
Started	May 12 01:22:48 PM PDT 24
Finished	May 12 01:22:50 PM PDT 24
Peak memory	200484 kb
Host	smart-d3719cb1-610b-49ac-8977-ef6958d077fe
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356753246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_div_intersig_mubi.3356753246
Directory	/workspace/27.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_extclk.982314821
Short name	T859
Test name
Test status
Simulation time	46277251 ps
CPU time	0.83 seconds
Started	May 12 01:22:48 PM PDT 24
Finished	May 12 01:22:50 PM PDT 24
Peak memory	200468 kb
Host	smart-a3fa5267-16dc-48ff-aa2f-29ec88de7b2f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982314821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.982314821
Directory	/workspace/27.clkmgr_extclk/latest

Test location	/workspace/coverage/default/27.clkmgr_frequency.69883978
Short name	T567
Test name
Test status
Simulation time	1642075843 ps
CPU time	12.42 seconds
Started	May 12 01:22:48 PM PDT 24
Finished	May 12 01:23:01 PM PDT 24
Peak memory	200580 kb
Host	smart-9ccc4ebd-16d5-4257-8a55-e8faf1bff465
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69883978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.69883978
Directory	/workspace/27.clkmgr_frequency/latest

Test location	/workspace/coverage/default/27.clkmgr_frequency_timeout.59594980
Short name	T331
Test name
Test status
Simulation time	1393081903 ps
CPU time	5.42 seconds
Started	May 12 01:22:49 PM PDT 24
Finished	May 12 01:22:55 PM PDT 24
Peak memory	200596 kb
Host	smart-ab082209-8cac-4ff4-94fd-ce43968b4e99
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59594980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_tim eout.59594980
Directory	/workspace/27.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/27.clkmgr_idle_intersig_mubi.212974577
Short name	T702
Test name
Test status
Simulation time	78837765 ps
CPU time	1.1 seconds
Started	May 12 01:22:47 PM PDT 24
Finished	May 12 01:22:49 PM PDT 24
Peak memory	200532 kb
Host	smart-022283b9-b567-45bf-b96b-1b98bf951e9b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212974577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.clkmgr_idle_intersig_mubi.212974577
Directory	/workspace/27.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.1918966865
Short name	T430
Test name
Test status
Simulation time	88479336 ps
CPU time	0.95 seconds
Started	May 12 01:22:54 PM PDT 24
Finished	May 12 01:22:55 PM PDT 24
Peak memory	200496 kb
Host	smart-0228bb9f-852a-4bee-92b8-26613d0d92ac
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918966865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 27.clkmgr_lc_clk_byp_req_intersig_mubi.1918966865
Directory	/workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.4210030828
Short name	T833
Test name
Test status
Simulation time	23952190 ps
CPU time	0.86 seconds
Started	May 12 01:22:48 PM PDT 24
Finished	May 12 01:22:50 PM PDT 24
Peak memory	200536 kb
Host	smart-8449b350-0bee-49f4-b50b-ed34d9396ba2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210030828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 27.clkmgr_lc_ctrl_intersig_mubi.4210030828
Directory	/workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/27.clkmgr_peri.1455606243
Short name	T643
Test name
Test status
Simulation time	19151961 ps
CPU time	0.78 seconds
Started	May 12 01:22:54 PM PDT 24
Finished	May 12 01:22:55 PM PDT 24
Peak memory	200260 kb
Host	smart-7a5b464e-fa85-4e7e-88b2-b22c8c8cacb5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455606243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.1455606243
Directory	/workspace/27.clkmgr_peri/latest

Test location	/workspace/coverage/default/27.clkmgr_regwen.2562691222
Short name	T380
Test name
Test status
Simulation time	584017171 ps
CPU time	2.89 seconds
Started	May 12 01:22:46 PM PDT 24
Finished	May 12 01:22:50 PM PDT 24
Peak memory	200592 kb
Host	smart-51c66dbb-1681-4e4c-9181-0d6eec2b0615
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562691222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.2562691222
Directory	/workspace/27.clkmgr_regwen/latest

Test location	/workspace/coverage/default/27.clkmgr_smoke.2612236574
Short name	T754
Test name
Test status
Simulation time	41985916 ps
CPU time	0.87 seconds
Started	May 12 01:22:47 PM PDT 24
Finished	May 12 01:22:49 PM PDT 24
Peak memory	200520 kb
Host	smart-f927d2b6-49ad-427d-b61a-497412dca49f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612236574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.2612236574
Directory	/workspace/27.clkmgr_smoke/latest

Test location	/workspace/coverage/default/27.clkmgr_stress_all.4291032186
Short name	T795
Test name
Test status
Simulation time	1842047291 ps
CPU time	12.6 seconds
Started	May 12 01:22:49 PM PDT 24
Finished	May 12 01:23:02 PM PDT 24
Peak memory	200812 kb
Host	smart-a1eae69b-e499-4756-a273-be9e76d5e6d5
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291032186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all.4291032186
Directory	/workspace/27.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.2562304238
Short name	T682
Test name
Test status
Simulation time	40642527992 ps
CPU time	756.93 seconds
Started	May 12 01:22:54 PM PDT 24
Finished	May 12 01:35:32 PM PDT 24
Peak memory	217340 kb
Host	smart-7cefcae4-9ee9-448a-8523-84cc8c62c409
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2562304238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.2562304238
Directory	/workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.clkmgr_trans.1202479325
Short name	T387
Test name
Test status
Simulation time	105578331 ps
CPU time	1.12 seconds
Started	May 12 01:22:46 PM PDT 24
Finished	May 12 01:22:48 PM PDT 24
Peak memory	200496 kb
Host	smart-f99e9db7-b964-42a7-9183-853828a6529c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202479325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.1202479325
Directory	/workspace/27.clkmgr_trans/latest

Test location	/workspace/coverage/default/28.clkmgr_alert_test.3179716197
Short name	T394
Test name
Test status
Simulation time	53345078 ps
CPU time	0.87 seconds
Started	May 12 01:22:50 PM PDT 24
Finished	May 12 01:22:52 PM PDT 24
Peak memory	200592 kb
Host	smart-c3a70b34-ab85-468e-82fc-9718d2ca0a48
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179716197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk mgr_alert_test.3179716197
Directory	/workspace/28.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.820670897
Short name	T271
Test name
Test status
Simulation time	73419924 ps
CPU time	1.02 seconds
Started	May 12 01:22:54 PM PDT 24
Finished	May 12 01:22:56 PM PDT 24
Peak memory	200480 kb
Host	smart-19787ec1-fc51-4bc3-87f9-2b0b883d3836
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820670897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_handshake_intersig_mubi.820670897
Directory	/workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_clk_status.2756628672
Short name	T360
Test name
Test status
Simulation time	14651503 ps
CPU time	0.71 seconds
Started	May 12 01:22:54 PM PDT 24
Finished	May 12 01:22:55 PM PDT 24
Peak memory	199516 kb
Host	smart-375e280d-7aed-4a02-8598-29bc9bc126b6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756628672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.2756628672
Directory	/workspace/28.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/28.clkmgr_div_intersig_mubi.1016601092
Short name	T463
Test name
Test status
Simulation time	24221841 ps
CPU time	0.88 seconds
Started	May 12 01:22:51 PM PDT 24
Finished	May 12 01:22:52 PM PDT 24
Peak memory	200452 kb
Host	smart-de34167e-8671-4a26-9f4d-ab2c77c73f67
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016601092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_div_intersig_mubi.1016601092
Directory	/workspace/28.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_extclk.668356828
Short name	T679
Test name
Test status
Simulation time	98897318 ps
CPU time	1.06 seconds
Started	May 12 01:22:48 PM PDT 24
Finished	May 12 01:22:50 PM PDT 24
Peak memory	200492 kb
Host	smart-fd84a096-5453-43da-917c-ea0d0d59194a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668356828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.668356828
Directory	/workspace/28.clkmgr_extclk/latest

Test location	/workspace/coverage/default/28.clkmgr_frequency.2226828001
Short name	T775
Test name
Test status
Simulation time	2360173397 ps
CPU time	17.49 seconds
Started	May 12 01:22:47 PM PDT 24
Finished	May 12 01:23:06 PM PDT 24
Peak memory	200760 kb
Host	smart-3fd7da59-a785-4279-b80b-c2c73683aadc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226828001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.2226828001
Directory	/workspace/28.clkmgr_frequency/latest

Test location	/workspace/coverage/default/28.clkmgr_frequency_timeout.2521280417
Short name	T417
Test name
Test status
Simulation time	2319470341 ps
CPU time	7.4 seconds
Started	May 12 01:22:46 PM PDT 24
Finished	May 12 01:22:55 PM PDT 24
Peak memory	200796 kb
Host	smart-05795824-c131-4f56-98c1-1bdec5477bdf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521280417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t imeout.2521280417
Directory	/workspace/28.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/28.clkmgr_idle_intersig_mubi.712484315
Short name	T264
Test name
Test status
Simulation time	22932335 ps
CPU time	0.86 seconds
Started	May 12 01:22:53 PM PDT 24
Finished	May 12 01:22:55 PM PDT 24
Peak memory	200476 kb
Host	smart-5b2b2f9e-7764-4fa1-a7d9-db10c4732f36
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712484315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.clkmgr_idle_intersig_mubi.712484315
Directory	/workspace/28.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.3710645644
Short name	T181
Test name
Test status
Simulation time	51594588 ps
CPU time	0.96 seconds
Started	May 12 01:22:51 PM PDT 24
Finished	May 12 01:22:52 PM PDT 24
Peak memory	200504 kb
Host	smart-07d4a8c1-bc34-4c58-aaff-ba22587067c7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710645644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 28.clkmgr_lc_clk_byp_req_intersig_mubi.3710645644
Directory	/workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.1491941903
Short name	T851
Test name
Test status
Simulation time	83462146 ps
CPU time	1.03 seconds
Started	May 12 01:22:50 PM PDT 24
Finished	May 12 01:22:51 PM PDT 24
Peak memory	200460 kb
Host	smart-0b36f8bc-e2f2-4e15-be80-2b1fbe91f5ac
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491941903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 28.clkmgr_lc_ctrl_intersig_mubi.1491941903
Directory	/workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/28.clkmgr_peri.1416960246
Short name	T593
Test name
Test status
Simulation time	21751196 ps
CPU time	0.73 seconds
Started	May 12 01:22:47 PM PDT 24
Finished	May 12 01:22:48 PM PDT 24
Peak memory	200308 kb
Host	smart-85120623-08f5-417b-95f1-f28a130d176b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416960246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.1416960246
Directory	/workspace/28.clkmgr_peri/latest

Test location	/workspace/coverage/default/28.clkmgr_smoke.1970930253
Short name	T156
Test name
Test status
Simulation time	37751342 ps
CPU time	0.88 seconds
Started	May 12 01:22:47 PM PDT 24
Finished	May 12 01:22:49 PM PDT 24
Peak memory	200396 kb
Host	smart-f1719d76-a76e-414c-b717-72485e9aade9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970930253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.1970930253
Directory	/workspace/28.clkmgr_smoke/latest

Test location	/workspace/coverage/default/28.clkmgr_stress_all.3347068099
Short name	T605
Test name
Test status
Simulation time	96257578 ps
CPU time	1.07 seconds
Started	May 12 01:22:51 PM PDT 24
Finished	May 12 01:22:54 PM PDT 24
Peak memory	200572 kb
Host	smart-a0433608-29f8-4d09-b287-9852a7a7994a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347068099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all.3347068099
Directory	/workspace/28.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.3594062180
Short name	T760
Test name
Test status
Simulation time	163519831476 ps
CPU time	1127.85 seconds
Started	May 12 01:22:52 PM PDT 24
Finished	May 12 01:41:41 PM PDT 24
Peak memory	217324 kb
Host	smart-7b8634f4-1956-46e9-8ca3-22f4b2086f8a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3594062180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.3594062180
Directory	/workspace/28.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/28.clkmgr_trans.2656741427
Short name	T230
Test name
Test status
Simulation time	41406202 ps
CPU time	0.83 seconds
Started	May 12 01:22:48 PM PDT 24
Finished	May 12 01:22:50 PM PDT 24
Peak memory	200472 kb
Host	smart-68b88852-231d-4d91-8bb7-48d96062a7cf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656741427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.2656741427
Directory	/workspace/28.clkmgr_trans/latest

Test location	/workspace/coverage/default/29.clkmgr_alert_test.50955961
Short name	T214
Test name
Test status
Simulation time	71511068 ps
CPU time	0.91 seconds
Started	May 12 01:22:51 PM PDT 24
Finished	May 12 01:22:53 PM PDT 24
Peak memory	200536 kb
Host	smart-1c82abe2-7832-410e-8f5e-1afb73992667
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50955961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmg r_alert_test.50955961
Directory	/workspace/29.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.2923726592
Short name	T352
Test name
Test status
Simulation time	18942564 ps
CPU time	0.86 seconds
Started	May 12 01:22:49 PM PDT 24
Finished	May 12 01:22:51 PM PDT 24
Peak memory	200456 kb
Host	smart-54083bae-c802-45d4-8f40-f7004b8ce8db
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923726592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_handshake_intersig_mubi.2923726592
Directory	/workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_clk_status.153213297
Short name	T465
Test name
Test status
Simulation time	15202065 ps
CPU time	0.7 seconds
Started	May 12 01:22:53 PM PDT 24
Finished	May 12 01:22:54 PM PDT 24
Peak memory	199556 kb
Host	smart-bf3229a5-62d4-4fa5-9b07-66cac2ecc257
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153213297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.153213297
Directory	/workspace/29.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/29.clkmgr_div_intersig_mubi.3511479909
Short name	T645
Test name
Test status
Simulation time	15476119 ps
CPU time	0.74 seconds
Started	May 12 01:22:53 PM PDT 24
Finished	May 12 01:22:54 PM PDT 24
Peak memory	200476 kb
Host	smart-8ae7421d-4980-4ead-a61f-a60086e60c1a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511479909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_div_intersig_mubi.3511479909
Directory	/workspace/29.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_extclk.1057706937
Short name	T468
Test name
Test status
Simulation time	37121804 ps
CPU time	0.9 seconds
Started	May 12 01:22:53 PM PDT 24
Finished	May 12 01:22:54 PM PDT 24
Peak memory	200524 kb
Host	smart-1e6f2e5b-c84c-479d-850d-c352bc874ff0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057706937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.1057706937
Directory	/workspace/29.clkmgr_extclk/latest

Test location	/workspace/coverage/default/29.clkmgr_frequency.1355118427
Short name	T776
Test name
Test status
Simulation time	2242102119 ps
CPU time	17.36 seconds
Started	May 12 01:22:51 PM PDT 24
Finished	May 12 01:23:09 PM PDT 24
Peak memory	200804 kb
Host	smart-4a4fd432-c67e-4c74-80a2-798a04303095
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355118427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.1355118427
Directory	/workspace/29.clkmgr_frequency/latest

Test location	/workspace/coverage/default/29.clkmgr_frequency_timeout.585266823
Short name	T249
Test name
Test status
Simulation time	2176939696 ps
CPU time	16.37 seconds
Started	May 12 01:22:51 PM PDT 24
Finished	May 12 01:23:09 PM PDT 24
Peak memory	200848 kb
Host	smart-b4584640-574f-4979-8ec9-053afebb5f6d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585266823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_ti meout.585266823
Directory	/workspace/29.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/29.clkmgr_idle_intersig_mubi.3247199419
Short name	T506
Test name
Test status
Simulation time	45644296 ps
CPU time	0.85 seconds
Started	May 12 01:22:53 PM PDT 24
Finished	May 12 01:22:55 PM PDT 24
Peak memory	200468 kb
Host	smart-75430199-c01e-482e-877e-937c3ef8e3b5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247199419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_idle_intersig_mubi.3247199419
Directory	/workspace/29.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.4225970308
Short name	T822
Test name
Test status
Simulation time	23812914 ps
CPU time	0.87 seconds
Started	May 12 01:22:49 PM PDT 24
Finished	May 12 01:22:51 PM PDT 24
Peak memory	200472 kb
Host	smart-313a1313-2b3d-48bd-a74b-1f12d62fbb0e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225970308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 29.clkmgr_lc_clk_byp_req_intersig_mubi.4225970308
Directory	/workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.192500699
Short name	T561
Test name
Test status
Simulation time	81890107 ps
CPU time	1.01 seconds
Started	May 12 01:22:54 PM PDT 24
Finished	May 12 01:22:55 PM PDT 24
Peak memory	200500 kb
Host	smart-7a0d86c6-b0f3-41c9-907a-fafe398248ac
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192500699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 29.clkmgr_lc_ctrl_intersig_mubi.192500699
Directory	/workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/29.clkmgr_peri.446116053
Short name	T190
Test name
Test status
Simulation time	16487349 ps
CPU time	0.76 seconds
Started	May 12 01:22:51 PM PDT 24
Finished	May 12 01:22:53 PM PDT 24
Peak memory	200300 kb
Host	smart-4d037607-7116-4fee-ac7e-ab0d47fdf786
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446116053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.446116053
Directory	/workspace/29.clkmgr_peri/latest

Test location	/workspace/coverage/default/29.clkmgr_regwen.3926743167
Short name	T608
Test name
Test status
Simulation time	295903957 ps
CPU time	1.65 seconds
Started	May 12 01:22:51 PM PDT 24
Finished	May 12 01:22:54 PM PDT 24
Peak memory	200464 kb
Host	smart-98ca3064-e13c-4519-902f-1e1a0bd26515
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926743167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.3926743167
Directory	/workspace/29.clkmgr_regwen/latest

Test location	/workspace/coverage/default/29.clkmgr_smoke.101306505
Short name	T594
Test name
Test status
Simulation time	24621070 ps
CPU time	0.81 seconds
Started	May 12 01:22:51 PM PDT 24
Finished	May 12 01:22:52 PM PDT 24
Peak memory	200468 kb
Host	smart-c4bf1096-e552-4df5-83b3-18a73b797b45
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101306505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.101306505
Directory	/workspace/29.clkmgr_smoke/latest

Test location	/workspace/coverage/default/29.clkmgr_stress_all.2172841733
Short name	T425
Test name
Test status
Simulation time	11032677853 ps
CPU time	42.47 seconds
Started	May 12 01:22:51 PM PDT 24
Finished	May 12 01:23:35 PM PDT 24
Peak memory	200904 kb
Host	smart-755fcf79-c61e-494a-add5-05e5eae58ed0
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172841733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all.2172841733
Directory	/workspace/29.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.4209267341
Short name	T359
Test name
Test status
Simulation time	60562274815 ps
CPU time	654.55 seconds
Started	May 12 01:22:59 PM PDT 24
Finished	May 12 01:33:54 PM PDT 24
Peak memory	212216 kb
Host	smart-b15e5e7f-ac47-47a1-bc88-a07e0d9045f0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4209267341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.4209267341
Directory	/workspace/29.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.clkmgr_trans.47604322
Short name	T193
Test name
Test status
Simulation time	30952475 ps
CPU time	0.94 seconds
Started	May 12 01:22:51 PM PDT 24
Finished	May 12 01:22:53 PM PDT 24
Peak memory	200412 kb
Host	smart-b925664c-1468-4396-9c65-a160e2eb4cf3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47604322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.47604322
Directory	/workspace/29.clkmgr_trans/latest

Test location	/workspace/coverage/default/3.clkmgr_alert_test.3045283558
Short name	T337
Test name
Test status
Simulation time	17729018 ps
CPU time	0.73 seconds
Started	May 12 01:21:32 PM PDT 24
Finished	May 12 01:21:33 PM PDT 24
Peak memory	200596 kb
Host	smart-3da18e0c-2c58-41b9-a2b2-547813812fe4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045283558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm gr_alert_test.3045283558
Directory	/workspace/3.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.1439333825
Short name	T848
Test name
Test status
Simulation time	53074251 ps
CPU time	0.94 seconds
Started	May 12 01:21:30 PM PDT 24
Finished	May 12 01:21:32 PM PDT 24
Peak memory	200480 kb
Host	smart-af68cdc7-d9fd-4a45-80ca-5971fdc3d516
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439333825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_handshake_intersig_mubi.1439333825
Directory	/workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_clk_status.3667178656
Short name	T62
Test name
Test status
Simulation time	39031060 ps
CPU time	0.76 seconds
Started	May 12 01:21:27 PM PDT 24
Finished	May 12 01:21:28 PM PDT 24
Peak memory	199528 kb
Host	smart-907e5075-3ac5-4c58-bb6c-fe8be31994b8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667178656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.3667178656
Directory	/workspace/3.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/3.clkmgr_div_intersig_mubi.1122532121
Short name	T210
Test name
Test status
Simulation time	41450415 ps
CPU time	1.02 seconds
Started	May 12 01:21:30 PM PDT 24
Finished	May 12 01:21:32 PM PDT 24
Peak memory	200504 kb
Host	smart-3c983fe7-0b54-424a-92f2-521a4c9b4281
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122532121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_div_intersig_mubi.1122532121
Directory	/workspace/3.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_extclk.4254521327
Short name	T732
Test name
Test status
Simulation time	12442650 ps
CPU time	0.71 seconds
Started	May 12 01:21:27 PM PDT 24
Finished	May 12 01:21:28 PM PDT 24
Peak memory	200476 kb
Host	smart-779767c9-c869-447b-92d7-7a3610214d7c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254521327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.4254521327
Directory	/workspace/3.clkmgr_extclk/latest

Test location	/workspace/coverage/default/3.clkmgr_frequency.3050929393
Short name	T783
Test name
Test status
Simulation time	1274924204 ps
CPU time	4.86 seconds
Started	May 12 01:21:26 PM PDT 24
Finished	May 12 01:21:32 PM PDT 24
Peak memory	200548 kb
Host	smart-00bbdb7f-d324-4d99-9fe1-6d72bbe979fb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050929393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.3050929393
Directory	/workspace/3.clkmgr_frequency/latest

Test location	/workspace/coverage/default/3.clkmgr_frequency_timeout.1908521623
Short name	T487
Test name
Test status
Simulation time	1706283894 ps
CPU time	7.83 seconds
Started	May 12 01:21:31 PM PDT 24
Finished	May 12 01:21:40 PM PDT 24
Peak memory	200652 kb
Host	smart-47250aeb-f4db-45c7-b0a8-725a822cca7d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908521623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti meout.1908521623
Directory	/workspace/3.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/3.clkmgr_idle_intersig_mubi.79981670
Short name	T375
Test name
Test status
Simulation time	44674897 ps
CPU time	0.82 seconds
Started	May 12 01:21:27 PM PDT 24
Finished	May 12 01:21:28 PM PDT 24
Peak memory	200480 kb
Host	smart-34639fbf-09f7-4dc8-8481-6f5001b01b3d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79981670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. clkmgr_idle_intersig_mubi.79981670
Directory	/workspace/3.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.66295707
Short name	T765
Test name
Test status
Simulation time	70491437 ps
CPU time	1 seconds
Started	May 12 01:21:30 PM PDT 24
Finished	May 12 01:21:31 PM PDT 24
Peak memory	200484 kb
Host	smart-9931bdbc-c1b0-437e-92d6-48c93ef495ac
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66295707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_clk_byp_req_intersig_mubi.66295707
Directory	/workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.4159492901
Short name	T231
Test name
Test status
Simulation time	44380862 ps
CPU time	0.88 seconds
Started	May 12 01:21:31 PM PDT 24
Finished	May 12 01:21:32 PM PDT 24
Peak memory	200492 kb
Host	smart-3ef2c9e0-8755-4788-a48b-a46a6eb10044
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159492901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 3.clkmgr_lc_ctrl_intersig_mubi.4159492901
Directory	/workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/3.clkmgr_peri.4065248338
Short name	T683
Test name
Test status
Simulation time	43280388 ps
CPU time	0.78 seconds
Started	May 12 01:21:31 PM PDT 24
Finished	May 12 01:21:33 PM PDT 24
Peak memory	200312 kb
Host	smart-a75a5ef6-a9c9-4c5c-b728-ae19a64ad396
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065248338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.4065248338
Directory	/workspace/3.clkmgr_peri/latest

Test location	/workspace/coverage/default/3.clkmgr_regwen.201744475
Short name	T10
Test name
Test status
Simulation time	1153404802 ps
CPU time	6.15 seconds
Started	May 12 01:21:33 PM PDT 24
Finished	May 12 01:21:40 PM PDT 24
Peak memory	200672 kb
Host	smart-9ec53c5b-598d-4d29-b236-514a79a5735b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201744475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.201744475
Directory	/workspace/3.clkmgr_regwen/latest

Test location	/workspace/coverage/default/3.clkmgr_sec_cm.2525189850
Short name	T49
Test name
Test status
Simulation time	213325208 ps
CPU time	1.97 seconds
Started	May 12 01:21:30 PM PDT 24
Finished	May 12 01:21:32 PM PDT 24
Peak memory	219844 kb
Host	smart-0eb09663-dea1-4316-9303-71475f95f990
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525189850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg r_sec_cm.2525189850
Directory	/workspace/3.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/3.clkmgr_smoke.94042563
Short name	T159
Test name
Test status
Simulation time	72405477 ps
CPU time	0.98 seconds
Started	May 12 01:21:28 PM PDT 24
Finished	May 12 01:21:30 PM PDT 24
Peak memory	200492 kb
Host	smart-cde8271a-3dc5-42d9-bae3-51aad2365668
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94042563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.94042563
Directory	/workspace/3.clkmgr_smoke/latest

Test location	/workspace/coverage/default/3.clkmgr_stress_all.1546003197
Short name	T400
Test name
Test status
Simulation time	6220282230 ps
CPU time	43.54 seconds
Started	May 12 01:21:28 PM PDT 24
Finished	May 12 01:22:12 PM PDT 24
Peak memory	200844 kb
Host	smart-e45c7cdc-521d-448f-8a48-fdef668f55f6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546003197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all.1546003197
Directory	/workspace/3.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/3.clkmgr_stress_all_with_rand_reset.2619741620
Short name	T172
Test name
Test status
Simulation time	75457045968 ps
CPU time	792.2 seconds
Started	May 12 01:21:31 PM PDT 24
Finished	May 12 01:34:44 PM PDT 24
Peak memory	217524 kb
Host	smart-78105be1-a707-49d9-8cab-3cc2e87977d4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2619741620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.2619741620
Directory	/workspace/3.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.clkmgr_trans.2913859713
Short name	T735
Test name
Test status
Simulation time	25828678 ps
CPU time	0.77 seconds
Started	May 12 01:21:27 PM PDT 24
Finished	May 12 01:21:28 PM PDT 24
Peak memory	200436 kb
Host	smart-d1929dca-a044-4e31-8cb0-dce9fb2d1182
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913859713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.2913859713
Directory	/workspace/3.clkmgr_trans/latest

Test location	/workspace/coverage/default/30.clkmgr_alert_test.4073588488
Short name	T663
Test name
Test status
Simulation time	43907251 ps
CPU time	0.8 seconds
Started	May 12 01:23:04 PM PDT 24
Finished	May 12 01:23:06 PM PDT 24
Peak memory	200496 kb
Host	smart-3b57f386-b68c-4a7c-9473-95accd2fd2fa
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073588488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk mgr_alert_test.4073588488
Directory	/workspace/30.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.553104946
Short name	T112
Test name
Test status
Simulation time	47746867 ps
CPU time	0.99 seconds
Started	May 12 01:22:58 PM PDT 24
Finished	May 12 01:23:00 PM PDT 24
Peak memory	200448 kb
Host	smart-6b8b9849-865c-4405-acad-9a6e892bc2f1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553104946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_handshake_intersig_mubi.553104946
Directory	/workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_clk_status.486761113
Short name	T583
Test name
Test status
Simulation time	16103527 ps
CPU time	0.74 seconds
Started	May 12 01:22:55 PM PDT 24
Finished	May 12 01:22:56 PM PDT 24
Peak memory	199556 kb
Host	smart-91cf16e2-ef50-4aef-9dda-d87ec8909349
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486761113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.486761113
Directory	/workspace/30.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/30.clkmgr_div_intersig_mubi.2522237514
Short name	T92
Test name
Test status
Simulation time	32946972 ps
CPU time	0.85 seconds
Started	May 12 01:23:03 PM PDT 24
Finished	May 12 01:23:05 PM PDT 24
Peak memory	200480 kb
Host	smart-9604c54a-a09d-4a7c-8da4-0b411460870b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522237514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_div_intersig_mubi.2522237514
Directory	/workspace/30.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_extclk.248832629
Short name	T581
Test name
Test status
Simulation time	22837087 ps
CPU time	0.78 seconds
Started	May 12 01:22:55 PM PDT 24
Finished	May 12 01:22:56 PM PDT 24
Peak memory	200480 kb
Host	smart-8e7fea2c-9241-4c86-b199-6f66bd63c05a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248832629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.248832629
Directory	/workspace/30.clkmgr_extclk/latest

Test location	/workspace/coverage/default/30.clkmgr_frequency.4223223406
Short name	T393
Test name
Test status
Simulation time	1402894698 ps
CPU time	10.52 seconds
Started	May 12 01:23:00 PM PDT 24
Finished	May 12 01:23:11 PM PDT 24
Peak memory	200560 kb
Host	smart-2ae25a34-aaf7-4557-b383-90dd5684dd60
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223223406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.4223223406
Directory	/workspace/30.clkmgr_frequency/latest

Test location	/workspace/coverage/default/30.clkmgr_frequency_timeout.2712711090
Short name	T637
Test name
Test status
Simulation time	1934945796 ps
CPU time	14 seconds
Started	May 12 01:22:55 PM PDT 24
Finished	May 12 01:23:10 PM PDT 24
Peak memory	200656 kb
Host	smart-6a26b218-82cd-407c-ad20-92bbfa93361a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712711090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t imeout.2712711090
Directory	/workspace/30.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/30.clkmgr_idle_intersig_mubi.711179483
Short name	T421
Test name
Test status
Simulation time	98087304 ps
CPU time	1.13 seconds
Started	May 12 01:22:58 PM PDT 24
Finished	May 12 01:22:59 PM PDT 24
Peak memory	200420 kb
Host	smart-3ab83ea0-6c03-4ac6-99aa-869cafb8a737
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711179483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.clkmgr_idle_intersig_mubi.711179483
Directory	/workspace/30.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.836643307
Short name	T216
Test name
Test status
Simulation time	20083037 ps
CPU time	0.83 seconds
Started	May 12 01:23:01 PM PDT 24
Finished	May 12 01:23:03 PM PDT 24
Peak memory	200516 kb
Host	smart-e2b68341-e69d-4c0e-83b9-be3944009ce9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836643307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.clkmgr_lc_clk_byp_req_intersig_mubi.836643307
Directory	/workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.2778397587
Short name	T585
Test name
Test status
Simulation time	20975339 ps
CPU time	0.82 seconds
Started	May 12 01:23:02 PM PDT 24
Finished	May 12 01:23:04 PM PDT 24
Peak memory	200532 kb
Host	smart-c677696c-1f12-45a9-9cd2-3e6f1ce1d81d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778397587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 30.clkmgr_lc_ctrl_intersig_mubi.2778397587
Directory	/workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/30.clkmgr_peri.3476027869
Short name	T467
Test name
Test status
Simulation time	16905559 ps
CPU time	0.71 seconds
Started	May 12 01:22:56 PM PDT 24
Finished	May 12 01:22:57 PM PDT 24
Peak memory	200312 kb
Host	smart-df06fba5-c915-4ffb-97e1-20ce565e4f6f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476027869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.3476027869
Directory	/workspace/30.clkmgr_peri/latest

Test location	/workspace/coverage/default/30.clkmgr_regwen.1690685784
Short name	T640
Test name
Test status
Simulation time	638314951 ps
CPU time	2.34 seconds
Started	May 12 01:23:04 PM PDT 24
Finished	May 12 01:23:07 PM PDT 24
Peak memory	200472 kb
Host	smart-4b6dbb6c-d9d7-41db-985d-3c04e3774c3a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690685784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.1690685784
Directory	/workspace/30.clkmgr_regwen/latest

Test location	/workspace/coverage/default/30.clkmgr_smoke.2901084973
Short name	T618
Test name
Test status
Simulation time	44618996 ps
CPU time	0.89 seconds
Started	May 12 01:22:57 PM PDT 24
Finished	May 12 01:22:59 PM PDT 24
Peak memory	200448 kb
Host	smart-c6bc4dff-b659-4171-bcdd-529ac1fda611
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901084973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.2901084973
Directory	/workspace/30.clkmgr_smoke/latest

Test location	/workspace/coverage/default/30.clkmgr_stress_all.2214287313
Short name	T632
Test name
Test status
Simulation time	4845924113 ps
CPU time	21.15 seconds
Started	May 12 01:23:00 PM PDT 24
Finished	May 12 01:23:22 PM PDT 24
Peak memory	200852 kb
Host	smart-2e1923ed-c9db-4a66-80e7-a21ccb505286
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214287313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all.2214287313
Directory	/workspace/30.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.3565685567
Short name	T753
Test name
Test status
Simulation time	41174995078 ps
CPU time	743.58 seconds
Started	May 12 01:23:01 PM PDT 24
Finished	May 12 01:35:25 PM PDT 24
Peak memory	209172 kb
Host	smart-e11cd47e-cc4d-4ab0-ad2e-ff9714f0290f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3565685567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.3565685567
Directory	/workspace/30.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.clkmgr_trans.520800861
Short name	T575
Test name
Test status
Simulation time	71289298 ps
CPU time	0.95 seconds
Started	May 12 01:22:56 PM PDT 24
Finished	May 12 01:22:58 PM PDT 24
Peak memory	200496 kb
Host	smart-64fcbd55-8a48-4c12-b2fb-d0fe75e52c05
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520800861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.520800861
Directory	/workspace/30.clkmgr_trans/latest

Test location	/workspace/coverage/default/31.clkmgr_alert_test.3336783295
Short name	T35
Test name
Test status
Simulation time	17111460 ps
CPU time	0.76 seconds
Started	May 12 01:23:03 PM PDT 24
Finished	May 12 01:23:04 PM PDT 24
Peak memory	200560 kb
Host	smart-4b02c18e-1556-439d-b25f-dc2f8eac07b9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336783295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk mgr_alert_test.3336783295
Directory	/workspace/31.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.577315800
Short name	T215
Test name
Test status
Simulation time	76597088 ps
CPU time	0.98 seconds
Started	May 12 01:23:01 PM PDT 24
Finished	May 12 01:23:03 PM PDT 24
Peak memory	200504 kb
Host	smart-ed5359df-9e9f-418a-9a0a-3d89a37c14fe
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577315800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_handshake_intersig_mubi.577315800
Directory	/workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_clk_status.410452443
Short name	T422
Test name
Test status
Simulation time	117414234 ps
CPU time	0.95 seconds
Started	May 12 01:23:04 PM PDT 24
Finished	May 12 01:23:07 PM PDT 24
Peak memory	199528 kb
Host	smart-ebbea69c-b742-4fab-a046-10b039fc4913
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410452443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.410452443
Directory	/workspace/31.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/31.clkmgr_div_intersig_mubi.1862263436
Short name	T841
Test name
Test status
Simulation time	17116697 ps
CPU time	0.74 seconds
Started	May 12 01:23:04 PM PDT 24
Finished	May 12 01:23:06 PM PDT 24
Peak memory	200508 kb
Host	smart-8949fdaa-c53a-463f-b8a1-b4477d0525f6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862263436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_div_intersig_mubi.1862263436
Directory	/workspace/31.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_extclk.3201122252
Short name	T566
Test name
Test status
Simulation time	17121097 ps
CPU time	0.76 seconds
Started	May 12 01:22:59 PM PDT 24
Finished	May 12 01:23:00 PM PDT 24
Peak memory	200516 kb
Host	smart-442a4f56-f524-4266-91cb-ae470ffc4f76
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201122252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.3201122252
Directory	/workspace/31.clkmgr_extclk/latest

Test location	/workspace/coverage/default/31.clkmgr_frequency.965951982
Short name	T402
Test name
Test status
Simulation time	1112105628 ps
CPU time	4.32 seconds
Started	May 12 01:23:04 PM PDT 24
Finished	May 12 01:23:10 PM PDT 24
Peak memory	200580 kb
Host	smart-47bc06e2-bf63-4d18-8707-cee555bd8043
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965951982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.965951982
Directory	/workspace/31.clkmgr_frequency/latest

Test location	/workspace/coverage/default/31.clkmgr_frequency_timeout.2382411087
Short name	T297
Test name
Test status
Simulation time	975376446 ps
CPU time	6.87 seconds
Started	May 12 01:23:02 PM PDT 24
Finished	May 12 01:23:10 PM PDT 24
Peak memory	200652 kb
Host	smart-18735b8d-31c9-43f9-8c65-60ce1565af0c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382411087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t imeout.2382411087
Directory	/workspace/31.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/31.clkmgr_idle_intersig_mubi.2203671207
Short name	T475
Test name
Test status
Simulation time	44379829 ps
CPU time	0.94 seconds
Started	May 12 01:22:58 PM PDT 24
Finished	May 12 01:23:00 PM PDT 24
Peak memory	200512 kb
Host	smart-9842c222-fac3-4563-8621-71d8f231e879
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203671207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_idle_intersig_mubi.2203671207
Directory	/workspace/31.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.3910360763
Short name	T649
Test name
Test status
Simulation time	14275389 ps
CPU time	0.74 seconds
Started	May 12 01:23:04 PM PDT 24
Finished	May 12 01:23:06 PM PDT 24
Peak memory	200500 kb
Host	smart-8e16a2ba-a6c0-4a3e-b530-c522c3f67fdd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910360763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 31.clkmgr_lc_clk_byp_req_intersig_mubi.3910360763
Directory	/workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.659150033
Short name	T164
Test name
Test status
Simulation time	79182227 ps
CPU time	0.95 seconds
Started	May 12 01:23:01 PM PDT 24
Finished	May 12 01:23:02 PM PDT 24
Peak memory	200468 kb
Host	smart-81f61779-9822-461e-921c-8e6e2147e466
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659150033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.clkmgr_lc_ctrl_intersig_mubi.659150033
Directory	/workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/31.clkmgr_peri.1548708411
Short name	T473
Test name
Test status
Simulation time	40047006 ps
CPU time	0.79 seconds
Started	May 12 01:23:00 PM PDT 24
Finished	May 12 01:23:02 PM PDT 24
Peak memory	200244 kb
Host	smart-b15d95e6-4ff0-440c-8b08-a1e67461e320
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548708411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.1548708411
Directory	/workspace/31.clkmgr_peri/latest

Test location	/workspace/coverage/default/31.clkmgr_regwen.2505262605
Short name	T5
Test name
Test status
Simulation time	1595090132 ps
CPU time	5.6 seconds
Started	May 12 01:23:00 PM PDT 24
Finished	May 12 01:23:06 PM PDT 24
Peak memory	200652 kb
Host	smart-9c4b2cd1-b60f-4252-ad67-7021014f36c4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505262605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.2505262605
Directory	/workspace/31.clkmgr_regwen/latest

Test location	/workspace/coverage/default/31.clkmgr_smoke.2011100756
Short name	T46
Test name
Test status
Simulation time	37888033 ps
CPU time	0.89 seconds
Started	May 12 01:23:04 PM PDT 24
Finished	May 12 01:23:05 PM PDT 24
Peak memory	200516 kb
Host	smart-20a4b54e-65c5-4326-8ba8-946ea19d1e37
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011100756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.2011100756
Directory	/workspace/31.clkmgr_smoke/latest

Test location	/workspace/coverage/default/31.clkmgr_stress_all.3132044796
Short name	T589
Test name
Test status
Simulation time	5773884498 ps
CPU time	28.31 seconds
Started	May 12 01:23:06 PM PDT 24
Finished	May 12 01:23:35 PM PDT 24
Peak memory	200852 kb
Host	smart-34797e89-1f51-41ce-b5ca-87d465b553de
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132044796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all.3132044796
Directory	/workspace/31.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.3162329552
Short name	T786
Test name
Test status
Simulation time	39405291596 ps
CPU time	703.24 seconds
Started	May 12 01:23:01 PM PDT 24
Finished	May 12 01:34:45 PM PDT 24
Peak memory	217352 kb
Host	smart-1ff5623a-ae6f-4b21-a93b-41334ade5080
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3162329552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.3162329552
Directory	/workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.clkmgr_trans.1557452620
Short name	T666
Test name
Test status
Simulation time	18249511 ps
CPU time	0.75 seconds
Started	May 12 01:22:58 PM PDT 24
Finished	May 12 01:22:59 PM PDT 24
Peak memory	200468 kb
Host	smart-29f8f55c-6bf0-40c5-be6a-527d25341a13
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557452620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.1557452620
Directory	/workspace/31.clkmgr_trans/latest

Test location	/workspace/coverage/default/32.clkmgr_alert_test.2910681410
Short name	T582
Test name
Test status
Simulation time	18500757 ps
CPU time	0.84 seconds
Started	May 12 01:23:06 PM PDT 24
Finished	May 12 01:23:07 PM PDT 24
Peak memory	200572 kb
Host	smart-d8718548-6c31-4d47-8f06-8a276e07357f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910681410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk mgr_alert_test.2910681410
Directory	/workspace/32.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.809435229
Short name	T189
Test name
Test status
Simulation time	159410223 ps
CPU time	1.21 seconds
Started	May 12 01:23:05 PM PDT 24
Finished	May 12 01:23:07 PM PDT 24
Peak memory	200472 kb
Host	smart-9db78bcb-fb8c-4bb3-b5d5-44bf7e9de8e1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809435229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_handshake_intersig_mubi.809435229
Directory	/workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_clk_status.1879537255
Short name	T175
Test name
Test status
Simulation time	23265175 ps
CPU time	0.69 seconds
Started	May 12 01:22:58 PM PDT 24
Finished	May 12 01:22:59 PM PDT 24
Peak memory	200236 kb
Host	smart-7f8124e9-693a-4ea5-951b-21ac2f5c12fa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879537255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.1879537255
Directory	/workspace/32.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/32.clkmgr_div_intersig_mubi.3008056945
Short name	T354
Test name
Test status
Simulation time	46443558 ps
CPU time	0.85 seconds
Started	May 12 01:23:10 PM PDT 24
Finished	May 12 01:23:12 PM PDT 24
Peak memory	200496 kb
Host	smart-145779b4-d210-4067-8a94-4c37c328cf9d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008056945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_div_intersig_mubi.3008056945
Directory	/workspace/32.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_extclk.357429497
Short name	T680
Test name
Test status
Simulation time	20823575 ps
CPU time	0.78 seconds
Started	May 12 01:23:04 PM PDT 24
Finished	May 12 01:23:06 PM PDT 24
Peak memory	200512 kb
Host	smart-08e4eaf0-859e-4919-bdef-d7a49f273acf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357429497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.357429497
Directory	/workspace/32.clkmgr_extclk/latest

Test location	/workspace/coverage/default/32.clkmgr_frequency.3246192147
Short name	T636
Test name
Test status
Simulation time	916893461 ps
CPU time	7.38 seconds
Started	May 12 01:23:02 PM PDT 24
Finished	May 12 01:23:10 PM PDT 24
Peak memory	200632 kb
Host	smart-46005e0b-ee37-4046-b987-bcfa5c9916ac
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246192147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.3246192147
Directory	/workspace/32.clkmgr_frequency/latest

Test location	/workspace/coverage/default/32.clkmgr_frequency_timeout.3636461200
Short name	T694
Test name
Test status
Simulation time	994623456 ps
CPU time	4.24 seconds
Started	May 12 01:23:00 PM PDT 24
Finished	May 12 01:23:05 PM PDT 24
Peak memory	200640 kb
Host	smart-c42297f1-9813-4c00-b2e6-1989c9bb2ee1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636461200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t imeout.3636461200
Directory	/workspace/32.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/32.clkmgr_idle_intersig_mubi.2883231710
Short name	T466
Test name
Test status
Simulation time	26555794 ps
CPU time	1.02 seconds
Started	May 12 01:23:03 PM PDT 24
Finished	May 12 01:23:05 PM PDT 24
Peak memory	200452 kb
Host	smart-e7fcc4f9-52ba-40ee-85a6-d404a9c9449f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883231710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_idle_intersig_mubi.2883231710
Directory	/workspace/32.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.3272305998
Short name	T263
Test name
Test status
Simulation time	32910304 ps
CPU time	0.82 seconds
Started	May 12 01:23:04 PM PDT 24
Finished	May 12 01:23:06 PM PDT 24
Peak memory	200496 kb
Host	smart-ec06315e-8530-452a-ae1f-3e92939909f4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272305998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 32.clkmgr_lc_clk_byp_req_intersig_mubi.3272305998
Directory	/workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.842348540
Short name	T497
Test name
Test status
Simulation time	45645978 ps
CPU time	0.85 seconds
Started	May 12 01:23:03 PM PDT 24
Finished	May 12 01:23:05 PM PDT 24
Peak memory	200504 kb
Host	smart-9b0eeb47-ab59-494d-83f7-c6419685609b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842348540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.clkmgr_lc_ctrl_intersig_mubi.842348540
Directory	/workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/32.clkmgr_peri.763190648
Short name	T816
Test name
Test status
Simulation time	37599837 ps
CPU time	0.78 seconds
Started	May 12 01:23:00 PM PDT 24
Finished	May 12 01:23:02 PM PDT 24
Peak memory	200316 kb
Host	smart-cc605332-5657-4d53-ad0a-13ce948d8f06
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763190648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.763190648
Directory	/workspace/32.clkmgr_peri/latest

Test location	/workspace/coverage/default/32.clkmgr_regwen.4266976853
Short name	T167
Test name
Test status
Simulation time	831130687 ps
CPU time	3.92 seconds
Started	May 12 01:23:03 PM PDT 24
Finished	May 12 01:23:08 PM PDT 24
Peak memory	200628 kb
Host	smart-4c08f65c-c92b-4382-952b-6794a117d824
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266976853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.4266976853
Directory	/workspace/32.clkmgr_regwen/latest

Test location	/workspace/coverage/default/32.clkmgr_smoke.1141109882
Short name	T194
Test name
Test status
Simulation time	20838781 ps
CPU time	0.86 seconds
Started	May 12 01:23:00 PM PDT 24
Finished	May 12 01:23:02 PM PDT 24
Peak memory	200480 kb
Host	smart-9998fd95-0554-4626-811c-8a6bac1c6451
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141109882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.1141109882
Directory	/workspace/32.clkmgr_smoke/latest

Test location	/workspace/coverage/default/32.clkmgr_stress_all.3854035072
Short name	T54
Test name
Test status
Simulation time	12220439350 ps
CPU time	88.59 seconds
Started	May 12 01:23:02 PM PDT 24
Finished	May 12 01:24:32 PM PDT 24
Peak memory	200964 kb
Host	smart-04a8eeed-1ab8-4d0c-9905-669ff3e05a7a
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854035072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all.3854035072
Directory	/workspace/32.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.1976072451
Short name	T464
Test name
Test status
Simulation time	78197848691 ps
CPU time	599.33 seconds
Started	May 12 01:23:03 PM PDT 24
Finished	May 12 01:33:04 PM PDT 24
Peak memory	217332 kb
Host	smart-28c6090b-e3ef-4f15-baf8-64ec522a848c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1976072451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.1976072451
Directory	/workspace/32.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.clkmgr_trans.125548920
Short name	T844
Test name
Test status
Simulation time	52143722 ps
CPU time	1.05 seconds
Started	May 12 01:23:00 PM PDT 24
Finished	May 12 01:23:02 PM PDT 24
Peak memory	200428 kb
Host	smart-b5f86e2a-88b8-42d3-b1ae-69326e6913ba
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125548920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.125548920
Directory	/workspace/32.clkmgr_trans/latest

Test location	/workspace/coverage/default/33.clkmgr_alert_test.1826317946
Short name	T404
Test name
Test status
Simulation time	60234003 ps
CPU time	0.9 seconds
Started	May 12 01:23:10 PM PDT 24
Finished	May 12 01:23:12 PM PDT 24
Peak memory	200580 kb
Host	smart-de4b6d37-f643-4648-b80f-18eb196f2729
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826317946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk mgr_alert_test.1826317946
Directory	/workspace/33.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.1571135564
Short name	T523
Test name
Test status
Simulation time	53431684 ps
CPU time	1.07 seconds
Started	May 12 01:23:04 PM PDT 24
Finished	May 12 01:23:06 PM PDT 24
Peak memory	200436 kb
Host	smart-c7fd3da9-aa2c-45fa-a41b-cf7200b6854f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571135564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_handshake_intersig_mubi.1571135564
Directory	/workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_clk_status.1004026677
Short name	T700
Test name
Test status
Simulation time	29810417 ps
CPU time	0.74 seconds
Started	May 12 01:23:05 PM PDT 24
Finished	May 12 01:23:07 PM PDT 24
Peak memory	199540 kb
Host	smart-f1e40a97-ea9a-4638-ad6a-ff9f61101f05
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004026677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.1004026677
Directory	/workspace/33.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/33.clkmgr_div_intersig_mubi.2926674405
Short name	T856
Test name
Test status
Simulation time	79439878 ps
CPU time	1.04 seconds
Started	May 12 01:23:02 PM PDT 24
Finished	May 12 01:23:04 PM PDT 24
Peak memory	200496 kb
Host	smart-da5dc30a-4eeb-4f18-adff-8a826dfe0a5f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926674405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_div_intersig_mubi.2926674405
Directory	/workspace/33.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_extclk.3943357877
Short name	T609
Test name
Test status
Simulation time	68881518 ps
CPU time	0.98 seconds
Started	May 12 01:23:05 PM PDT 24
Finished	May 12 01:23:07 PM PDT 24
Peak memory	200528 kb
Host	smart-7b49bc9b-14a6-4476-a17b-204acc06490f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943357877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.3943357877
Directory	/workspace/33.clkmgr_extclk/latest

Test location	/workspace/coverage/default/33.clkmgr_frequency.294593717
Short name	T19
Test name
Test status
Simulation time	682472751 ps
CPU time	4.15 seconds
Started	May 12 01:23:04 PM PDT 24
Finished	May 12 01:23:10 PM PDT 24
Peak memory	200416 kb
Host	smart-5e83c664-e3d5-4234-a27b-5bb1a1f73641
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294593717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.294593717
Directory	/workspace/33.clkmgr_frequency/latest

Test location	/workspace/coverage/default/33.clkmgr_frequency_timeout.473647747
Short name	T287
Test name
Test status
Simulation time	1921872141 ps
CPU time	5.98 seconds
Started	May 12 01:23:04 PM PDT 24
Finished	May 12 01:23:11 PM PDT 24
Peak memory	200624 kb
Host	smart-825bff40-0eeb-4cb4-b645-a3c76f71c902
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473647747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_ti meout.473647747
Directory	/workspace/33.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/33.clkmgr_idle_intersig_mubi.808470136
Short name	T793
Test name
Test status
Simulation time	24024548 ps
CPU time	0.94 seconds
Started	May 12 01:23:05 PM PDT 24
Finished	May 12 01:23:07 PM PDT 24
Peak memory	200472 kb
Host	smart-58488368-c605-407d-8042-7acb7913a06d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808470136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.clkmgr_idle_intersig_mubi.808470136
Directory	/workspace/33.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.2565331230
Short name	T449
Test name
Test status
Simulation time	19211332 ps
CPU time	0.8 seconds
Started	May 12 01:23:09 PM PDT 24
Finished	May 12 01:23:12 PM PDT 24
Peak memory	200512 kb
Host	smart-72c5be19-f2ad-4fc5-ad0a-b2a218174e99
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565331230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 33.clkmgr_lc_clk_byp_req_intersig_mubi.2565331230
Directory	/workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.707828519
Short name	T416
Test name
Test status
Simulation time	72407407 ps
CPU time	0.93 seconds
Started	May 12 01:23:03 PM PDT 24
Finished	May 12 01:23:04 PM PDT 24
Peak memory	200516 kb
Host	smart-6615cc92-8985-4f8c-aaf2-7c0b1702e92a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707828519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 33.clkmgr_lc_ctrl_intersig_mubi.707828519
Directory	/workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/33.clkmgr_peri.1452739497
Short name	T328
Test name
Test status
Simulation time	39386439 ps
CPU time	0.8 seconds
Started	May 12 01:23:06 PM PDT 24
Finished	May 12 01:23:08 PM PDT 24
Peak memory	200312 kb
Host	smart-af3cbf22-97f8-488f-8c5b-2a2903f25b48
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452739497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.1452739497
Directory	/workspace/33.clkmgr_peri/latest

Test location	/workspace/coverage/default/33.clkmgr_regwen.2033793287
Short name	T615
Test name
Test status
Simulation time	1310218668 ps
CPU time	5.51 seconds
Started	May 12 01:23:04 PM PDT 24
Finished	May 12 01:23:11 PM PDT 24
Peak memory	200676 kb
Host	smart-80c95bc3-2f54-4da2-a3b6-0e289a976dac
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033793287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.2033793287
Directory	/workspace/33.clkmgr_regwen/latest

Test location	/workspace/coverage/default/33.clkmgr_smoke.4023754481
Short name	T734
Test name
Test status
Simulation time	186229870 ps
CPU time	1.33 seconds
Started	May 12 01:23:04 PM PDT 24
Finished	May 12 01:23:06 PM PDT 24
Peak memory	200512 kb
Host	smart-7ba3cee7-95a5-417a-89c0-dc388005f2ac
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023754481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.4023754481
Directory	/workspace/33.clkmgr_smoke/latest

Test location	/workspace/coverage/default/33.clkmgr_stress_all.4085269463
Short name	T767
Test name
Test status
Simulation time	4560317530 ps
CPU time	33.17 seconds
Started	May 12 01:23:07 PM PDT 24
Finished	May 12 01:23:41 PM PDT 24
Peak memory	200868 kb
Host	smart-31ce8db3-c402-47f9-aabd-daf212ffb464
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085269463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all.4085269463
Directory	/workspace/33.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/33.clkmgr_stress_all_with_rand_reset.502742545
Short name	T280
Test name
Test status
Simulation time	31255257706 ps
CPU time	463.24 seconds
Started	May 12 01:23:04 PM PDT 24
Finished	May 12 01:30:49 PM PDT 24
Peak memory	209196 kb
Host	smart-a67e6206-667d-41b1-bd00-0c45b50bd98c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=502742545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.502742545
Directory	/workspace/33.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.clkmgr_trans.1294108579
Short name	T378
Test name
Test status
Simulation time	34425818 ps
CPU time	1 seconds
Started	May 12 01:23:05 PM PDT 24
Finished	May 12 01:23:07 PM PDT 24
Peak memory	200460 kb
Host	smart-e0a764fd-0ae9-4dd7-bdb0-ec8e61046669
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294108579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.1294108579
Directory	/workspace/33.clkmgr_trans/latest

Test location	/workspace/coverage/default/34.clkmgr_alert_test.3953902244
Short name	T674
Test name
Test status
Simulation time	27203677 ps
CPU time	0.76 seconds
Started	May 12 01:23:10 PM PDT 24
Finished	May 12 01:23:12 PM PDT 24
Peak memory	200532 kb
Host	smart-322f420b-5d45-49bf-be86-7fb4d2d408e6
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953902244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk mgr_alert_test.3953902244
Directory	/workspace/34.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.1617828613
Short name	T88
Test name
Test status
Simulation time	107388560 ps
CPU time	1.17 seconds
Started	May 12 01:23:08 PM PDT 24
Finished	May 12 01:23:11 PM PDT 24
Peak memory	200500 kb
Host	smart-813a5d39-6ea5-485d-8578-4323159e2e14
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617828613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_handshake_intersig_mubi.1617828613
Directory	/workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_clk_status.2933756598
Short name	T714
Test name
Test status
Simulation time	15984406 ps
CPU time	0.75 seconds
Started	May 12 01:23:10 PM PDT 24
Finished	May 12 01:23:12 PM PDT 24
Peak memory	200212 kb
Host	smart-41843d82-8eda-49e9-a0f8-9a4ebade0d32
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933756598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.2933756598
Directory	/workspace/34.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/34.clkmgr_div_intersig_mubi.3841933666
Short name	T212
Test name
Test status
Simulation time	66057406 ps
CPU time	0.99 seconds
Started	May 12 01:23:08 PM PDT 24
Finished	May 12 01:23:10 PM PDT 24
Peak memory	200504 kb
Host	smart-7b5dd303-09dc-4b66-8855-bf02ac164eaf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841933666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_div_intersig_mubi.3841933666
Directory	/workspace/34.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_extclk.40324204
Short name	T519
Test name
Test status
Simulation time	22009814 ps
CPU time	0.81 seconds
Started	May 12 01:23:02 PM PDT 24
Finished	May 12 01:23:04 PM PDT 24
Peak memory	200484 kb
Host	smart-0f5e92cd-b86c-49c2-a8dc-43c8678855f9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40324204 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.40324204
Directory	/workspace/34.clkmgr_extclk/latest

Test location	/workspace/coverage/default/34.clkmgr_frequency.2849925132
Short name	T371
Test name
Test status
Simulation time	197659746 ps
CPU time	2.19 seconds
Started	May 12 01:23:06 PM PDT 24
Finished	May 12 01:23:09 PM PDT 24
Peak memory	200552 kb
Host	smart-fb2ea3be-1cb9-4505-93bd-6d5bf9167747
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849925132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.2849925132
Directory	/workspace/34.clkmgr_frequency/latest

Test location	/workspace/coverage/default/34.clkmgr_frequency_timeout.2705566993
Short name	T336
Test name
Test status
Simulation time	378642422 ps
CPU time	2.52 seconds
Started	May 12 01:23:04 PM PDT 24
Finished	May 12 01:23:07 PM PDT 24
Peak memory	200596 kb
Host	smart-24c03096-f6ee-4281-b610-e7746fcdd733
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705566993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t imeout.2705566993
Directory	/workspace/34.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/34.clkmgr_idle_intersig_mubi.2061126408
Short name	T659
Test name
Test status
Simulation time	29180874 ps
CPU time	0.99 seconds
Started	May 12 01:23:09 PM PDT 24
Finished	May 12 01:23:11 PM PDT 24
Peak memory	200448 kb
Host	smart-e76f85d3-8cfd-4e17-8a26-6559b3d36a9e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061126408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_idle_intersig_mubi.2061126408
Directory	/workspace/34.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.1099078584
Short name	T742
Test name
Test status
Simulation time	96304165 ps
CPU time	1.03 seconds
Started	May 12 01:23:09 PM PDT 24
Finished	May 12 01:23:11 PM PDT 24
Peak memory	200520 kb
Host	smart-414461af-d379-4c3c-a348-598fcbe4aa03
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099078584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 34.clkmgr_lc_clk_byp_req_intersig_mubi.1099078584
Directory	/workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.2780337675
Short name	T312
Test name
Test status
Simulation time	152864111 ps
CPU time	1.19 seconds
Started	May 12 01:23:08 PM PDT 24
Finished	May 12 01:23:10 PM PDT 24
Peak memory	200504 kb
Host	smart-04656f59-011b-4388-b342-7dafdf0d119f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780337675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 34.clkmgr_lc_ctrl_intersig_mubi.2780337675
Directory	/workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/34.clkmgr_peri.1527518548
Short name	T778
Test name
Test status
Simulation time	41836851 ps
CPU time	0.79 seconds
Started	May 12 01:23:08 PM PDT 24
Finished	May 12 01:23:10 PM PDT 24
Peak memory	200388 kb
Host	smart-9fe933ac-e9bc-40ed-b680-e5df0201cde6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527518548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.1527518548
Directory	/workspace/34.clkmgr_peri/latest

Test location	/workspace/coverage/default/34.clkmgr_regwen.3742208237
Short name	T641
Test name
Test status
Simulation time	820552700 ps
CPU time	3.77 seconds
Started	May 12 01:23:10 PM PDT 24
Finished	May 12 01:23:15 PM PDT 24
Peak memory	200696 kb
Host	smart-61c3de76-0470-42b3-9e43-c44b2c7eccf9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742208237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.3742208237
Directory	/workspace/34.clkmgr_regwen/latest

Test location	/workspace/coverage/default/34.clkmgr_smoke.1539304942
Short name	T24
Test name
Test status
Simulation time	43347513 ps
CPU time	0.93 seconds
Started	May 12 01:23:05 PM PDT 24
Finished	May 12 01:23:07 PM PDT 24
Peak memory	200440 kb
Host	smart-e196569a-692e-4473-a03d-32b39ac63fd6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539304942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.1539304942
Directory	/workspace/34.clkmgr_smoke/latest

Test location	/workspace/coverage/default/34.clkmgr_stress_all.2514447699
Short name	T545
Test name
Test status
Simulation time	1817504098 ps
CPU time	8.3 seconds
Started	May 12 01:23:10 PM PDT 24
Finished	May 12 01:23:20 PM PDT 24
Peak memory	200808 kb
Host	smart-ce3366d5-6141-427a-b3bc-cfedaa4de0b3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514447699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all.2514447699
Directory	/workspace/34.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.487751804
Short name	T187
Test name
Test status
Simulation time	98616788845 ps
CPU time	600.28 seconds
Started	May 12 01:23:11 PM PDT 24
Finished	May 12 01:33:12 PM PDT 24
Peak memory	209136 kb
Host	smart-177bef8b-b2fa-4118-9d40-abe3133ae0eb
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=487751804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.487751804
Directory	/workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/34.clkmgr_trans.49525413
Short name	T238
Test name
Test status
Simulation time	16207318 ps
CPU time	0.74 seconds
Started	May 12 01:23:03 PM PDT 24
Finished	May 12 01:23:04 PM PDT 24
Peak memory	200376 kb
Host	smart-7023e8c7-e91e-479e-a79c-f9216b76dfa2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49525413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.49525413
Directory	/workspace/34.clkmgr_trans/latest

Test location	/workspace/coverage/default/35.clkmgr_alert_test.1707377369
Short name	T489
Test name
Test status
Simulation time	25601578 ps
CPU time	0.79 seconds
Started	May 12 01:23:14 PM PDT 24
Finished	May 12 01:23:16 PM PDT 24
Peak memory	200548 kb
Host	smart-02ccd8bd-963e-4c86-b2ec-aee4031b092d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707377369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk mgr_alert_test.1707377369
Directory	/workspace/35.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.611315579
Short name	T541
Test name
Test status
Simulation time	21954283 ps
CPU time	0.87 seconds
Started	May 12 01:23:12 PM PDT 24
Finished	May 12 01:23:14 PM PDT 24
Peak memory	200492 kb
Host	smart-4fb95c05-3abb-4a83-868a-06dbb08e60c5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611315579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_handshake_intersig_mubi.611315579
Directory	/workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_clk_status.454781387
Short name	T672
Test name
Test status
Simulation time	183686946 ps
CPU time	1.08 seconds
Started	May 12 01:23:09 PM PDT 24
Finished	May 12 01:23:11 PM PDT 24
Peak memory	200172 kb
Host	smart-91bbf7e9-d1e9-4243-b244-7ba73f756083
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454781387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.454781387
Directory	/workspace/35.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/35.clkmgr_div_intersig_mubi.2648978511
Short name	T515
Test name
Test status
Simulation time	73967191 ps
CPU time	0.95 seconds
Started	May 12 01:23:12 PM PDT 24
Finished	May 12 01:23:14 PM PDT 24
Peak memory	200504 kb
Host	smart-89a0bafb-9168-4502-8242-1a1c91b278ac
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648978511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_div_intersig_mubi.2648978511
Directory	/workspace/35.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_extclk.3554050200
Short name	T298
Test name
Test status
Simulation time	37766792 ps
CPU time	0.88 seconds
Started	May 12 01:23:10 PM PDT 24
Finished	May 12 01:23:12 PM PDT 24
Peak memory	200528 kb
Host	smart-dd69c005-8f39-4536-bc63-1c2e49b43b5a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554050200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.3554050200
Directory	/workspace/35.clkmgr_extclk/latest

Test location	/workspace/coverage/default/35.clkmgr_frequency.4177972419
Short name	T96
Test name
Test status
Simulation time	685822784 ps
CPU time	3.75 seconds
Started	May 12 01:23:09 PM PDT 24
Finished	May 12 01:23:13 PM PDT 24
Peak memory	200524 kb
Host	smart-c5b75060-737d-48ee-b7d8-f4ef1d828561
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177972419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.4177972419
Directory	/workspace/35.clkmgr_frequency/latest

Test location	/workspace/coverage/default/35.clkmgr_frequency_timeout.433011283
Short name	T383
Test name
Test status
Simulation time	1941935527 ps
CPU time	9.71 seconds
Started	May 12 01:23:10 PM PDT 24
Finished	May 12 01:23:21 PM PDT 24
Peak memory	200656 kb
Host	smart-f66e3005-1ec9-49e4-a13e-356ad7125a09
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433011283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_ti meout.433011283
Directory	/workspace/35.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/35.clkmgr_idle_intersig_mubi.1931201802
Short name	T603
Test name
Test status
Simulation time	72234534 ps
CPU time	0.93 seconds
Started	May 12 01:23:10 PM PDT 24
Finished	May 12 01:23:12 PM PDT 24
Peak memory	200428 kb
Host	smart-f9e1ebdc-bba2-4c2a-b36e-c28b5496fc9d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931201802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_idle_intersig_mubi.1931201802
Directory	/workspace/35.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.3837836305
Short name	T261
Test name
Test status
Simulation time	63774977 ps
CPU time	0.84 seconds
Started	May 12 01:23:13 PM PDT 24
Finished	May 12 01:23:15 PM PDT 24
Peak memory	200528 kb
Host	smart-1b361b83-57d9-4145-bccb-7ea0f6bd44bd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837836305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 35.clkmgr_lc_clk_byp_req_intersig_mubi.3837836305
Directory	/workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.1917295056
Short name	T51
Test name
Test status
Simulation time	73451453 ps
CPU time	0.98 seconds
Started	May 12 01:23:27 PM PDT 24
Finished	May 12 01:23:29 PM PDT 24
Peak memory	200460 kb
Host	smart-15e6f3cb-9d2d-433f-8b56-eafef4208755
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917295056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 35.clkmgr_lc_ctrl_intersig_mubi.1917295056
Directory	/workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/35.clkmgr_peri.2166910084
Short name	T450
Test name
Test status
Simulation time	17963110 ps
CPU time	0.77 seconds
Started	May 12 01:23:11 PM PDT 24
Finished	May 12 01:23:13 PM PDT 24
Peak memory	200300 kb
Host	smart-a1f5cba9-81bc-42ef-acd7-d10edbb6888f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166910084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.2166910084
Directory	/workspace/35.clkmgr_peri/latest

Test location	/workspace/coverage/default/35.clkmgr_regwen.3204285535
Short name	T498
Test name
Test status
Simulation time	511258186 ps
CPU time	2.29 seconds
Started	May 12 01:23:14 PM PDT 24
Finished	May 12 01:23:17 PM PDT 24
Peak memory	200476 kb
Host	smart-4877d9de-7880-402e-b6f9-1b95e91cf521
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204285535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.3204285535
Directory	/workspace/35.clkmgr_regwen/latest

Test location	/workspace/coverage/default/35.clkmgr_smoke.2098621687
Short name	T219
Test name
Test status
Simulation time	58201493 ps
CPU time	0.9 seconds
Started	May 12 01:23:08 PM PDT 24
Finished	May 12 01:23:10 PM PDT 24
Peak memory	200504 kb
Host	smart-141e2a4c-1320-4664-9e0d-f015a85c12cb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098621687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.2098621687
Directory	/workspace/35.clkmgr_smoke/latest

Test location	/workspace/coverage/default/35.clkmgr_stress_all.2422409832
Short name	T158
Test name
Test status
Simulation time	2673752754 ps
CPU time	18.43 seconds
Started	May 12 01:23:16 PM PDT 24
Finished	May 12 01:23:35 PM PDT 24
Peak memory	200908 kb
Host	smart-a8086edc-e848-4b5f-b8e4-2dff899276fb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422409832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all.2422409832
Directory	/workspace/35.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.2078746389
Short name	T322
Test name
Test status
Simulation time	26178322017 ps
CPU time	458.19 seconds
Started	May 12 01:23:15 PM PDT 24
Finished	May 12 01:30:54 PM PDT 24
Peak memory	217384 kb
Host	smart-e15483fd-5f9d-4ddf-8b1f-52dacc9aa936
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2078746389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.2078746389
Directory	/workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/35.clkmgr_trans.1827551293
Short name	T472
Test name
Test status
Simulation time	20855579 ps
CPU time	0.83 seconds
Started	May 12 01:23:08 PM PDT 24
Finished	May 12 01:23:10 PM PDT 24
Peak memory	200512 kb
Host	smart-23756ed0-4a7e-44e3-be5c-801c89186b21
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827551293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.1827551293
Directory	/workspace/35.clkmgr_trans/latest

Test location	/workspace/coverage/default/36.clkmgr_alert_test.4263675583
Short name	T526
Test name
Test status
Simulation time	12249106 ps
CPU time	0.74 seconds
Started	May 12 01:23:13 PM PDT 24
Finished	May 12 01:23:16 PM PDT 24
Peak memory	200516 kb
Host	smart-9adca219-8218-4872-8c30-5f1dc67f19fc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263675583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk mgr_alert_test.4263675583
Directory	/workspace/36.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.155717817
Short name	T858
Test name
Test status
Simulation time	71366287 ps
CPU time	1 seconds
Started	May 12 01:23:13 PM PDT 24
Finished	May 12 01:23:16 PM PDT 24
Peak memory	200520 kb
Host	smart-466025d3-e730-4ffb-9a4c-75a390471fcf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155717817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_handshake_intersig_mubi.155717817
Directory	/workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_clk_status.2613848811
Short name	T433
Test name
Test status
Simulation time	16486908 ps
CPU time	0.75 seconds
Started	May 12 01:23:13 PM PDT 24
Finished	May 12 01:23:15 PM PDT 24
Peak memory	199528 kb
Host	smart-f0728e3b-e35b-4ae3-abc1-958e61c374cd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613848811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.2613848811
Directory	/workspace/36.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/36.clkmgr_div_intersig_mubi.2696701015
Short name	T792
Test name
Test status
Simulation time	76701170 ps
CPU time	1.04 seconds
Started	May 12 01:23:12 PM PDT 24
Finished	May 12 01:23:14 PM PDT 24
Peak memory	200740 kb
Host	smart-bf9d2527-7edb-460c-b570-08cfd3642909
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696701015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_div_intersig_mubi.2696701015
Directory	/workspace/36.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_extclk.2500324387
Short name	T87
Test name
Test status
Simulation time	27824700 ps
CPU time	0.89 seconds
Started	May 12 01:23:11 PM PDT 24
Finished	May 12 01:23:13 PM PDT 24
Peak memory	200524 kb
Host	smart-4fa249a5-d0a2-4061-883c-9ca88c98c942
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500324387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.2500324387
Directory	/workspace/36.clkmgr_extclk/latest

Test location	/workspace/coverage/default/36.clkmgr_frequency.745159298
Short name	T648
Test name
Test status
Simulation time	682504696 ps
CPU time	4.92 seconds
Started	May 12 01:23:11 PM PDT 24
Finished	May 12 01:23:17 PM PDT 24
Peak memory	200524 kb
Host	smart-ccab7037-e0ee-4ef9-befa-701083e574d4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745159298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.745159298
Directory	/workspace/36.clkmgr_frequency/latest

Test location	/workspace/coverage/default/36.clkmgr_frequency_timeout.2306585361
Short name	T410
Test name
Test status
Simulation time	1939487124 ps
CPU time	13.71 seconds
Started	May 12 01:23:15 PM PDT 24
Finished	May 12 01:23:30 PM PDT 24
Peak memory	200624 kb
Host	smart-766113f3-c44d-46de-a5dd-4765bcb957d4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306585361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t imeout.2306585361
Directory	/workspace/36.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/36.clkmgr_idle_intersig_mubi.3990932691
Short name	T557
Test name
Test status
Simulation time	92927776 ps
CPU time	1.1 seconds
Started	May 12 01:23:12 PM PDT 24
Finished	May 12 01:23:14 PM PDT 24
Peak memory	200432 kb
Host	smart-f0d4fb7c-7adc-40cc-9f8b-61c85055c50c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990932691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_idle_intersig_mubi.3990932691
Directory	/workspace/36.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.855181450
Short name	T236
Test name
Test status
Simulation time	41062429 ps
CPU time	0.79 seconds
Started	May 12 01:23:13 PM PDT 24
Finished	May 12 01:23:15 PM PDT 24
Peak memory	200700 kb
Host	smart-03bd258c-f70d-4dc3-a2c3-a99a49c605a4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855181450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.clkmgr_lc_clk_byp_req_intersig_mubi.855181450
Directory	/workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.102761299
Short name	T235
Test name
Test status
Simulation time	80791542 ps
CPU time	1 seconds
Started	May 12 01:23:16 PM PDT 24
Finished	May 12 01:23:18 PM PDT 24
Peak memory	200508 kb
Host	smart-066e03e2-a765-4098-adc1-be383d0ce044
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102761299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.clkmgr_lc_ctrl_intersig_mubi.102761299
Directory	/workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/36.clkmgr_peri.3805194998
Short name	T349
Test name
Test status
Simulation time	14877302 ps
CPU time	0.7 seconds
Started	May 12 01:23:14 PM PDT 24
Finished	May 12 01:23:16 PM PDT 24
Peak memory	200300 kb
Host	smart-2b405ad3-d3dc-4a48-879f-80e014ddd373
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805194998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.3805194998
Directory	/workspace/36.clkmgr_peri/latest

Test location	/workspace/coverage/default/36.clkmgr_regwen.1829185644
Short name	T426
Test name
Test status
Simulation time	914987839 ps
CPU time	3.64 seconds
Started	May 12 01:23:12 PM PDT 24
Finished	May 12 01:23:17 PM PDT 24
Peak memory	200680 kb
Host	smart-c421e59c-f424-4998-9424-e8aa0beeab16
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829185644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.1829185644
Directory	/workspace/36.clkmgr_regwen/latest

Test location	/workspace/coverage/default/36.clkmgr_smoke.488787670
Short name	T820
Test name
Test status
Simulation time	33325120 ps
CPU time	0.9 seconds
Started	May 12 01:23:13 PM PDT 24
Finished	May 12 01:23:16 PM PDT 24
Peak memory	200484 kb
Host	smart-18f029db-01a3-4057-9da8-c7bdcc9eb971
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488787670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.488787670
Directory	/workspace/36.clkmgr_smoke/latest

Test location	/workspace/coverage/default/36.clkmgr_stress_all.3264535891
Short name	T758
Test name
Test status
Simulation time	841484966 ps
CPU time	4.89 seconds
Started	May 12 01:23:14 PM PDT 24
Finished	May 12 01:23:20 PM PDT 24
Peak memory	200688 kb
Host	smart-d447cc6e-deb1-47d7-9b13-5d551ec1af09
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264535891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all.3264535891
Directory	/workspace/36.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.1854645822
Short name	T14
Test name
Test status
Simulation time	28973204638 ps
CPU time	418.18 seconds
Started	May 12 01:23:12 PM PDT 24
Finished	May 12 01:30:12 PM PDT 24
Peak memory	209156 kb
Host	smart-5f81f92a-7fae-4270-bc6e-f8fc90332c44
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1854645822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.1854645822
Directory	/workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.clkmgr_trans.2566861876
Short name	T255
Test name
Test status
Simulation time	128974646 ps
CPU time	1.29 seconds
Started	May 12 01:23:14 PM PDT 24
Finished	May 12 01:23:17 PM PDT 24
Peak memory	200512 kb
Host	smart-11635da8-0703-4645-8a37-21b792e9e99c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566861876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.2566861876
Directory	/workspace/36.clkmgr_trans/latest

Test location	/workspace/coverage/default/37.clkmgr_alert_test.4085539504
Short name	T272
Test name
Test status
Simulation time	16447757 ps
CPU time	0.75 seconds
Started	May 12 01:23:17 PM PDT 24
Finished	May 12 01:23:18 PM PDT 24
Peak memory	200504 kb
Host	smart-526203d1-4602-4215-b67a-997a64fe4212
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085539504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk mgr_alert_test.4085539504
Directory	/workspace/37.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.2122883275
Short name	T573
Test name
Test status
Simulation time	41536925 ps
CPU time	0.77 seconds
Started	May 12 01:23:13 PM PDT 24
Finished	May 12 01:23:16 PM PDT 24
Peak memory	200464 kb
Host	smart-e2f60025-8987-4c6e-a247-c909dd96e0c8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122883275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_handshake_intersig_mubi.2122883275
Directory	/workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_clk_status.3211784849
Short name	T558
Test name
Test status
Simulation time	41089434 ps
CPU time	0.75 seconds
Started	May 12 01:23:11 PM PDT 24
Finished	May 12 01:23:13 PM PDT 24
Peak memory	199560 kb
Host	smart-cf2135a7-205d-4da0-8405-f86e5d23721a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211784849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.3211784849
Directory	/workspace/37.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/37.clkmgr_div_intersig_mubi.2619999244
Short name	T197
Test name
Test status
Simulation time	70344343 ps
CPU time	0.96 seconds
Started	May 12 01:23:12 PM PDT 24
Finished	May 12 01:23:15 PM PDT 24
Peak memory	200552 kb
Host	smart-38f1949e-23d0-42f1-adb8-58b31a0d3068
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619999244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_div_intersig_mubi.2619999244
Directory	/workspace/37.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_extclk.1842141995
Short name	T259
Test name
Test status
Simulation time	18411952 ps
CPU time	0.8 seconds
Started	May 12 01:23:14 PM PDT 24
Finished	May 12 01:23:16 PM PDT 24
Peak memory	200496 kb
Host	smart-5cf0d685-b1c0-4859-9ea9-35532d242daa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842141995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.1842141995
Directory	/workspace/37.clkmgr_extclk/latest

Test location	/workspace/coverage/default/37.clkmgr_frequency.1724868870
Short name	T389
Test name
Test status
Simulation time	681558633 ps
CPU time	5.92 seconds
Started	May 12 01:23:13 PM PDT 24
Finished	May 12 01:23:21 PM PDT 24
Peak memory	200560 kb
Host	smart-0ada04d0-76be-4dc8-b422-f0235e4fd7b0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724868870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.1724868870
Directory	/workspace/37.clkmgr_frequency/latest

Test location	/workspace/coverage/default/37.clkmgr_frequency_timeout.3885510143
Short name	T23
Test name
Test status
Simulation time	982636588 ps
CPU time	7.28 seconds
Started	May 12 01:23:12 PM PDT 24
Finished	May 12 01:23:21 PM PDT 24
Peak memory	200668 kb
Host	smart-cf4dc797-279d-4a13-b8b8-92a659796e2c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885510143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t imeout.3885510143
Directory	/workspace/37.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/37.clkmgr_idle_intersig_mubi.1286991314
Short name	T715
Test name
Test status
Simulation time	24893847 ps
CPU time	0.85 seconds
Started	May 12 01:23:12 PM PDT 24
Finished	May 12 01:23:14 PM PDT 24
Peak memory	200512 kb
Host	smart-7a46e43b-be00-4e44-a682-2c43d2b65989
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286991314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_idle_intersig_mubi.1286991314
Directory	/workspace/37.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.3831560457
Short name	T317
Test name
Test status
Simulation time	259897797 ps
CPU time	1.49 seconds
Started	May 12 01:23:15 PM PDT 24
Finished	May 12 01:23:17 PM PDT 24
Peak memory	200500 kb
Host	smart-aa655dd4-472a-4fce-9aba-88704a76bcc9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831560457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 37.clkmgr_lc_clk_byp_req_intersig_mubi.3831560457
Directory	/workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.557971616
Short name	T773
Test name
Test status
Simulation time	22965246 ps
CPU time	0.84 seconds
Started	May 12 01:23:13 PM PDT 24
Finished	May 12 01:23:16 PM PDT 24
Peak memory	200488 kb
Host	smart-5da6c551-38fe-4233-85a5-94d1d2277278
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557971616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.clkmgr_lc_ctrl_intersig_mubi.557971616
Directory	/workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/37.clkmgr_peri.2179166263
Short name	T556
Test name
Test status
Simulation time	44124700 ps
CPU time	0.78 seconds
Started	May 12 01:23:17 PM PDT 24
Finished	May 12 01:23:18 PM PDT 24
Peak memory	200268 kb
Host	smart-19553458-2776-4a78-8840-c01dadc558eb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179166263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.2179166263
Directory	/workspace/37.clkmgr_peri/latest

Test location	/workspace/coverage/default/37.clkmgr_regwen.626060751
Short name	T248
Test name
Test status
Simulation time	1216351745 ps
CPU time	5.26 seconds
Started	May 12 01:23:17 PM PDT 24
Finished	May 12 01:23:23 PM PDT 24
Peak memory	200608 kb
Host	smart-0f4e52e0-8530-4c18-8f14-9d328b75d86d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626060751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.626060751
Directory	/workspace/37.clkmgr_regwen/latest

Test location	/workspace/coverage/default/37.clkmgr_smoke.4033174443
Short name	T438
Test name
Test status
Simulation time	19388783 ps
CPU time	0.83 seconds
Started	May 12 01:23:13 PM PDT 24
Finished	May 12 01:23:16 PM PDT 24
Peak memory	200704 kb
Host	smart-a723b7a1-6739-437d-82b6-b5dccf378c9a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033174443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.4033174443
Directory	/workspace/37.clkmgr_smoke/latest

Test location	/workspace/coverage/default/37.clkmgr_stress_all.427956033
Short name	T347
Test name
Test status
Simulation time	26324526 ps
CPU time	0.84 seconds
Started	May 12 01:23:16 PM PDT 24
Finished	May 12 01:23:18 PM PDT 24
Peak memory	200324 kb
Host	smart-6d68a829-21cf-4c37-a987-7f774e0e9b7b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427956033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all.427956033
Directory	/workspace/37.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.4063622593
Short name	T327
Test name
Test status
Simulation time	16718582699 ps
CPU time	247.05 seconds
Started	May 12 01:23:16 PM PDT 24
Finished	May 12 01:27:24 PM PDT 24
Peak memory	209196 kb
Host	smart-902e7d48-00a9-4753-b80c-151ac5f0638a
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4063622593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.4063622593
Directory	/workspace/37.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/37.clkmgr_trans.809661678
Short name	T521
Test name
Test status
Simulation time	31357270 ps
CPU time	0.96 seconds
Started	May 12 01:23:14 PM PDT 24
Finished	May 12 01:23:16 PM PDT 24
Peak memory	200500 kb
Host	smart-ab58bc0d-62c0-4dbe-b88f-1bb01b23dd5f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809661678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.809661678
Directory	/workspace/37.clkmgr_trans/latest

Test location	/workspace/coverage/default/38.clkmgr_alert_test.3618767745
Short name	T390
Test name
Test status
Simulation time	27239648 ps
CPU time	0.83 seconds
Started	May 12 01:23:16 PM PDT 24
Finished	May 12 01:23:17 PM PDT 24
Peak memory	200592 kb
Host	smart-aed9c2c9-bdc7-4db0-b9a3-2f540fa8e9f1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618767745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk mgr_alert_test.3618767745
Directory	/workspace/38.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.3536209697
Short name	T108
Test name
Test status
Simulation time	270238896 ps
CPU time	1.59 seconds
Started	May 12 01:23:16 PM PDT 24
Finished	May 12 01:23:19 PM PDT 24
Peak memory	200736 kb
Host	smart-9967380b-0adb-4bcb-a922-0c6839a6c2b8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536209697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_handshake_intersig_mubi.3536209697
Directory	/workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_clk_status.1830446124
Short name	T374
Test name
Test status
Simulation time	17795489 ps
CPU time	0.74 seconds
Started	May 12 01:23:17 PM PDT 24
Finished	May 12 01:23:19 PM PDT 24
Peak memory	199492 kb
Host	smart-7abec474-132f-45ca-a57e-e678d5a33678
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830446124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.1830446124
Directory	/workspace/38.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/38.clkmgr_div_intersig_mubi.212583653
Short name	T486
Test name
Test status
Simulation time	57273546 ps
CPU time	0.87 seconds
Started	May 12 01:23:17 PM PDT 24
Finished	May 12 01:23:18 PM PDT 24
Peak memory	200480 kb
Host	smart-f26213c9-f53b-490b-98a2-89d6588ac879
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212583653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.clkmgr_div_intersig_mubi.212583653
Directory	/workspace/38.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_frequency.1980496709
Short name	T693
Test name
Test status
Simulation time	1037127414 ps
CPU time	8.34 seconds
Started	May 12 01:23:17 PM PDT 24
Finished	May 12 01:23:26 PM PDT 24
Peak memory	200572 kb
Host	smart-8d3e8cf0-bf16-4222-9380-ffc6cfeb6ea7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980496709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.1980496709
Directory	/workspace/38.clkmgr_frequency/latest

Test location	/workspace/coverage/default/38.clkmgr_frequency_timeout.1927303344
Short name	T655
Test name
Test status
Simulation time	2415275800 ps
CPU time	16.75 seconds
Started	May 12 01:23:16 PM PDT 24
Finished	May 12 01:23:34 PM PDT 24
Peak memory	200848 kb
Host	smart-923a45d6-7525-4988-8cc5-327d00b26821
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927303344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t imeout.1927303344
Directory	/workspace/38.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/38.clkmgr_idle_intersig_mubi.3975145538
Short name	T31
Test name
Test status
Simulation time	24451249 ps
CPU time	0.91 seconds
Started	May 12 01:23:16 PM PDT 24
Finished	May 12 01:23:17 PM PDT 24
Peak memory	200452 kb
Host	smart-3cbd59f9-70c6-40fc-a19a-37c57dbb18bb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975145538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_idle_intersig_mubi.3975145538
Directory	/workspace/38.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.3655360181
Short name	T64
Test name
Test status
Simulation time	17469899 ps
CPU time	0.75 seconds
Started	May 12 01:23:19 PM PDT 24
Finished	May 12 01:23:20 PM PDT 24
Peak memory	200456 kb
Host	smart-590dbdad-892f-40fc-a0ec-a1c225de7e3d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655360181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 38.clkmgr_lc_clk_byp_req_intersig_mubi.3655360181
Directory	/workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.815060916
Short name	T333
Test name
Test status
Simulation time	25299200 ps
CPU time	0.88 seconds
Started	May 12 01:23:17 PM PDT 24
Finished	May 12 01:23:19 PM PDT 24
Peak memory	200532 kb
Host	smart-64bb29eb-adf4-4a7c-843b-140bee91a4d0
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815060916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.clkmgr_lc_ctrl_intersig_mubi.815060916
Directory	/workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/38.clkmgr_peri.2025684048
Short name	T799
Test name
Test status
Simulation time	17879708 ps
CPU time	0.75 seconds
Started	May 12 01:23:19 PM PDT 24
Finished	May 12 01:23:20 PM PDT 24
Peak memory	200296 kb
Host	smart-970f91cc-9ba0-4505-a4ee-8f896cebc777
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025684048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.2025684048
Directory	/workspace/38.clkmgr_peri/latest

Test location	/workspace/coverage/default/38.clkmgr_regwen.1104339670
Short name	T796
Test name
Test status
Simulation time	771976523 ps
CPU time	3.24 seconds
Started	May 12 01:23:16 PM PDT 24
Finished	May 12 01:23:20 PM PDT 24
Peak memory	200788 kb
Host	smart-ddee2909-db84-4c74-b267-1a8711dd8fe2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104339670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.1104339670
Directory	/workspace/38.clkmgr_regwen/latest

Test location	/workspace/coverage/default/38.clkmgr_smoke.4107368056
Short name	T536
Test name
Test status
Simulation time	17357339 ps
CPU time	0.84 seconds
Started	May 12 01:23:15 PM PDT 24
Finished	May 12 01:23:17 PM PDT 24
Peak memory	200516 kb
Host	smart-98339fb0-5fc8-4fd4-b8ce-90ea661594ac
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107368056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.4107368056
Directory	/workspace/38.clkmgr_smoke/latest

Test location	/workspace/coverage/default/38.clkmgr_stress_all.1775081435
Short name	T626
Test name
Test status
Simulation time	6010318928 ps
CPU time	24.51 seconds
Started	May 12 01:23:18 PM PDT 24
Finished	May 12 01:23:43 PM PDT 24
Peak memory	200896 kb
Host	smart-f3a7c600-4de5-4fda-8f16-c93c64ed5ee3
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775081435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all.1775081435
Directory	/workspace/38.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.3395201006
Short name	T670
Test name
Test status
Simulation time	18385345787 ps
CPU time	334.91 seconds
Started	May 12 01:23:18 PM PDT 24
Finished	May 12 01:28:54 PM PDT 24
Peak memory	209140 kb
Host	smart-754e6521-060e-4c99-9f36-1bbeda601130
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3395201006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.3395201006
Directory	/workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.clkmgr_trans.512599898
Short name	T227
Test name
Test status
Simulation time	20955731 ps
CPU time	0.81 seconds
Started	May 12 01:23:16 PM PDT 24
Finished	May 12 01:23:18 PM PDT 24
Peak memory	200504 kb
Host	smart-dc0cfc45-ea64-4a44-b8c0-378fac217145
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512599898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.512599898
Directory	/workspace/38.clkmgr_trans/latest

Test location	/workspace/coverage/default/39.clkmgr_alert_test.205465205
Short name	T332
Test name
Test status
Simulation time	14927202 ps
CPU time	0.74 seconds
Started	May 12 01:23:20 PM PDT 24
Finished	May 12 01:23:21 PM PDT 24
Peak memory	200564 kb
Host	smart-07a68076-58cf-43b3-aafe-2a6012b98768
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205465205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkm gr_alert_test.205465205
Directory	/workspace/39.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.584006376
Short name	T442
Test name
Test status
Simulation time	35479330 ps
CPU time	0.95 seconds
Started	May 12 01:23:27 PM PDT 24
Finished	May 12 01:23:29 PM PDT 24
Peak memory	200420 kb
Host	smart-9696e736-de99-4bf9-bb0f-8ca0309a2d3f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584006376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_handshake_intersig_mubi.584006376
Directory	/workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_clk_status.3365754268
Short name	T362
Test name
Test status
Simulation time	31259140 ps
CPU time	0.76 seconds
Started	May 12 01:23:22 PM PDT 24
Finished	May 12 01:23:23 PM PDT 24
Peak memory	200228 kb
Host	smart-2aa2f4fe-766d-43ed-a631-f2c737f7a49f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365754268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.3365754268
Directory	/workspace/39.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/39.clkmgr_div_intersig_mubi.2413661405
Short name	T569
Test name
Test status
Simulation time	17308044 ps
CPU time	0.74 seconds
Started	May 12 01:23:25 PM PDT 24
Finished	May 12 01:23:26 PM PDT 24
Peak memory	200468 kb
Host	smart-168317a1-cfef-452d-b374-d79cac7c3860
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413661405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_div_intersig_mubi.2413661405
Directory	/workspace/39.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_extclk.3010452523
Short name	T491
Test name
Test status
Simulation time	65957115 ps
CPU time	0.97 seconds
Started	May 12 01:23:19 PM PDT 24
Finished	May 12 01:23:21 PM PDT 24
Peak memory	200500 kb
Host	smart-6d183682-e3e8-401f-9255-8519be683f7e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010452523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.3010452523
Directory	/workspace/39.clkmgr_extclk/latest

Test location	/workspace/coverage/default/39.clkmgr_frequency.3087731763
Short name	T590
Test name
Test status
Simulation time	2484560203 ps
CPU time	13.14 seconds
Started	May 12 01:23:18 PM PDT 24
Finished	May 12 01:23:31 PM PDT 24
Peak memory	200804 kb
Host	smart-4fe7c183-514b-4e1b-afed-c136ce92c2ba
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087731763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.3087731763
Directory	/workspace/39.clkmgr_frequency/latest

Test location	/workspace/coverage/default/39.clkmgr_frequency_timeout.3981275486
Short name	T191
Test name
Test status
Simulation time	1766626920 ps
CPU time	6 seconds
Started	May 12 01:23:21 PM PDT 24
Finished	May 12 01:23:27 PM PDT 24
Peak memory	200624 kb
Host	smart-6a7a6c6b-ed5f-45c3-aa04-3cd51aca9bf6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981275486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t imeout.3981275486
Directory	/workspace/39.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/39.clkmgr_idle_intersig_mubi.1971760580
Short name	T706
Test name
Test status
Simulation time	65312628 ps
CPU time	0.94 seconds
Started	May 12 01:23:23 PM PDT 24
Finished	May 12 01:23:24 PM PDT 24
Peak memory	200508 kb
Host	smart-feba6c4a-8dbd-4a31-b430-658f495d9b81
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971760580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_idle_intersig_mubi.1971760580
Directory	/workspace/39.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.1330861707
Short name	T835
Test name
Test status
Simulation time	59272646 ps
CPU time	0.9 seconds
Started	May 12 01:23:19 PM PDT 24
Finished	May 12 01:23:21 PM PDT 24
Peak memory	200512 kb
Host	smart-61e93ca9-3038-4d1f-8ace-57c41c280f5b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330861707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 39.clkmgr_lc_clk_byp_req_intersig_mubi.1330861707
Directory	/workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.3851313195
Short name	T258
Test name
Test status
Simulation time	52017642 ps
CPU time	0.9 seconds
Started	May 12 01:23:20 PM PDT 24
Finished	May 12 01:23:21 PM PDT 24
Peak memory	200532 kb
Host	smart-9824a550-218e-44c8-90a7-710674a346d1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851313195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 39.clkmgr_lc_ctrl_intersig_mubi.3851313195
Directory	/workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/39.clkmgr_peri.3338860645
Short name	T801
Test name
Test status
Simulation time	129972217 ps
CPU time	1.01 seconds
Started	May 12 01:23:22 PM PDT 24
Finished	May 12 01:23:24 PM PDT 24
Peak memory	200292 kb
Host	smart-eff31e34-a758-4c68-9bca-3e7d58ffc036
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338860645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.3338860645
Directory	/workspace/39.clkmgr_peri/latest

Test location	/workspace/coverage/default/39.clkmgr_smoke.328141053
Short name	T756
Test name
Test status
Simulation time	52453279 ps
CPU time	0.93 seconds
Started	May 12 01:23:17 PM PDT 24
Finished	May 12 01:23:18 PM PDT 24
Peak memory	200512 kb
Host	smart-2e051f90-0c9e-4897-b3ba-d8f5cf9a6f22
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328141053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.328141053
Directory	/workspace/39.clkmgr_smoke/latest

Test location	/workspace/coverage/default/39.clkmgr_stress_all.62994132
Short name	T323
Test name
Test status
Simulation time	8488454544 ps
CPU time	32.05 seconds
Started	May 12 01:23:22 PM PDT 24
Finished	May 12 01:23:54 PM PDT 24
Peak memory	200916 kb
Host	smart-c007de54-ad14-4ccd-b0e6-d330ff125fab
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62994132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_ TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 9.clkmgr_stress_all.62994132
Directory	/workspace/39.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.3815397545
Short name	T709
Test name
Test status
Simulation time	22685658641 ps
CPU time	396.72 seconds
Started	May 12 01:23:22 PM PDT 24
Finished	May 12 01:29:59 PM PDT 24
Peak memory	217260 kb
Host	smart-3fbc0b28-00e9-4269-8642-dfdd1f9e4f4c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3815397545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.3815397545
Directory	/workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.clkmgr_trans.3151697845
Short name	T204
Test name
Test status
Simulation time	70796985 ps
CPU time	0.92 seconds
Started	May 12 01:23:23 PM PDT 24
Finished	May 12 01:23:24 PM PDT 24
Peak memory	200500 kb
Host	smart-89193839-06f8-4bf4-88b2-f90189689981
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151697845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.3151697845
Directory	/workspace/39.clkmgr_trans/latest

Test location	/workspace/coverage/default/4.clkmgr_alert_test.4033199379
Short name	T478
Test name
Test status
Simulation time	18933312 ps
CPU time	0.83 seconds
Started	May 12 01:21:36 PM PDT 24
Finished	May 12 01:21:37 PM PDT 24
Peak memory	200596 kb
Host	smart-ef567cf8-5609-463e-b35a-7c9f37d53d13
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033199379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm gr_alert_test.4033199379
Directory	/workspace/4.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.953686340
Short name	T642
Test name
Test status
Simulation time	290225938 ps
CPU time	1.53 seconds
Started	May 12 01:21:36 PM PDT 24
Finished	May 12 01:21:38 PM PDT 24
Peak memory	200528 kb
Host	smart-26af2f03-ced0-467e-9a51-1c1c141f9279
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953686340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_handshake_intersig_mubi.953686340
Directory	/workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_clk_status.258949589
Short name	T584
Test name
Test status
Simulation time	17789879 ps
CPU time	0.76 seconds
Started	May 12 01:21:32 PM PDT 24
Finished	May 12 01:21:33 PM PDT 24
Peak memory	200248 kb
Host	smart-25c71650-08a0-48aa-80c2-5040662592f7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258949589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.258949589
Directory	/workspace/4.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/4.clkmgr_div_intersig_mubi.2467099287
Short name	T647
Test name
Test status
Simulation time	128167937 ps
CPU time	1.11 seconds
Started	May 12 01:21:35 PM PDT 24
Finished	May 12 01:21:36 PM PDT 24
Peak memory	200460 kb
Host	smart-3feeca9d-9dab-4faa-917d-8ac29c455719
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467099287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_div_intersig_mubi.2467099287
Directory	/workspace/4.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_extclk.4030377075
Short name	T462
Test name
Test status
Simulation time	64747141 ps
CPU time	1.01 seconds
Started	May 12 01:21:33 PM PDT 24
Finished	May 12 01:21:34 PM PDT 24
Peak memory	200480 kb
Host	smart-914b836b-3fe7-474f-a195-67da1df0d8b2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030377075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.4030377075
Directory	/workspace/4.clkmgr_extclk/latest

Test location	/workspace/coverage/default/4.clkmgr_frequency.459009184
Short name	T132
Test name
Test status
Simulation time	212309051 ps
CPU time	1.77 seconds
Started	May 12 01:21:36 PM PDT 24
Finished	May 12 01:21:38 PM PDT 24
Peak memory	200500 kb
Host	smart-9b1766db-fdc0-4dc4-b60d-d9e4f9b4f22e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459009184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.459009184
Directory	/workspace/4.clkmgr_frequency/latest

Test location	/workspace/coverage/default/4.clkmgr_frequency_timeout.3122707416
Short name	T241
Test name
Test status
Simulation time	2063894828 ps
CPU time	14.36 seconds
Started	May 12 01:21:33 PM PDT 24
Finished	May 12 01:21:48 PM PDT 24
Peak memory	200804 kb
Host	smart-596e87e0-1551-4a8e-8ec6-7432a4799e04
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122707416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti meout.3122707416
Directory	/workspace/4.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/4.clkmgr_idle_intersig_mubi.156204381
Short name	T493
Test name
Test status
Simulation time	40923964 ps
CPU time	0.91 seconds
Started	May 12 01:21:31 PM PDT 24
Finished	May 12 01:21:32 PM PDT 24
Peak memory	200500 kb
Host	smart-9e3f1448-6f3e-4741-b204-9b669243ed85
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156204381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .clkmgr_idle_intersig_mubi.156204381
Directory	/workspace/4.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.2196853273
Short name	T316
Test name
Test status
Simulation time	26487309 ps
CPU time	0.76 seconds
Started	May 12 01:21:35 PM PDT 24
Finished	May 12 01:21:36 PM PDT 24
Peak memory	200480 kb
Host	smart-25f39684-d249-4de2-9b1e-5d65463f41cd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196853273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 4.clkmgr_lc_clk_byp_req_intersig_mubi.2196853273
Directory	/workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.1744837051
Short name	T221
Test name
Test status
Simulation time	288634828 ps
CPU time	1.61 seconds
Started	May 12 01:21:35 PM PDT 24
Finished	May 12 01:21:37 PM PDT 24
Peak memory	200456 kb
Host	smart-6e55b434-cf52-409d-a947-bde3564178e5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744837051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 4.clkmgr_lc_ctrl_intersig_mubi.1744837051
Directory	/workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/4.clkmgr_peri.3367453358
Short name	T552
Test name
Test status
Simulation time	14693209 ps
CPU time	0.77 seconds
Started	May 12 01:21:31 PM PDT 24
Finished	May 12 01:21:33 PM PDT 24
Peak memory	200516 kb
Host	smart-aa9df4b4-5698-4620-b3fb-43e87ac5faa2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367453358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.3367453358
Directory	/workspace/4.clkmgr_peri/latest

Test location	/workspace/coverage/default/4.clkmgr_regwen.766961919
Short name	T355
Test name
Test status
Simulation time	1644844080 ps
CPU time	6 seconds
Started	May 12 01:21:38 PM PDT 24
Finished	May 12 01:21:44 PM PDT 24
Peak memory	200572 kb
Host	smart-4b655f34-d45f-4847-b6c8-e8c4c24ba6c2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766961919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.766961919
Directory	/workspace/4.clkmgr_regwen/latest

Test location	/workspace/coverage/default/4.clkmgr_sec_cm.2350902693
Short name	T48
Test name
Test status
Simulation time	310331438 ps
CPU time	3.28 seconds
Started	May 12 01:21:36 PM PDT 24
Finished	May 12 01:21:40 PM PDT 24
Peak memory	215928 kb
Host	smart-1679c931-20ed-4e3a-a162-003fa31a9566
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350902693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg r_sec_cm.2350902693
Directory	/workspace/4.clkmgr_sec_cm/latest

Test location	/workspace/coverage/default/4.clkmgr_smoke.211082057
Short name	T814
Test name
Test status
Simulation time	19182670 ps
CPU time	0.84 seconds
Started	May 12 01:21:31 PM PDT 24
Finished	May 12 01:21:32 PM PDT 24
Peak memory	200460 kb
Host	smart-1ee87504-e69e-4274-b599-1f0bb5124168
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211082057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.211082057
Directory	/workspace/4.clkmgr_smoke/latest

Test location	/workspace/coverage/default/4.clkmgr_stress_all.1102467731
Short name	T830
Test name
Test status
Simulation time	77377255 ps
CPU time	1.33 seconds
Started	May 12 01:21:36 PM PDT 24
Finished	May 12 01:21:38 PM PDT 24
Peak memory	200600 kb
Host	smart-91f36f6a-d8d3-46e6-9836-fa6e62963022
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102467731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all.1102467731
Directory	/workspace/4.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/4.clkmgr_trans.3180029
Short name	T540
Test name
Test status
Simulation time	77460304 ps
CPU time	0.96 seconds
Started	May 12 01:21:31 PM PDT 24
Finished	May 12 01:21:33 PM PDT 24
Peak memory	200532 kb
Host	smart-c2479dbe-5d54-4846-ab8c-1204b2d882db
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.3180029
Directory	/workspace/4.clkmgr_trans/latest

Test location	/workspace/coverage/default/40.clkmgr_alert_test.1097901214
Short name	T553
Test name
Test status
Simulation time	38409816 ps
CPU time	0.81 seconds
Started	May 12 01:23:25 PM PDT 24
Finished	May 12 01:23:26 PM PDT 24
Peak memory	200552 kb
Host	smart-6579439a-8ea9-47f8-b7d1-0ae2eaf9f208
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097901214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk mgr_alert_test.1097901214
Directory	/workspace/40.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.760437670
Short name	T565
Test name
Test status
Simulation time	14954301 ps
CPU time	0.79 seconds
Started	May 12 01:23:21 PM PDT 24
Finished	May 12 01:23:22 PM PDT 24
Peak memory	200480 kb
Host	smart-eb15c8a0-9e69-416a-bde8-5a1f502379d5
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760437670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_handshake_intersig_mubi.760437670
Directory	/workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_clk_status.2608530247
Short name	T611
Test name
Test status
Simulation time	57188318 ps
CPU time	0.85 seconds
Started	May 12 01:23:21 PM PDT 24
Finished	May 12 01:23:22 PM PDT 24
Peak memory	199536 kb
Host	smart-abb25681-8a14-45eb-958a-a033c4331023
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608530247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.2608530247
Directory	/workspace/40.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/40.clkmgr_div_intersig_mubi.2398178147
Short name	T784
Test name
Test status
Simulation time	64557842 ps
CPU time	0.98 seconds
Started	May 12 01:23:24 PM PDT 24
Finished	May 12 01:23:25 PM PDT 24
Peak memory	200504 kb
Host	smart-09f5c991-653f-4e06-b038-569c1b4606bf
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398178147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_div_intersig_mubi.2398178147
Directory	/workspace/40.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_extclk.1945487035
Short name	T65
Test name
Test status
Simulation time	37326590 ps
CPU time	0.8 seconds
Started	May 12 01:23:24 PM PDT 24
Finished	May 12 01:23:26 PM PDT 24
Peak memory	200496 kb
Host	smart-cb08ce9b-3a08-4971-a0de-d2aee6ae086e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945487035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.1945487035
Directory	/workspace/40.clkmgr_extclk/latest

Test location	/workspace/coverage/default/40.clkmgr_frequency.593740733
Short name	T63
Test name
Test status
Simulation time	918431326 ps
CPU time	7.35 seconds
Started	May 12 01:23:23 PM PDT 24
Finished	May 12 01:23:31 PM PDT 24
Peak memory	200528 kb
Host	smart-402b8c3c-d4d0-4d41-a4aa-8b07c91f82e6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593740733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.593740733
Directory	/workspace/40.clkmgr_frequency/latest

Test location	/workspace/coverage/default/40.clkmgr_frequency_timeout.2292072134
Short name	T831
Test name
Test status
Simulation time	148602605 ps
CPU time	1.39 seconds
Started	May 12 01:23:27 PM PDT 24
Finished	May 12 01:23:29 PM PDT 24
Peak memory	200564 kb
Host	smart-86e1772e-aa60-4a7a-8780-b1e98c9d2ede
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292072134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t imeout.2292072134
Directory	/workspace/40.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/40.clkmgr_idle_intersig_mubi.3179520987
Short name	T676
Test name
Test status
Simulation time	26763410 ps
CPU time	0.97 seconds
Started	May 12 01:23:25 PM PDT 24
Finished	May 12 01:23:26 PM PDT 24
Peak memory	200412 kb
Host	smart-3b9db97b-57cc-4bc2-9dc2-83db0f5f6141
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179520987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_idle_intersig_mubi.3179520987
Directory	/workspace/40.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.1192399182
Short name	T276
Test name
Test status
Simulation time	65108259 ps
CPU time	0.98 seconds
Started	May 12 01:23:21 PM PDT 24
Finished	May 12 01:23:22 PM PDT 24
Peak memory	200516 kb
Host	smart-e72a9d13-e8e1-4392-b234-19ecb3d94e64
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192399182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 40.clkmgr_lc_clk_byp_req_intersig_mubi.1192399182
Directory	/workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.3450739160
Short name	T162
Test name
Test status
Simulation time	28199242 ps
CPU time	0.97 seconds
Started	May 12 01:23:20 PM PDT 24
Finished	May 12 01:23:22 PM PDT 24
Peak memory	200512 kb
Host	smart-0a2e9fe4-b102-4abb-a6f5-b0bcb32d98ea
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450739160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 40.clkmgr_lc_ctrl_intersig_mubi.3450739160
Directory	/workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/40.clkmgr_peri.97353519
Short name	T809
Test name
Test status
Simulation time	34042896 ps
CPU time	0.77 seconds
Started	May 12 01:23:22 PM PDT 24
Finished	May 12 01:23:23 PM PDT 24
Peak memory	200312 kb
Host	smart-30cb8da1-b466-4466-b05a-f1c5f49ea3ca
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97353519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.97353519
Directory	/workspace/40.clkmgr_peri/latest

Test location	/workspace/coverage/default/40.clkmgr_regwen.1635621836
Short name	T772
Test name
Test status
Simulation time	803081035 ps
CPU time	2.81 seconds
Started	May 12 01:23:23 PM PDT 24
Finished	May 12 01:23:26 PM PDT 24
Peak memory	200528 kb
Host	smart-c0cc428d-6ddf-4519-8066-b07dc97a8efb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635621836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.1635621836
Directory	/workspace/40.clkmgr_regwen/latest

Test location	/workspace/coverage/default/40.clkmgr_smoke.2295953866
Short name	T825
Test name
Test status
Simulation time	39174218 ps
CPU time	0.9 seconds
Started	May 12 01:23:22 PM PDT 24
Finished	May 12 01:23:23 PM PDT 24
Peak memory	200440 kb
Host	smart-6ad4733c-1883-402f-a5e1-6b4a13662b20
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295953866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.2295953866
Directory	/workspace/40.clkmgr_smoke/latest

Test location	/workspace/coverage/default/40.clkmgr_stress_all.1716823468
Short name	T407
Test name
Test status
Simulation time	2811368641 ps
CPU time	14.04 seconds
Started	May 12 01:23:23 PM PDT 24
Finished	May 12 01:23:37 PM PDT 24
Peak memory	200904 kb
Host	smart-26752ad8-a790-438d-b63d-846f1a14847b
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716823468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all.1716823468
Directory	/workspace/40.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/40.clkmgr_stress_all_with_rand_reset.269787493
Short name	T580
Test name
Test status
Simulation time	24757982566 ps
CPU time	221.22 seconds
Started	May 12 01:23:24 PM PDT 24
Finished	May 12 01:27:05 PM PDT 24
Peak memory	209220 kb
Host	smart-aaf23b80-225f-4924-bfee-5e35876399ca
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=269787493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.269787493
Directory	/workspace/40.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/40.clkmgr_trans.372163292
Short name	T482
Test name
Test status
Simulation time	31323079 ps
CPU time	0.78 seconds
Started	May 12 01:23:20 PM PDT 24
Finished	May 12 01:23:21 PM PDT 24
Peak memory	200480 kb
Host	smart-b52809f0-db08-46cb-9545-5d3361159249
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372163292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.372163292
Directory	/workspace/40.clkmgr_trans/latest

Test location	/workspace/coverage/default/41.clkmgr_alert_test.2711004476
Short name	T37
Test name
Test status
Simulation time	18737233 ps
CPU time	0.78 seconds
Started	May 12 01:23:29 PM PDT 24
Finished	May 12 01:23:31 PM PDT 24
Peak memory	200556 kb
Host	smart-3c6944de-cab7-4a1a-b94f-c5528ea5d292
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711004476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk mgr_alert_test.2711004476
Directory	/workspace/41.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.3366458011
Short name	T439
Test name
Test status
Simulation time	70967205 ps
CPU time	0.99 seconds
Started	May 12 01:23:25 PM PDT 24
Finished	May 12 01:23:27 PM PDT 24
Peak memory	200432 kb
Host	smart-eddcfaa5-88c3-4d69-80f5-ee065446615d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366458011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_handshake_intersig_mubi.3366458011
Directory	/workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_clk_status.945439548
Short name	T610
Test name
Test status
Simulation time	14772385 ps
CPU time	0.74 seconds
Started	May 12 01:23:30 PM PDT 24
Finished	May 12 01:23:32 PM PDT 24
Peak memory	199500 kb
Host	smart-83a95a43-9cc3-4bd8-adc0-2cef56232c9a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945439548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.945439548
Directory	/workspace/41.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/41.clkmgr_div_intersig_mubi.241469464
Short name	T435
Test name
Test status
Simulation time	21945707 ps
CPU time	0.83 seconds
Started	May 12 01:23:28 PM PDT 24
Finished	May 12 01:23:30 PM PDT 24
Peak memory	200396 kb
Host	smart-f58988c6-c9be-43ca-beaa-6663b29de3f9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241469464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.clkmgr_div_intersig_mubi.241469464
Directory	/workspace/41.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_extclk.983952766
Short name	T789
Test name
Test status
Simulation time	44207447 ps
CPU time	0.87 seconds
Started	May 12 01:23:29 PM PDT 24
Finished	May 12 01:23:32 PM PDT 24
Peak memory	200480 kb
Host	smart-479a3bd8-1971-4e7c-9641-4961f8bc1c17
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983952766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.983952766
Directory	/workspace/41.clkmgr_extclk/latest

Test location	/workspace/coverage/default/41.clkmgr_frequency.4206791824
Short name	T308
Test name
Test status
Simulation time	588122799 ps
CPU time	3.43 seconds
Started	May 12 01:23:27 PM PDT 24
Finished	May 12 01:23:31 PM PDT 24
Peak memory	200524 kb
Host	smart-63a7291f-6dd6-4d8d-8305-717796c9041a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206791824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.4206791824
Directory	/workspace/41.clkmgr_frequency/latest

Test location	/workspace/coverage/default/41.clkmgr_frequency_timeout.2375213623
Short name	T22
Test name
Test status
Simulation time	1373829261 ps
CPU time	5.24 seconds
Started	May 12 01:23:26 PM PDT 24
Finished	May 12 01:23:32 PM PDT 24
Peak memory	200624 kb
Host	smart-ceb41925-fba8-4d4f-b780-3f666e30f7a3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375213623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t imeout.2375213623
Directory	/workspace/41.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/41.clkmgr_idle_intersig_mubi.4101277504
Short name	T41
Test name
Test status
Simulation time	17422835 ps
CPU time	0.79 seconds
Started	May 12 01:23:27 PM PDT 24
Finished	May 12 01:23:29 PM PDT 24
Peak memory	200476 kb
Host	smart-e45ed8ab-e29f-410b-9c51-58dea691144f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101277504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_idle_intersig_mubi.4101277504
Directory	/workspace/41.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.2300575475
Short name	T30
Test name
Test status
Simulation time	19096749 ps
CPU time	0.81 seconds
Started	May 12 01:23:28 PM PDT 24
Finished	May 12 01:23:31 PM PDT 24
Peak memory	200464 kb
Host	smart-101d67a7-78f6-4b87-a53f-c4b269953e9b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300575475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 41.clkmgr_lc_clk_byp_req_intersig_mubi.2300575475
Directory	/workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.2660841851
Short name	T686
Test name
Test status
Simulation time	46633416 ps
CPU time	0.92 seconds
Started	May 12 01:23:27 PM PDT 24
Finished	May 12 01:23:29 PM PDT 24
Peak memory	200532 kb
Host	smart-821273ad-b1d3-4739-88ef-526c5e886659
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660841851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 41.clkmgr_lc_ctrl_intersig_mubi.2660841851
Directory	/workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/41.clkmgr_peri.2375232790
Short name	T397
Test name
Test status
Simulation time	15140989 ps
CPU time	0.72 seconds
Started	May 12 01:23:26 PM PDT 24
Finished	May 12 01:23:28 PM PDT 24
Peak memory	200312 kb
Host	smart-cc03f4d9-e333-449d-bb2e-31cfa2f52121
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375232790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.2375232790
Directory	/workspace/41.clkmgr_peri/latest

Test location	/workspace/coverage/default/41.clkmgr_regwen.1086878877
Short name	T85
Test name
Test status
Simulation time	1141759209 ps
CPU time	6.28 seconds
Started	May 12 01:23:29 PM PDT 24
Finished	May 12 01:23:37 PM PDT 24
Peak memory	200616 kb
Host	smart-e498f947-f664-4c1d-94a3-f8306c0b1432
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086878877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.1086878877
Directory	/workspace/41.clkmgr_regwen/latest

Test location	/workspace/coverage/default/41.clkmgr_smoke.3135735416
Short name	T853
Test name
Test status
Simulation time	21732504 ps
CPU time	0.85 seconds
Started	May 12 01:23:27 PM PDT 24
Finished	May 12 01:23:29 PM PDT 24
Peak memory	200440 kb
Host	smart-4fd4fda3-40a5-4b3d-a810-e2928f3bb06e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135735416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.3135735416
Directory	/workspace/41.clkmgr_smoke/latest

Test location	/workspace/coverage/default/41.clkmgr_stress_all.993639787
Short name	T11
Test name
Test status
Simulation time	7225467852 ps
CPU time	36.71 seconds
Started	May 12 01:23:26 PM PDT 24
Finished	May 12 01:24:04 PM PDT 24
Peak memory	200936 kb
Host	smart-c51d8c8c-d9c0-47fb-b9e9-a2e338b8e424
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993639787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all.993639787
Directory	/workspace/41.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.30967511
Short name	T16
Test name
Test status
Simulation time	44324868041 ps
CPU time	649.95 seconds
Started	May 12 01:23:26 PM PDT 24
Finished	May 12 01:34:17 PM PDT 24
Peak memory	217372 kb
Host	smart-e89f0f4c-4eb3-46e9-92c0-069e2bbf44ac
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=30967511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.30967511
Directory	/workspace/41.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.clkmgr_trans.3781050366
Short name	T237
Test name
Test status
Simulation time	66061625 ps
CPU time	0.93 seconds
Started	May 12 01:23:28 PM PDT 24
Finished	May 12 01:23:31 PM PDT 24
Peak memory	200472 kb
Host	smart-7f1af639-dc45-492b-a87a-9aa75fd7f9cd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781050366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.3781050366
Directory	/workspace/41.clkmgr_trans/latest

Test location	/workspace/coverage/default/42.clkmgr_alert_test.3720137666
Short name	T341
Test name
Test status
Simulation time	47766945 ps
CPU time	0.83 seconds
Started	May 12 01:23:28 PM PDT 24
Finished	May 12 01:23:31 PM PDT 24
Peak memory	200572 kb
Host	smart-772e8cb0-719e-403c-a55c-eb34727d1e16
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720137666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk mgr_alert_test.3720137666
Directory	/workspace/42.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.2660859614
Short name	T657
Test name
Test status
Simulation time	65896721 ps
CPU time	0.94 seconds
Started	May 12 01:23:28 PM PDT 24
Finished	May 12 01:23:30 PM PDT 24
Peak memory	200504 kb
Host	smart-b57591ab-263a-44bd-a4b2-b8e13bac9b47
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660859614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_handshake_intersig_mubi.2660859614
Directory	/workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_clk_status.125929981
Short name	T477
Test name
Test status
Simulation time	17595413 ps
CPU time	0.76 seconds
Started	May 12 01:23:27 PM PDT 24
Finished	May 12 01:23:29 PM PDT 24
Peak memory	199472 kb
Host	smart-494ece40-bbe5-4c8c-b5b0-e788da33f3eb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125929981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.125929981
Directory	/workspace/42.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/42.clkmgr_div_intersig_mubi.3614016284
Short name	T520
Test name
Test status
Simulation time	271811466 ps
CPU time	1.56 seconds
Started	May 12 01:23:27 PM PDT 24
Finished	May 12 01:23:29 PM PDT 24
Peak memory	200520 kb
Host	smart-e1dc4abc-d2ec-4a22-97e5-c30147071824
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614016284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_div_intersig_mubi.3614016284
Directory	/workspace/42.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_extclk.1432618550
Short name	T838
Test name
Test status
Simulation time	32269447 ps
CPU time	0.9 seconds
Started	May 12 01:23:30 PM PDT 24
Finished	May 12 01:23:32 PM PDT 24
Peak memory	200520 kb
Host	smart-6b4f9c1a-c385-4f81-ac4d-865300c068e1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432618550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.1432618550
Directory	/workspace/42.clkmgr_extclk/latest

Test location	/workspace/coverage/default/42.clkmgr_frequency.629232797
Short name	T542
Test name
Test status
Simulation time	947336853 ps
CPU time	4.43 seconds
Started	May 12 01:23:28 PM PDT 24
Finished	May 12 01:23:33 PM PDT 24
Peak memory	200576 kb
Host	smart-7f1636cd-d55a-4788-8596-e1f4deec0c01
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629232797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.629232797
Directory	/workspace/42.clkmgr_frequency/latest

Test location	/workspace/coverage/default/42.clkmgr_frequency_timeout.703311918
Short name	T769
Test name
Test status
Simulation time	1439419275 ps
CPU time	5.27 seconds
Started	May 12 01:23:27 PM PDT 24
Finished	May 12 01:23:33 PM PDT 24
Peak memory	200600 kb
Host	smart-2c0c5326-f7f3-4b78-913b-778dbcf80273
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703311918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_ti meout.703311918
Directory	/workspace/42.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/42.clkmgr_idle_intersig_mubi.3946774533
Short name	T602
Test name
Test status
Simulation time	33008424 ps
CPU time	0.97 seconds
Started	May 12 01:23:27 PM PDT 24
Finished	May 12 01:23:29 PM PDT 24
Peak memory	200512 kb
Host	smart-3c78add0-511b-4b98-93c1-0a3efbeaeb3c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946774533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_idle_intersig_mubi.3946774533
Directory	/workspace/42.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.3101202864
Short name	T535
Test name
Test status
Simulation time	53945676 ps
CPU time	0.98 seconds
Started	May 12 01:23:28 PM PDT 24
Finished	May 12 01:23:31 PM PDT 24
Peak memory	200456 kb
Host	smart-be0d0d24-1540-4131-8475-d1b419006f52
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101202864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 42.clkmgr_lc_clk_byp_req_intersig_mubi.3101202864
Directory	/workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.2998963822
Short name	T697
Test name
Test status
Simulation time	16528995 ps
CPU time	0.77 seconds
Started	May 12 01:23:29 PM PDT 24
Finished	May 12 01:23:31 PM PDT 24
Peak memory	200504 kb
Host	smart-4ad7da93-e2e9-4878-a18e-51b4749163dd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998963822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 42.clkmgr_lc_ctrl_intersig_mubi.2998963822
Directory	/workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/42.clkmgr_peri.2798471768
Short name	T269
Test name
Test status
Simulation time	21158996 ps
CPU time	0.73 seconds
Started	May 12 01:23:25 PM PDT 24
Finished	May 12 01:23:26 PM PDT 24
Peak memory	200292 kb
Host	smart-99f9bca3-497f-4795-a064-b4cc541aef6a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798471768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.2798471768
Directory	/workspace/42.clkmgr_peri/latest

Test location	/workspace/coverage/default/42.clkmgr_regwen.1895128528
Short name	T168
Test name
Test status
Simulation time	651043063 ps
CPU time	2.96 seconds
Started	May 12 01:23:26 PM PDT 24
Finished	May 12 01:23:29 PM PDT 24
Peak memory	200876 kb
Host	smart-77bd9fbb-9eb3-4268-94f3-cb45c722703e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895128528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.1895128528
Directory	/workspace/42.clkmgr_regwen/latest

Test location	/workspace/coverage/default/42.clkmgr_smoke.2073318955
Short name	T721
Test name
Test status
Simulation time	17194983 ps
CPU time	0.81 seconds
Started	May 12 01:23:26 PM PDT 24
Finished	May 12 01:23:27 PM PDT 24
Peak memory	200492 kb
Host	smart-dac0a6f3-bb2f-4c16-8deb-a60c95a8a6af
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073318955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.2073318955
Directory	/workspace/42.clkmgr_smoke/latest

Test location	/workspace/coverage/default/42.clkmgr_stress_all.3712907673
Short name	T669
Test name
Test status
Simulation time	7993183673 ps
CPU time	29.8 seconds
Started	May 12 01:23:31 PM PDT 24
Finished	May 12 01:24:01 PM PDT 24
Peak memory	200884 kb
Host	smart-9f54ad57-a744-40e6-88ad-c8943b05da28
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712907673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all.3712907673
Directory	/workspace/42.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.145687159
Short name	T173
Test name
Test status
Simulation time	218644637442 ps
CPU time	1231.88 seconds
Started	May 12 01:23:28 PM PDT 24
Finished	May 12 01:44:01 PM PDT 24
Peak memory	213800 kb
Host	smart-1633e357-fe02-405d-a6cb-a9f2eb1439c7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=145687159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.145687159
Directory	/workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.clkmgr_trans.3060351976
Short name	T56
Test name
Test status
Simulation time	44579666 ps
CPU time	0.84 seconds
Started	May 12 01:23:28 PM PDT 24
Finished	May 12 01:23:31 PM PDT 24
Peak memory	200372 kb
Host	smart-972f1aa4-9759-49fe-b6d7-f149268f91ea
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060351976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.3060351976
Directory	/workspace/42.clkmgr_trans/latest

Test location	/workspace/coverage/default/43.clkmgr_alert_test.3222092078
Short name	T495
Test name
Test status
Simulation time	16852828 ps
CPU time	0.75 seconds
Started	May 12 01:23:31 PM PDT 24
Finished	May 12 01:23:33 PM PDT 24
Peak memory	200544 kb
Host	smart-f38a8126-8759-430d-807b-e752b9081fa0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222092078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk mgr_alert_test.3222092078
Directory	/workspace/43.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.369475227
Short name	T823
Test name
Test status
Simulation time	98664050 ps
CPU time	1.15 seconds
Started	May 12 01:23:28 PM PDT 24
Finished	May 12 01:23:31 PM PDT 24
Peak memory	200496 kb
Host	smart-baeb3321-c4a1-4375-b0f4-8ebf9616f2ea
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369475227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_handshake_intersig_mubi.369475227
Directory	/workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_clk_status.277498458
Short name	T285
Test name
Test status
Simulation time	24163706 ps
CPU time	0.73 seconds
Started	May 12 01:23:29 PM PDT 24
Finished	May 12 01:23:31 PM PDT 24
Peak memory	199492 kb
Host	smart-80513f4e-5104-44a0-bac8-8c9600f4f7e8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277498458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.277498458
Directory	/workspace/43.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/43.clkmgr_div_intersig_mubi.173678804
Short name	T804
Test name
Test status
Simulation time	105603644 ps
CPU time	1.17 seconds
Started	May 12 01:23:30 PM PDT 24
Finished	May 12 01:23:32 PM PDT 24
Peak memory	200508 kb
Host	smart-2e10fbc3-3fa7-4fa1-9133-3db1493a0020
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173678804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test + UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.clkmgr_div_intersig_mubi.173678804
Directory	/workspace/43.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_extclk.1845725557
Short name	T224
Test name
Test status
Simulation time	32158405 ps
CPU time	0.87 seconds
Started	May 12 01:23:31 PM PDT 24
Finished	May 12 01:23:33 PM PDT 24
Peak memory	200528 kb
Host	smart-a599c4ec-b520-49e5-a0c1-9d4bc3c00b25
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845725557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.1845725557
Directory	/workspace/43.clkmgr_extclk/latest

Test location	/workspace/coverage/default/43.clkmgr_frequency.2579659588
Short name	T846
Test name
Test status
Simulation time	437022740 ps
CPU time	3.88 seconds
Started	May 12 01:23:29 PM PDT 24
Finished	May 12 01:23:34 PM PDT 24
Peak memory	200492 kb
Host	smart-36978480-d3c3-4d06-85cc-1eb3369ca6ac
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579659588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.2579659588
Directory	/workspace/43.clkmgr_frequency/latest

Test location	/workspace/coverage/default/43.clkmgr_frequency_timeout.1916818331
Short name	T739
Test name
Test status
Simulation time	1459941125 ps
CPU time	7.45 seconds
Started	May 12 01:23:29 PM PDT 24
Finished	May 12 01:23:38 PM PDT 24
Peak memory	200588 kb
Host	smart-48ec4a8e-9d2a-4905-9b8d-0a59a59e7bb2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916818331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t imeout.1916818331
Directory	/workspace/43.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/43.clkmgr_idle_intersig_mubi.2995845361
Short name	T562
Test name
Test status
Simulation time	56517356 ps
CPU time	1.04 seconds
Started	May 12 01:23:31 PM PDT 24
Finished	May 12 01:23:32 PM PDT 24
Peak memory	200392 kb
Host	smart-42c41f64-1a95-42b7-b2c2-6a8d123dd994
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995845361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_idle_intersig_mubi.2995845361
Directory	/workspace/43.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.3305487774
Short name	T522
Test name
Test status
Simulation time	58250988 ps
CPU time	0.93 seconds
Started	May 12 01:23:29 PM PDT 24
Finished	May 12 01:23:31 PM PDT 24
Peak memory	200516 kb
Host	smart-34782862-744a-4e05-a22e-039918018c5c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305487774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 43.clkmgr_lc_clk_byp_req_intersig_mubi.3305487774
Directory	/workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.996713713
Short name	T485
Test name
Test status
Simulation time	16575949 ps
CPU time	0.78 seconds
Started	May 12 01:23:29 PM PDT 24
Finished	May 12 01:23:31 PM PDT 24
Peak memory	200420 kb
Host	smart-6a26f300-16b1-4009-becb-3ab9303f92b1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996713713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 43.clkmgr_lc_ctrl_intersig_mubi.996713713
Directory	/workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/43.clkmgr_peri.2520729443
Short name	T340
Test name
Test status
Simulation time	28329226 ps
CPU time	0.75 seconds
Started	May 12 01:23:31 PM PDT 24
Finished	May 12 01:23:33 PM PDT 24
Peak memory	200308 kb
Host	smart-554eee4c-9a45-46d1-8712-f36e676822d4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520729443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.2520729443
Directory	/workspace/43.clkmgr_peri/latest

Test location	/workspace/coverage/default/43.clkmgr_regwen.1295768751
Short name	T427
Test name
Test status
Simulation time	333243983 ps
CPU time	1.73 seconds
Started	May 12 01:23:32 PM PDT 24
Finished	May 12 01:23:34 PM PDT 24
Peak memory	200488 kb
Host	smart-52f2d3f2-d094-41c5-91bb-491fbe7d68a9
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295768751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.1295768751
Directory	/workspace/43.clkmgr_regwen/latest

Test location	/workspace/coverage/default/43.clkmgr_smoke.3084991193
Short name	T460
Test name
Test status
Simulation time	53386257 ps
CPU time	0.88 seconds
Started	May 12 01:23:27 PM PDT 24
Finished	May 12 01:23:28 PM PDT 24
Peak memory	200396 kb
Host	smart-523f4a83-adc6-4400-a0b0-ce63e4f1cbc3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084991193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.3084991193
Directory	/workspace/43.clkmgr_smoke/latest

Test location	/workspace/coverage/default/43.clkmgr_stress_all.1688626389
Short name	T854
Test name
Test status
Simulation time	3291060490 ps
CPU time	17.65 seconds
Started	May 12 01:23:28 PM PDT 24
Finished	May 12 01:23:47 PM PDT 24
Peak memory	200868 kb
Host	smart-3a916e61-3496-4339-844b-df30341d4cfb
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688626389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all.1688626389
Directory	/workspace/43.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/43.clkmgr_stress_all_with_rand_reset.1373399552
Short name	T160
Test name
Test status
Simulation time	73657052475 ps
CPU time	400.11 seconds
Started	May 12 01:23:28 PM PDT 24
Finished	May 12 01:30:10 PM PDT 24
Peak memory	209160 kb
Host	smart-10edb1e4-c5ff-4414-bb49-7134c2f5af72
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1373399552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.1373399552
Directory	/workspace/43.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.clkmgr_trans.3600885303
Short name	T469
Test name
Test status
Simulation time	92455071 ps
CPU time	1.11 seconds
Started	May 12 01:23:29 PM PDT 24
Finished	May 12 01:23:31 PM PDT 24
Peak memory	200488 kb
Host	smart-23e78b81-5730-495f-bfee-4bf783d0fc4c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600885303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.3600885303
Directory	/workspace/43.clkmgr_trans/latest

Test location	/workspace/coverage/default/44.clkmgr_alert_test.61978434
Short name	T436
Test name
Test status
Simulation time	18759539 ps
CPU time	0.68 seconds
Started	May 12 01:23:33 PM PDT 24
Finished	May 12 01:23:34 PM PDT 24
Peak memory	199900 kb
Host	smart-3a1fcc89-2afe-4bfa-b3f7-913bd684523e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61978434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmg r_alert_test.61978434
Directory	/workspace/44.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.240710247
Short name	T446
Test name
Test status
Simulation time	124952065 ps
CPU time	1.16 seconds
Started	May 12 01:23:40 PM PDT 24
Finished	May 12 01:23:42 PM PDT 24
Peak memory	200432 kb
Host	smart-f4f366e0-95f0-47ff-a459-5038b7fa42f3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240710247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_handshake_intersig_mubi.240710247
Directory	/workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_clk_status.3907245043
Short name	T502
Test name
Test status
Simulation time	37761900 ps
CPU time	0.74 seconds
Started	May 12 01:23:36 PM PDT 24
Finished	May 12 01:23:38 PM PDT 24
Peak memory	200204 kb
Host	smart-54821dee-a14f-4e9a-af43-59ddd803e263
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907245043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.3907245043
Directory	/workspace/44.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/44.clkmgr_div_intersig_mubi.3481763651
Short name	T455
Test name
Test status
Simulation time	52014687 ps
CPU time	0.96 seconds
Started	May 12 01:23:34 PM PDT 24
Finished	May 12 01:23:36 PM PDT 24
Peak memory	200508 kb
Host	smart-7dfdaca3-bb1b-4aef-ae39-4e63dcb868b3
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481763651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_div_intersig_mubi.3481763651
Directory	/workspace/44.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_extclk.811109809
Short name	T247
Test name
Test status
Simulation time	26101110 ps
CPU time	0.9 seconds
Started	May 12 01:23:29 PM PDT 24
Finished	May 12 01:23:31 PM PDT 24
Peak memory	200480 kb
Host	smart-eaf5f467-7bbb-4c0f-8584-f68e693e5abd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811109809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.811109809
Directory	/workspace/44.clkmgr_extclk/latest

Test location	/workspace/coverage/default/44.clkmgr_frequency.1277218226
Short name	T834
Test name
Test status
Simulation time	1074745713 ps
CPU time	4.97 seconds
Started	May 12 01:23:31 PM PDT 24
Finished	May 12 01:23:37 PM PDT 24
Peak memory	200564 kb
Host	smart-1fed0c84-c758-4acd-b5c4-c5e85fab5ce1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277218226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.1277218226
Directory	/workspace/44.clkmgr_frequency/latest

Test location	/workspace/coverage/default/44.clkmgr_frequency_timeout.1180847285
Short name	T423
Test name
Test status
Simulation time	1100207404 ps
CPU time	7.88 seconds
Started	May 12 01:23:29 PM PDT 24
Finished	May 12 01:23:38 PM PDT 24
Peak memory	200596 kb
Host	smart-25b1ee42-a730-4853-bd79-582537ecd3f6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180847285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t imeout.1180847285
Directory	/workspace/44.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/44.clkmgr_idle_intersig_mubi.3921210252
Short name	T504
Test name
Test status
Simulation time	78982050 ps
CPU time	0.95 seconds
Started	May 12 01:23:41 PM PDT 24
Finished	May 12 01:23:42 PM PDT 24
Peak memory	200420 kb
Host	smart-c22fd1df-33a1-447a-8961-0f87d753ef5d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921210252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_idle_intersig_mubi.3921210252
Directory	/workspace/44.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.138235253
Short name	T52
Test name
Test status
Simulation time	34068086 ps
CPU time	0.77 seconds
Started	May 12 01:23:35 PM PDT 24
Finished	May 12 01:23:36 PM PDT 24
Peak memory	200444 kb
Host	smart-483f1b60-0099-4361-9734-5cc10278fd7a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138235253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 44.clkmgr_lc_clk_byp_req_intersig_mubi.138235253
Directory	/workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.3406271702
Short name	T379
Test name
Test status
Simulation time	56032262 ps
CPU time	0.89 seconds
Started	May 12 01:23:40 PM PDT 24
Finished	May 12 01:23:42 PM PDT 24
Peak memory	200448 kb
Host	smart-48ce4b7b-baaf-45c1-97c3-3da6b458cb20
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406271702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 44.clkmgr_lc_ctrl_intersig_mubi.3406271702
Directory	/workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/44.clkmgr_peri.1948839726
Short name	T790
Test name
Test status
Simulation time	41272167 ps
CPU time	0.79 seconds
Started	May 12 01:23:34 PM PDT 24
Finished	May 12 01:23:35 PM PDT 24
Peak memory	200324 kb
Host	smart-3ad6f8bb-f4bf-4c86-bb21-4996facc9a8f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948839726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.1948839726
Directory	/workspace/44.clkmgr_peri/latest

Test location	/workspace/coverage/default/44.clkmgr_regwen.516653119
Short name	T166
Test name
Test status
Simulation time	498440315 ps
CPU time	3.29 seconds
Started	May 12 01:23:35 PM PDT 24
Finished	May 12 01:23:39 PM PDT 24
Peak memory	200480 kb
Host	smart-9ddb895a-7dc6-4a36-a62a-fe7edd787d48
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516653119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.516653119
Directory	/workspace/44.clkmgr_regwen/latest

Test location	/workspace/coverage/default/44.clkmgr_smoke.3083840412
Short name	T639
Test name
Test status
Simulation time	146327140 ps
CPU time	1.19 seconds
Started	May 12 01:23:28 PM PDT 24
Finished	May 12 01:23:30 PM PDT 24
Peak memory	200520 kb
Host	smart-42bb8f47-2519-4628-9785-f2572e0898f1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083840412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.3083840412
Directory	/workspace/44.clkmgr_smoke/latest

Test location	/workspace/coverage/default/44.clkmgr_stress_all.4075442717
Short name	T616
Test name
Test status
Simulation time	4842294840 ps
CPU time	19.69 seconds
Started	May 12 01:23:35 PM PDT 24
Finished	May 12 01:23:55 PM PDT 24
Peak memory	200948 kb
Host	smart-9a041f63-a28b-4e6d-8fd2-9b9ab8274188
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075442717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all.4075442717
Directory	/workspace/44.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.2818624864
Short name	T79
Test name
Test status
Simulation time	552908405460 ps
CPU time	1852.57 seconds
Started	May 12 01:23:32 PM PDT 24
Finished	May 12 01:54:26 PM PDT 24
Peak memory	217328 kb
Host	smart-cba83e17-3803-4d33-8df2-26f6a2ae4562
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2818624864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.2818624864
Directory	/workspace/44.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.clkmgr_trans.1895223870
Short name	T749
Test name
Test status
Simulation time	57815854 ps
CPU time	0.83 seconds
Started	May 12 01:23:35 PM PDT 24
Finished	May 12 01:23:37 PM PDT 24
Peak memory	200472 kb
Host	smart-d466cc3a-f28f-49c1-abaf-0db59895aa95
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895223870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.1895223870
Directory	/workspace/44.clkmgr_trans/latest

Test location	/workspace/coverage/default/45.clkmgr_alert_test.907064593
Short name	T398
Test name
Test status
Simulation time	12937296 ps
CPU time	0.77 seconds
Started	May 12 01:23:37 PM PDT 24
Finished	May 12 01:23:39 PM PDT 24
Peak memory	200576 kb
Host	smart-49f712fe-a110-4545-a9a9-48bca8665add
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907064593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkm gr_alert_test.907064593
Directory	/workspace/45.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.474977135
Short name	T242
Test name
Test status
Simulation time	48784594 ps
CPU time	0.84 seconds
Started	May 12 01:23:34 PM PDT 24
Finished	May 12 01:23:35 PM PDT 24
Peak memory	200484 kb
Host	smart-b8bdd4ec-8744-4196-a7ee-e611cfbc1fb4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474977135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_handshake_intersig_mubi.474977135
Directory	/workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_clk_status.2665848462
Short name	T279
Test name
Test status
Simulation time	31810648 ps
CPU time	0.76 seconds
Started	May 12 01:23:34 PM PDT 24
Finished	May 12 01:23:35 PM PDT 24
Peak memory	200236 kb
Host	smart-5faa8885-5a8b-46ba-a861-c6c158083620
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665848462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.2665848462
Directory	/workspace/45.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/45.clkmgr_div_intersig_mubi.4168134521
Short name	T395
Test name
Test status
Simulation time	23595113 ps
CPU time	0.76 seconds
Started	May 12 01:23:35 PM PDT 24
Finished	May 12 01:23:37 PM PDT 24
Peak memory	200508 kb
Host	smart-d2b126a9-7735-43b5-9ce7-874a88eb4bf2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168134521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_div_intersig_mubi.4168134521
Directory	/workspace/45.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_extclk.539601105
Short name	T528
Test name
Test status
Simulation time	22443336 ps
CPU time	0.78 seconds
Started	May 12 01:23:35 PM PDT 24
Finished	May 12 01:23:36 PM PDT 24
Peak memory	200480 kb
Host	smart-811d00bb-bcc1-4ffd-b86b-491848ba3127
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539601105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.539601105
Directory	/workspace/45.clkmgr_extclk/latest

Test location	/workspace/coverage/default/45.clkmgr_frequency.1529220644
Short name	T343
Test name
Test status
Simulation time	1470515181 ps
CPU time	6.69 seconds
Started	May 12 01:23:35 PM PDT 24
Finished	May 12 01:23:43 PM PDT 24
Peak memory	200596 kb
Host	smart-821f9445-90bc-4bb7-a12f-a4c709f32e94
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529220644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.1529220644
Directory	/workspace/45.clkmgr_frequency/latest

Test location	/workspace/coverage/default/45.clkmgr_frequency_timeout.777255253
Short name	T428
Test name
Test status
Simulation time	2053814584 ps
CPU time	15.04 seconds
Started	May 12 01:23:35 PM PDT 24
Finished	May 12 01:23:51 PM PDT 24
Peak memory	200748 kb
Host	smart-983cdfe1-3e14-4643-8ed8-4940882fd676
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777255253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_ti meout.777255253
Directory	/workspace/45.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/45.clkmgr_idle_intersig_mubi.2377806739
Short name	T741
Test name
Test status
Simulation time	40698320 ps
CPU time	0.78 seconds
Started	May 12 01:23:35 PM PDT 24
Finished	May 12 01:23:36 PM PDT 24
Peak memory	200472 kb
Host	smart-e76d6301-052a-4209-b126-26d773594e26
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377806739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_idle_intersig_mubi.2377806739
Directory	/workspace/45.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.1444930260
Short name	T89
Test name
Test status
Simulation time	34451594 ps
CPU time	0.88 seconds
Started	May 12 01:23:35 PM PDT 24
Finished	May 12 01:23:37 PM PDT 24
Peak memory	200520 kb
Host	smart-77f6102d-996f-4b64-af73-acf57de4932a
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444930260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 45.clkmgr_lc_clk_byp_req_intersig_mubi.1444930260
Directory	/workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.362016138
Short name	T513
Test name
Test status
Simulation time	15135685 ps
CPU time	0.76 seconds
Started	May 12 01:23:41 PM PDT 24
Finished	May 12 01:23:42 PM PDT 24
Peak memory	200448 kb
Host	smart-2d50454e-3a10-46c6-9d0a-3d78182d1d7e
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362016138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.clkmgr_lc_ctrl_intersig_mubi.362016138
Directory	/workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/45.clkmgr_peri.522847414
Short name	T229
Test name
Test status
Simulation time	43738891 ps
CPU time	0.8 seconds
Started	May 12 01:23:33 PM PDT 24
Finished	May 12 01:23:34 PM PDT 24
Peak memory	200284 kb
Host	smart-7f9516f6-1729-4f49-a23e-396f6e779e04
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522847414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.522847414
Directory	/workspace/45.clkmgr_peri/latest

Test location	/workspace/coverage/default/45.clkmgr_regwen.1111664315
Short name	T621
Test name
Test status
Simulation time	720192974 ps
CPU time	4.32 seconds
Started	May 12 01:23:41 PM PDT 24
Finished	May 12 01:23:46 PM PDT 24
Peak memory	200596 kb
Host	smart-895b229b-ddcc-48fe-88e2-420d7e8b06af
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111664315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.1111664315
Directory	/workspace/45.clkmgr_regwen/latest

Test location	/workspace/coverage/default/45.clkmgr_smoke.1938892139
Short name	T153
Test name
Test status
Simulation time	24150335 ps
CPU time	0.89 seconds
Started	May 12 01:23:32 PM PDT 24
Finished	May 12 01:23:34 PM PDT 24
Peak memory	200516 kb
Host	smart-f72c114d-fd39-45d5-a2ef-0874d39b130c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938892139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.1938892139
Directory	/workspace/45.clkmgr_smoke/latest

Test location	/workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.3191452114
Short name	T38
Test name
Test status
Simulation time	31291800784 ps
CPU time	286.6 seconds
Started	May 12 01:23:38 PM PDT 24
Finished	May 12 01:28:25 PM PDT 24
Peak memory	209096 kb
Host	smart-6b0174e2-2b62-422f-b139-1acb78e5960d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3191452114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.3191452114
Directory	/workspace/45.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.clkmgr_trans.2817469907
Short name	T420
Test name
Test status
Simulation time	23867799 ps
CPU time	0.95 seconds
Started	May 12 01:23:36 PM PDT 24
Finished	May 12 01:23:37 PM PDT 24
Peak memory	200468 kb
Host	smart-3bcad0c7-0d7a-40d4-bd34-5b6b2478abda
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817469907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.2817469907
Directory	/workspace/45.clkmgr_trans/latest

Test location	/workspace/coverage/default/46.clkmgr_alert_test.1023426422
Short name	T288
Test name
Test status
Simulation time	14882158 ps
CPU time	0.74 seconds
Started	May 12 01:23:37 PM PDT 24
Finished	May 12 01:23:38 PM PDT 24
Peak memory	200584 kb
Host	smart-c97ec37f-5d82-45c7-9f20-ae1b89e8b8bc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023426422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk mgr_alert_test.1023426422
Directory	/workspace/46.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.1006647628
Short name	T625
Test name
Test status
Simulation time	124354905 ps
CPU time	1.06 seconds
Started	May 12 01:23:36 PM PDT 24
Finished	May 12 01:23:37 PM PDT 24
Peak memory	200480 kb
Host	smart-20758b66-74fd-4aa9-b958-dad999ca8bd6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006647628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_handshake_intersig_mubi.1006647628
Directory	/workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_clk_status.3818102920
Short name	T633
Test name
Test status
Simulation time	41401672 ps
CPU time	0.78 seconds
Started	May 12 01:23:37 PM PDT 24
Finished	May 12 01:23:39 PM PDT 24
Peak memory	199520 kb
Host	smart-0a6e428b-b0da-4c49-bb99-146aab252073
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818102920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.3818102920
Directory	/workspace/46.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/46.clkmgr_div_intersig_mubi.2720632448
Short name	T538
Test name
Test status
Simulation time	41536616 ps
CPU time	0.9 seconds
Started	May 12 01:23:36 PM PDT 24
Finished	May 12 01:23:38 PM PDT 24
Peak memory	200512 kb
Host	smart-6afc8c68-479b-465d-b9a8-742fb63bc703
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720632448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_div_intersig_mubi.2720632448
Directory	/workspace/46.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_extclk.2196153498
Short name	T199
Test name
Test status
Simulation time	53394589 ps
CPU time	0.84 seconds
Started	May 12 01:23:36 PM PDT 24
Finished	May 12 01:23:38 PM PDT 24
Peak memory	200460 kb
Host	smart-400b062c-89c7-45f5-bf91-49a159e6728e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196153498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.2196153498
Directory	/workspace/46.clkmgr_extclk/latest

Test location	/workspace/coverage/default/46.clkmgr_frequency.2184027484
Short name	T630
Test name
Test status
Simulation time	1649432614 ps
CPU time	8.73 seconds
Started	May 12 01:23:37 PM PDT 24
Finished	May 12 01:23:47 PM PDT 24
Peak memory	200532 kb
Host	smart-abc673dc-c01f-4a3d-9206-5b1cbf82e092
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184027484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.2184027484
Directory	/workspace/46.clkmgr_frequency/latest

Test location	/workspace/coverage/default/46.clkmgr_frequency_timeout.1663999931
Short name	T268
Test name
Test status
Simulation time	1475000156 ps
CPU time	6.25 seconds
Started	May 12 01:23:38 PM PDT 24
Finished	May 12 01:23:44 PM PDT 24
Peak memory	200616 kb
Host	smart-57dbd0ec-fa57-4633-92c7-2fbd3a5fa980
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663999931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t imeout.1663999931
Directory	/workspace/46.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/46.clkmgr_idle_intersig_mubi.1100237746
Short name	T751
Test name
Test status
Simulation time	101232914 ps
CPU time	1.1 seconds
Started	May 12 01:23:36 PM PDT 24
Finished	May 12 01:23:38 PM PDT 24
Peak memory	200472 kb
Host	smart-cf99ab4a-b1c0-4e85-a5f6-c8c8b01a0f60
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100237746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_idle_intersig_mubi.1100237746
Directory	/workspace/46.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.3344271941
Short name	T738
Test name
Test status
Simulation time	200820921 ps
CPU time	1.3 seconds
Started	May 12 01:23:40 PM PDT 24
Finished	May 12 01:23:42 PM PDT 24
Peak memory	200524 kb
Host	smart-a43390fa-29ef-4808-aa8c-dc4ff23a4e15
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344271941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 46.clkmgr_lc_clk_byp_req_intersig_mubi.3344271941
Directory	/workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.841311551
Short name	T32
Test name
Test status
Simulation time	15624231 ps
CPU time	0.78 seconds
Started	May 12 01:23:39 PM PDT 24
Finished	May 12 01:23:40 PM PDT 24
Peak memory	200476 kb
Host	smart-4841bc59-05a2-4a04-8b57-e9c12bb4c5cd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841311551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.clkmgr_lc_ctrl_intersig_mubi.841311551
Directory	/workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/46.clkmgr_peri.1104753916
Short name	T514
Test name
Test status
Simulation time	43706097 ps
CPU time	0.83 seconds
Started	May 12 01:23:37 PM PDT 24
Finished	May 12 01:23:38 PM PDT 24
Peak memory	200316 kb
Host	smart-243c053e-f2d1-4ae8-9cf2-18b07b47a6e5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104753916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.1104753916
Directory	/workspace/46.clkmgr_peri/latest

Test location	/workspace/coverage/default/46.clkmgr_regwen.1086217289
Short name	T294
Test name
Test status
Simulation time	642038234 ps
CPU time	3.77 seconds
Started	May 12 01:23:38 PM PDT 24
Finished	May 12 01:23:42 PM PDT 24
Peak memory	200592 kb
Host	smart-029ed675-72f1-4aca-ae38-8181d6ae6de2
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086217289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.1086217289
Directory	/workspace/46.clkmgr_regwen/latest

Test location	/workspace/coverage/default/46.clkmgr_smoke.3661968653
Short name	T623
Test name
Test status
Simulation time	30048161 ps
CPU time	0.84 seconds
Started	May 12 01:23:37 PM PDT 24
Finished	May 12 01:23:38 PM PDT 24
Peak memory	200488 kb
Host	smart-7f6d221f-f6f3-4a0a-ac30-70f66d39019e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661968653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.3661968653
Directory	/workspace/46.clkmgr_smoke/latest

Test location	/workspace/coverage/default/46.clkmgr_stress_all.1559119868
Short name	T13
Test name
Test status
Simulation time	6964396998 ps
CPU time	26.69 seconds
Started	May 12 01:23:41 PM PDT 24
Finished	May 12 01:24:08 PM PDT 24
Peak memory	200904 kb
Host	smart-188a671c-145a-4d5b-b3e8-c53ea6e32380
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559119868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all.1559119868
Directory	/workspace/46.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.2163343411
Short name	T50
Test name
Test status
Simulation time	25671078228 ps
CPU time	426.77 seconds
Started	May 12 01:23:39 PM PDT 24
Finished	May 12 01:30:46 PM PDT 24
Peak memory	209184 kb
Host	smart-c7119634-3f91-4e85-a410-74b34e69f377
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2163343411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.2163343411
Directory	/workspace/46.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.clkmgr_trans.2773723813
Short name	T206
Test name
Test status
Simulation time	40653072 ps
CPU time	0.82 seconds
Started	May 12 01:23:38 PM PDT 24
Finished	May 12 01:23:40 PM PDT 24
Peak memory	200440 kb
Host	smart-e6e7ddb8-3904-410d-89cb-742c92e17f8b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773723813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.2773723813
Directory	/workspace/46.clkmgr_trans/latest

Test location	/workspace/coverage/default/47.clkmgr_alert_test.1833770080
Short name	T544
Test name
Test status
Simulation time	32677766 ps
CPU time	0.79 seconds
Started	May 12 01:23:41 PM PDT 24
Finished	May 12 01:23:42 PM PDT 24
Peak memory	200472 kb
Host	smart-2d723799-17e4-4e7f-95d5-05e882ccf025
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833770080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk mgr_alert_test.1833770080
Directory	/workspace/47.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.2187868629
Short name	T601
Test name
Test status
Simulation time	54777573 ps
CPU time	1.01 seconds
Started	May 12 01:23:41 PM PDT 24
Finished	May 12 01:23:42 PM PDT 24
Peak memory	200512 kb
Host	smart-8183833f-64f8-4765-a2af-040b42e2101b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187868629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_handshake_intersig_mubi.2187868629
Directory	/workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_clk_status.228418190
Short name	T28
Test name
Test status
Simulation time	47872750 ps
CPU time	0.79 seconds
Started	May 12 01:23:44 PM PDT 24
Finished	May 12 01:23:45 PM PDT 24
Peak memory	199520 kb
Host	smart-0290aa00-dd90-44ca-83a4-a8d749f1fd14
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228418190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.228418190
Directory	/workspace/47.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/47.clkmgr_div_intersig_mubi.2592932798
Short name	T763
Test name
Test status
Simulation time	75994429 ps
CPU time	1.03 seconds
Started	May 12 01:23:42 PM PDT 24
Finished	May 12 01:23:44 PM PDT 24
Peak memory	200452 kb
Host	smart-becaf589-8f59-477a-982d-a1a5a092ed0d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592932798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_div_intersig_mubi.2592932798
Directory	/workspace/47.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_extclk.3576106893
Short name	T445
Test name
Test status
Simulation time	14800894 ps
CPU time	0.74 seconds
Started	May 12 01:23:37 PM PDT 24
Finished	May 12 01:23:38 PM PDT 24
Peak memory	200524 kb
Host	smart-26aa7689-ad23-4a5b-b5ec-3ae24142fe72
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576106893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.3576106893
Directory	/workspace/47.clkmgr_extclk/latest

Test location	/workspace/coverage/default/47.clkmgr_frequency.3895564628
Short name	T546
Test name
Test status
Simulation time	738046618 ps
CPU time	3.54 seconds
Started	May 12 01:23:41 PM PDT 24
Finished	May 12 01:23:45 PM PDT 24
Peak memory	200552 kb
Host	smart-6476ead2-b47e-44fc-be0c-7cb75553fca4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895564628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.3895564628
Directory	/workspace/47.clkmgr_frequency/latest

Test location	/workspace/coverage/default/47.clkmgr_frequency_timeout.2539306167
Short name	T396
Test name
Test status
Simulation time	991831985 ps
CPU time	4.3 seconds
Started	May 12 01:23:40 PM PDT 24
Finished	May 12 01:23:45 PM PDT 24
Peak memory	200628 kb
Host	smart-c4ecb28c-640a-4497-93ad-c6e5569c23be
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539306167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t imeout.2539306167
Directory	/workspace/47.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/47.clkmgr_idle_intersig_mubi.3993800992
Short name	T808
Test name
Test status
Simulation time	44678802 ps
CPU time	0.95 seconds
Started	May 12 01:23:41 PM PDT 24
Finished	May 12 01:23:43 PM PDT 24
Peak memory	200476 kb
Host	smart-81946028-9d68-4fba-b9a5-c4e97472bb3b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993800992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_idle_intersig_mubi.3993800992
Directory	/workspace/47.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.1749432572
Short name	T845
Test name
Test status
Simulation time	20554223 ps
CPU time	0.82 seconds
Started	May 12 01:23:41 PM PDT 24
Finished	May 12 01:23:43 PM PDT 24
Peak memory	200512 kb
Host	smart-e90ae9bb-317f-4e0a-acd1-25ab791d13fb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749432572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 47.clkmgr_lc_clk_byp_req_intersig_mubi.1749432572
Directory	/workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.3355509769
Short name	T179
Test name
Test status
Simulation time	71002178 ps
CPU time	0.94 seconds
Started	May 12 01:23:45 PM PDT 24
Finished	May 12 01:23:46 PM PDT 24
Peak memory	200476 kb
Host	smart-13557c96-8f98-4634-b469-0a0fde4cea59
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355509769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 47.clkmgr_lc_ctrl_intersig_mubi.3355509769
Directory	/workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/47.clkmgr_peri.2822578454
Short name	T293
Test name
Test status
Simulation time	14922854 ps
CPU time	0.72 seconds
Started	May 12 01:23:44 PM PDT 24
Finished	May 12 01:23:45 PM PDT 24
Peak memory	200264 kb
Host	smart-da5de5d0-04d3-4776-b54d-4956bb749528
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822578454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.2822578454
Directory	/workspace/47.clkmgr_peri/latest

Test location	/workspace/coverage/default/47.clkmgr_regwen.2249720223
Short name	T170
Test name
Test status
Simulation time	1027266408 ps
CPU time	6.43 seconds
Started	May 12 01:23:43 PM PDT 24
Finished	May 12 01:23:49 PM PDT 24
Peak memory	200676 kb
Host	smart-ca749d7b-584b-47cc-aaf9-f5d21f4d91e0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249720223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.2249720223
Directory	/workspace/47.clkmgr_regwen/latest

Test location	/workspace/coverage/default/47.clkmgr_smoke.2900288091
Short name	T578
Test name
Test status
Simulation time	79387965 ps
CPU time	1.07 seconds
Started	May 12 01:23:38 PM PDT 24
Finished	May 12 01:23:40 PM PDT 24
Peak memory	200484 kb
Host	smart-4651ce6c-82c0-4494-9758-573341e706a0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900288091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.2900288091
Directory	/workspace/47.clkmgr_smoke/latest

Test location	/workspace/coverage/default/47.clkmgr_stress_all.4155318974
Short name	T812
Test name
Test status
Simulation time	2788137691 ps
CPU time	20.86 seconds
Started	May 12 01:23:47 PM PDT 24
Finished	May 12 01:24:08 PM PDT 24
Peak memory	200936 kb
Host	smart-22cba6ea-c2f1-44db-825e-c582215da801
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155318974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all.4155318974
Directory	/workspace/47.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.1907485817
Short name	T771
Test name
Test status
Simulation time	114921381190 ps
CPU time	695.17 seconds
Started	May 12 01:23:45 PM PDT 24
Finished	May 12 01:35:20 PM PDT 24
Peak memory	217420 kb
Host	smart-96d025cd-c7b4-4f40-9b52-b7ac25c23199
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1907485817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.1907485817
Directory	/workspace/47.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/47.clkmgr_trans.361948007
Short name	T652
Test name
Test status
Simulation time	81121393 ps
CPU time	1.04 seconds
Started	May 12 01:23:44 PM PDT 24
Finished	May 12 01:23:45 PM PDT 24
Peak memory	200500 kb
Host	smart-889b7598-e316-4c59-81e4-5a47882a893f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361948007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.361948007
Directory	/workspace/47.clkmgr_trans/latest

Test location	/workspace/coverage/default/48.clkmgr_alert_test.3124176598
Short name	T443
Test name
Test status
Simulation time	29608488 ps
CPU time	0.74 seconds
Started	May 12 01:23:41 PM PDT 24
Finished	May 12 01:23:42 PM PDT 24
Peak memory	200496 kb
Host	smart-13c11ded-0b38-4954-bd5e-a0e0092c2c8a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124176598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk mgr_alert_test.3124176598
Directory	/workspace/48.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.807220896
Short name	T512
Test name
Test status
Simulation time	139151071 ps
CPU time	1.09 seconds
Started	May 12 01:23:42 PM PDT 24
Finished	May 12 01:23:44 PM PDT 24
Peak memory	200504 kb
Host	smart-90c489e7-507d-466c-81ec-f2a086546954
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807220896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_handshake_intersig_mubi.807220896
Directory	/workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_clk_status.1991847098
Short name	T338
Test name
Test status
Simulation time	75339982 ps
CPU time	0.85 seconds
Started	May 12 01:23:43 PM PDT 24
Finished	May 12 01:23:44 PM PDT 24
Peak memory	199516 kb
Host	smart-b4c81299-f572-4b5d-9f9d-48532a2a2f16
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991847098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.1991847098
Directory	/workspace/48.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/48.clkmgr_div_intersig_mubi.3101082916
Short name	T779
Test name
Test status
Simulation time	15398132 ps
CPU time	0.75 seconds
Started	May 12 01:23:45 PM PDT 24
Finished	May 12 01:23:46 PM PDT 24
Peak memory	200448 kb
Host	smart-d9266c9b-40fc-42fc-ad77-ebd344bcdfa9
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101082916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_div_intersig_mubi.3101082916
Directory	/workspace/48.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_extclk.201320964
Short name	T53
Test name
Test status
Simulation time	35120612 ps
CPU time	0.86 seconds
Started	May 12 01:23:48 PM PDT 24
Finished	May 12 01:23:49 PM PDT 24
Peak memory	200492 kb
Host	smart-785b6cd2-695c-49ca-a581-a15285f0b3cf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201320964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.201320964
Directory	/workspace/48.clkmgr_extclk/latest

Test location	/workspace/coverage/default/48.clkmgr_frequency.1164018060
Short name	T262
Test name
Test status
Simulation time	943268424 ps
CPU time	3.62 seconds
Started	May 12 01:23:42 PM PDT 24
Finished	May 12 01:23:46 PM PDT 24
Peak memory	200540 kb
Host	smart-7561ce4c-c192-44ad-98bb-59beddb6423b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164018060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.1164018060
Directory	/workspace/48.clkmgr_frequency/latest

Test location	/workspace/coverage/default/48.clkmgr_frequency_timeout.3867608322
Short name	T321
Test name
Test status
Simulation time	614410790 ps
CPU time	4.89 seconds
Started	May 12 01:23:40 PM PDT 24
Finished	May 12 01:23:46 PM PDT 24
Peak memory	200552 kb
Host	smart-f9f0409a-5917-49cb-a1f3-d7361af7f9f3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867608322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t imeout.3867608322
Directory	/workspace/48.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/48.clkmgr_idle_intersig_mubi.593647319
Short name	T29
Test name
Test status
Simulation time	18853957 ps
CPU time	0.76 seconds
Started	May 12 01:23:42 PM PDT 24
Finished	May 12 01:23:43 PM PDT 24
Peak memory	200436 kb
Host	smart-cc1965ee-64b5-4286-8325-24c887693eb7
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593647319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.clkmgr_idle_intersig_mubi.593647319
Directory	/workspace/48.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.3937571421
Short name	T766
Test name
Test status
Simulation time	28513868 ps
CPU time	0.94 seconds
Started	May 12 01:23:45 PM PDT 24
Finished	May 12 01:23:46 PM PDT 24
Peak memory	200464 kb
Host	smart-6dd2e681-e4ca-4cb2-afb8-235467f3a7d4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937571421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 48.clkmgr_lc_clk_byp_req_intersig_mubi.3937571421
Directory	/workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.1420348720
Short name	T484
Test name
Test status
Simulation time	33248111 ps
CPU time	0.77 seconds
Started	May 12 01:23:43 PM PDT 24
Finished	May 12 01:23:45 PM PDT 24
Peak memory	200508 kb
Host	smart-b57500e3-1000-4232-9915-a29514a38b4c
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420348720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 48.clkmgr_lc_ctrl_intersig_mubi.1420348720
Directory	/workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/48.clkmgr_peri.2376472696
Short name	T613
Test name
Test status
Simulation time	18804759 ps
CPU time	0.79 seconds
Started	May 12 01:23:41 PM PDT 24
Finished	May 12 01:23:42 PM PDT 24
Peak memory	200316 kb
Host	smart-f558e750-91c4-4798-8cd3-af5b441401bd
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376472696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.2376472696
Directory	/workspace/48.clkmgr_peri/latest

Test location	/workspace/coverage/default/48.clkmgr_regwen.2906229720
Short name	T424
Test name
Test status
Simulation time	1248640533 ps
CPU time	7.09 seconds
Started	May 12 01:23:48 PM PDT 24
Finished	May 12 01:23:55 PM PDT 24
Peak memory	200656 kb
Host	smart-1bbcfd1b-2088-4400-b742-776fda9e555b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906229720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.2906229720
Directory	/workspace/48.clkmgr_regwen/latest

Test location	/workspace/coverage/default/48.clkmgr_smoke.2017286449
Short name	T716
Test name
Test status
Simulation time	64420465 ps
CPU time	0.97 seconds
Started	May 12 01:23:41 PM PDT 24
Finished	May 12 01:23:43 PM PDT 24
Peak memory	200736 kb
Host	smart-eea65213-25f3-477a-a4ea-ee8872a93601
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017286449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.2017286449
Directory	/workspace/48.clkmgr_smoke/latest

Test location	/workspace/coverage/default/48.clkmgr_stress_all.2692225263
Short name	T363
Test name
Test status
Simulation time	7332675222 ps
CPU time	30.63 seconds
Started	May 12 01:23:44 PM PDT 24
Finished	May 12 01:24:15 PM PDT 24
Peak memory	200884 kb
Host	smart-13251a62-fe63-4dbb-a6e8-390e211ae47f
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692225263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all.2692225263
Directory	/workspace/48.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.2863536664
Short name	T307
Test name
Test status
Simulation time	12200526306 ps
CPU time	183.45 seconds
Started	May 12 01:23:42 PM PDT 24
Finished	May 12 01:26:46 PM PDT 24
Peak memory	209184 kb
Host	smart-5e1b85a2-a4a3-47ee-b524-99389e17e895
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2863536664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.2863536664
Directory	/workspace/48.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.clkmgr_trans.2236463401
Short name	T559
Test name
Test status
Simulation time	39730421 ps
CPU time	0.92 seconds
Started	May 12 01:23:41 PM PDT 24
Finished	May 12 01:23:43 PM PDT 24
Peak memory	200472 kb
Host	smart-5b1c30c6-3386-4364-8036-7915794149b7
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236463401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.2236463401
Directory	/workspace/48.clkmgr_trans/latest

Test location	/workspace/coverage/default/49.clkmgr_alert_test.1652504443
Short name	T310
Test name
Test status
Simulation time	55220354 ps
CPU time	0.92 seconds
Started	May 12 01:23:58 PM PDT 24
Finished	May 12 01:23:59 PM PDT 24
Peak memory	200592 kb
Host	smart-b4ed6253-de75-4008-b83a-77428237ceef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652504443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk mgr_alert_test.1652504443
Directory	/workspace/49.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.3749626223
Short name	T109
Test name
Test status
Simulation time	82243146 ps
CPU time	1.13 seconds
Started	May 12 01:23:47 PM PDT 24
Finished	May 12 01:23:49 PM PDT 24
Peak memory	200496 kb
Host	smart-82852544-37b8-46bd-8e27-c735a4ed3d11
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749626223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_handshake_intersig_mubi.3749626223
Directory	/workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_clk_status.2645531909
Short name	T57
Test name
Test status
Simulation time	18095725 ps
CPU time	0.75 seconds
Started	May 12 01:23:46 PM PDT 24
Finished	May 12 01:23:48 PM PDT 24
Peak memory	199524 kb
Host	smart-d2d7b86b-efd5-480f-8f51-9b7c3fcdd34f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645531909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.2645531909
Directory	/workspace/49.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/49.clkmgr_div_intersig_mubi.1570593529
Short name	T591
Test name
Test status
Simulation time	55444707 ps
CPU time	0.88 seconds
Started	May 12 01:23:51 PM PDT 24
Finished	May 12 01:23:53 PM PDT 24
Peak memory	200480 kb
Host	smart-bf44bcfc-6e08-47d4-b390-e28821ba680f
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570593529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_div_intersig_mubi.1570593529
Directory	/workspace/49.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_extclk.1662199030
Short name	T281
Test name
Test status
Simulation time	30399037 ps
CPU time	0.98 seconds
Started	May 12 01:23:44 PM PDT 24
Finished	May 12 01:23:45 PM PDT 24
Peak memory	200464 kb
Host	smart-af250a83-7eaa-4c2e-b6d9-678d7b8a8e95
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662199030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.1662199030
Directory	/workspace/49.clkmgr_extclk/latest

Test location	/workspace/coverage/default/49.clkmgr_frequency.4064253893
Short name	T283
Test name
Test status
Simulation time	324942844 ps
CPU time	2.33 seconds
Started	May 12 01:23:45 PM PDT 24
Finished	May 12 01:23:48 PM PDT 24
Peak memory	200556 kb
Host	smart-d1b19e8a-950e-4094-959c-c6c2413496ff
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064253893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.4064253893
Directory	/workspace/49.clkmgr_frequency/latest

Test location	/workspace/coverage/default/49.clkmgr_frequency_timeout.2847182260
Short name	T458
Test name
Test status
Simulation time	259403948 ps
CPU time	2.43 seconds
Started	May 12 01:23:46 PM PDT 24
Finished	May 12 01:23:49 PM PDT 24
Peak memory	200640 kb
Host	smart-05988f6c-8253-40a7-880c-ffe9d39b108a
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847182260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t imeout.2847182260
Directory	/workspace/49.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/49.clkmgr_idle_intersig_mubi.1628841306
Short name	T500
Test name
Test status
Simulation time	83222488 ps
CPU time	1.27 seconds
Started	May 12 01:23:45 PM PDT 24
Finished	May 12 01:23:47 PM PDT 24
Peak memory	200520 kb
Host	smart-a5f4cd9d-7503-46f3-b176-dd26dccf4281
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628841306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_idle_intersig_mubi.1628841306
Directory	/workspace/49.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.4178902302
Short name	T490
Test name
Test status
Simulation time	228989761 ps
CPU time	1.38 seconds
Started	May 12 01:23:46 PM PDT 24
Finished	May 12 01:23:47 PM PDT 24
Peak memory	200476 kb
Host	smart-7e5ba515-9cba-40fb-a48a-8146786335be
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178902302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 49.clkmgr_lc_clk_byp_req_intersig_mubi.4178902302
Directory	/workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.566885671
Short name	T651
Test name
Test status
Simulation time	28810693 ps
CPU time	0.85 seconds
Started	May 12 01:23:46 PM PDT 24
Finished	May 12 01:23:47 PM PDT 24
Peak memory	200484 kb
Host	smart-8277e0ec-5079-4279-b2e0-53967888c6e2
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566885671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 49.clkmgr_lc_ctrl_intersig_mubi.566885671
Directory	/workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/49.clkmgr_peri.933413738
Short name	T548
Test name
Test status
Simulation time	37736742 ps
CPU time	0.78 seconds
Started	May 12 01:23:52 PM PDT 24
Finished	May 12 01:23:54 PM PDT 24
Peak memory	200296 kb
Host	smart-f107c914-eaa3-4faf-afbe-4fb7607c761b
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933413738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.933413738
Directory	/workspace/49.clkmgr_peri/latest

Test location	/workspace/coverage/default/49.clkmgr_regwen.184883256
Short name	T93
Test name
Test status
Simulation time	619560281 ps
CPU time	3.83 seconds
Started	May 12 01:23:47 PM PDT 24
Finished	May 12 01:23:51 PM PDT 24
Peak memory	200640 kb
Host	smart-67b8839b-2dc6-4281-b941-9cbdc1f93632
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184883256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.184883256
Directory	/workspace/49.clkmgr_regwen/latest

Test location	/workspace/coverage/default/49.clkmgr_smoke.1935827233
Short name	T547
Test name
Test status
Simulation time	22215374 ps
CPU time	0.89 seconds
Started	May 12 01:23:45 PM PDT 24
Finished	May 12 01:23:46 PM PDT 24
Peak memory	200516 kb
Host	smart-d3c398ca-85d1-4c2c-bd78-ce4262627cf4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935827233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.1935827233
Directory	/workspace/49.clkmgr_smoke/latest

Test location	/workspace/coverage/default/49.clkmgr_stress_all.2036179613
Short name	T811
Test name
Test status
Simulation time	7416732091 ps
CPU time	53.11 seconds
Started	May 12 01:23:46 PM PDT 24
Finished	May 12 01:24:40 PM PDT 24
Peak memory	200860 kb
Host	smart-1ee3332b-8dfd-404e-ac67-be9e44977eec
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036179613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all.2036179613
Directory	/workspace/49.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/49.clkmgr_stress_all_with_rand_reset.2002671428
Short name	T78
Test name
Test status
Simulation time	35665167727 ps
CPU time	225.61 seconds
Started	May 12 01:23:51 PM PDT 24
Finished	May 12 01:27:38 PM PDT 24
Peak memory	209132 kb
Host	smart-7505a93f-1218-452a-87de-a77e7acf3231
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2002671428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.2002671428
Directory	/workspace/49.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.clkmgr_trans.3470814676
Short name	T533
Test name
Test status
Simulation time	173157493 ps
CPU time	1.2 seconds
Started	May 12 01:23:48 PM PDT 24
Finished	May 12 01:23:50 PM PDT 24
Peak memory	200496 kb
Host	smart-ff820298-3e84-4842-86ef-d9255670d8f0
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470814676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.3470814676
Directory	/workspace/49.clkmgr_trans/latest

Test location	/workspace/coverage/default/5.clkmgr_alert_test.3287187820
Short name	T571
Test name
Test status
Simulation time	73976318 ps
CPU time	0.95 seconds
Started	May 12 01:21:44 PM PDT 24
Finished	May 12 01:21:45 PM PDT 24
Peak memory	200524 kb
Host	smart-5660b33c-76a0-4a67-8119-c81f2c3a6aff
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287187820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm gr_alert_test.3287187820
Directory	/workspace/5.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.941432900
Short name	T275
Test name
Test status
Simulation time	18507190 ps
CPU time	0.8 seconds
Started	May 12 01:21:41 PM PDT 24
Finished	May 12 01:21:42 PM PDT 24
Peak memory	200500 kb
Host	smart-e7f87cc7-49ba-4cde-8a56-e4e26bd6c632
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941432900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_handshake_intersig_mubi.941432900
Directory	/workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_clk_status.3215670415
Short name	T60
Test name
Test status
Simulation time	52033426 ps
CPU time	0.82 seconds
Started	May 12 01:21:39 PM PDT 24
Finished	May 12 01:21:40 PM PDT 24
Peak memory	199520 kb
Host	smart-b8450a04-0525-4c93-96ce-7d38177f9eba
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215670415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.3215670415
Directory	/workspace/5.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/5.clkmgr_div_intersig_mubi.3881833417
Short name	T661
Test name
Test status
Simulation time	36302999 ps
CPU time	0.85 seconds
Started	May 12 01:21:38 PM PDT 24
Finished	May 12 01:21:39 PM PDT 24
Peak memory	200448 kb
Host	smart-eda5f4f6-02bd-46b6-9f86-d4f7b73acffd
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881833417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_div_intersig_mubi.3881833417
Directory	/workspace/5.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_extclk.1839996861
Short name	T774
Test name
Test status
Simulation time	12883538 ps
CPU time	0.72 seconds
Started	May 12 01:21:33 PM PDT 24
Finished	May 12 01:21:34 PM PDT 24
Peak memory	200456 kb
Host	smart-f913d181-f7a2-4fec-8da0-4e119c19eb06
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839996861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.1839996861
Directory	/workspace/5.clkmgr_extclk/latest

Test location	/workspace/coverage/default/5.clkmgr_frequency.2352178621
Short name	T131
Test name
Test status
Simulation time	2124572282 ps
CPU time	13.23 seconds
Started	May 12 01:21:34 PM PDT 24
Finished	May 12 01:21:48 PM PDT 24
Peak memory	200752 kb
Host	smart-30159244-aaee-405a-b1d2-0dc9682247bc
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352178621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.2352178621
Directory	/workspace/5.clkmgr_frequency/latest

Test location	/workspace/coverage/default/5.clkmgr_frequency_timeout.3848190320
Short name	T481
Test name
Test status
Simulation time	1343461877 ps
CPU time	9.95 seconds
Started	May 12 01:21:36 PM PDT 24
Finished	May 12 01:21:46 PM PDT 24
Peak memory	200648 kb
Host	smart-43b1d0f9-d99b-4d4d-a33f-449d3b109ada
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848190320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti meout.3848190320
Directory	/workspace/5.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/5.clkmgr_idle_intersig_mubi.2321288004
Short name	T723
Test name
Test status
Simulation time	45815754 ps
CPU time	0.98 seconds
Started	May 12 01:21:39 PM PDT 24
Finished	May 12 01:21:41 PM PDT 24
Peak memory	200432 kb
Host	smart-86763e32-be99-4873-83d0-4b5742257032
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321288004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.2321288004
Directory	/workspace/5.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.3604366821
Short name	T26
Test name
Test status
Simulation time	76771121 ps
CPU time	1.05 seconds
Started	May 12 01:21:39 PM PDT 24
Finished	May 12 01:21:41 PM PDT 24
Peak memory	200432 kb
Host	smart-73d92c44-130f-44a1-b3e6-c374d14846ae
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604366821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 5.clkmgr_lc_clk_byp_req_intersig_mubi.3604366821
Directory	/workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.888497213
Short name	T689
Test name
Test status
Simulation time	13435456 ps
CPU time	0.71 seconds
Started	May 12 01:21:38 PM PDT 24
Finished	May 12 01:21:40 PM PDT 24
Peak memory	200488 kb
Host	smart-903d3c19-60b7-46ef-b39c-6810190bf5a1
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888497213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.clkmgr_lc_ctrl_intersig_mubi.888497213
Directory	/workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/5.clkmgr_peri.224614270
Short name	T205
Test name
Test status
Simulation time	42465910 ps
CPU time	0.8 seconds
Started	May 12 01:21:38 PM PDT 24
Finished	May 12 01:21:39 PM PDT 24
Peak memory	200260 kb
Host	smart-5ddbd63b-e780-41bd-b60b-4672afb0eebb
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224614270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.224614270
Directory	/workspace/5.clkmgr_peri/latest

Test location	/workspace/coverage/default/5.clkmgr_regwen.2027528149
Short name	T653
Test name
Test status
Simulation time	120450990 ps
CPU time	1.01 seconds
Started	May 12 01:21:39 PM PDT 24
Finished	May 12 01:21:41 PM PDT 24
Peak memory	200420 kb
Host	smart-0a5d7e2b-353d-44c9-853a-03b8dcabea3f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027528149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.2027528149
Directory	/workspace/5.clkmgr_regwen/latest

Test location	/workspace/coverage/default/5.clkmgr_smoke.2015408198
Short name	T25
Test name
Test status
Simulation time	43689524 ps
CPU time	0.89 seconds
Started	May 12 01:21:35 PM PDT 24
Finished	May 12 01:21:37 PM PDT 24
Peak memory	200504 kb
Host	smart-47856e76-387a-482a-bf67-d2eb6a5fe491
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015408198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.2015408198
Directory	/workspace/5.clkmgr_smoke/latest

Test location	/workspace/coverage/default/5.clkmgr_stress_all.408538322
Short name	T604
Test name
Test status
Simulation time	405647930 ps
CPU time	2.26 seconds
Started	May 12 01:21:42 PM PDT 24
Finished	May 12 01:21:44 PM PDT 24
Peak memory	200628 kb
Host	smart-7f4ae58d-ce52-4780-a25d-505ea10d3bea
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408538322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all.408538322
Directory	/workspace/5.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.2749420765
Short name	T529
Test name
Test status
Simulation time	86433733828 ps
CPU time	528.13 seconds
Started	May 12 01:21:39 PM PDT 24
Finished	May 12 01:30:27 PM PDT 24
Peak memory	209192 kb
Host	smart-249dd98f-8b68-4896-b007-5515fa052fc1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2749420765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.2749420765
Directory	/workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/5.clkmgr_trans.2589173620
Short name	T350
Test name
Test status
Simulation time	32694443 ps
CPU time	0.99 seconds
Started	May 12 01:21:40 PM PDT 24
Finished	May 12 01:21:42 PM PDT 24
Peak memory	200472 kb
Host	smart-867861ed-8a09-4efe-8162-128723689de3
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589173620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.2589173620
Directory	/workspace/5.clkmgr_trans/latest

Test location	/workspace/coverage/default/6.clkmgr_alert_test.647626333
Short name	T781
Test name
Test status
Simulation time	12070477 ps
CPU time	0.72 seconds
Started	May 12 01:21:43 PM PDT 24
Finished	May 12 01:21:44 PM PDT 24
Peak memory	200544 kb
Host	smart-08d9fbf6-befd-452e-b181-4f89bf72ca8f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647626333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmg r_alert_test.647626333
Directory	/workspace/6.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.3343074502
Short name	T619
Test name
Test status
Simulation time	150048267 ps
CPU time	1.15 seconds
Started	May 12 01:21:45 PM PDT 24
Finished	May 12 01:21:47 PM PDT 24
Peak memory	200508 kb
Host	smart-cd2a8591-7f0c-4168-9edf-3394729d964d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343074502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_handshake_intersig_mubi.3343074502
Directory	/workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_clk_status.3181362106
Short name	T717
Test name
Test status
Simulation time	57882157 ps
CPU time	0.77 seconds
Started	May 12 01:21:41 PM PDT 24
Finished	May 12 01:21:42 PM PDT 24
Peak memory	199532 kb
Host	smart-8b1244f1-247c-4c68-867a-8de279b4a3d1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181362106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.3181362106
Directory	/workspace/6.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/6.clkmgr_div_intersig_mubi.1074645896
Short name	T180
Test name
Test status
Simulation time	116202198 ps
CPU time	1.08 seconds
Started	May 12 01:21:44 PM PDT 24
Finished	May 12 01:21:46 PM PDT 24
Peak memory	200444 kb
Host	smart-ccbaa739-53f0-44ac-8692-1b71ec02a2eb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074645896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_div_intersig_mubi.1074645896
Directory	/workspace/6.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_extclk.1715114049
Short name	T128
Test name
Test status
Simulation time	410138529 ps
CPU time	1.89 seconds
Started	May 12 01:21:43 PM PDT 24
Finished	May 12 01:21:45 PM PDT 24
Peak memory	200432 kb
Host	smart-ee469a34-f102-45d4-81c2-39e82973401e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715114049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.1715114049
Directory	/workspace/6.clkmgr_extclk/latest

Test location	/workspace/coverage/default/6.clkmgr_frequency.4169434342
Short name	T607
Test name
Test status
Simulation time	2130071681 ps
CPU time	9.05 seconds
Started	May 12 01:21:43 PM PDT 24
Finished	May 12 01:21:52 PM PDT 24
Peak memory	200708 kb
Host	smart-4af6dd94-4a10-405e-831c-9d4527ad819e
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169434342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.4169434342
Directory	/workspace/6.clkmgr_frequency/latest

Test location	/workspace/coverage/default/6.clkmgr_frequency_timeout.3224013044
Short name	T351
Test name
Test status
Simulation time	502924833 ps
CPU time	2.95 seconds
Started	May 12 01:21:42 PM PDT 24
Finished	May 12 01:21:45 PM PDT 24
Peak memory	200608 kb
Host	smart-5354e574-900e-45c7-8ab6-8d3aa64ccc18
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224013044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti meout.3224013044
Directory	/workspace/6.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/6.clkmgr_idle_intersig_mubi.1354073848
Short name	T370
Test name
Test status
Simulation time	20193043 ps
CPU time	0.76 seconds
Started	May 12 01:21:46 PM PDT 24
Finished	May 12 01:21:47 PM PDT 24
Peak memory	200404 kb
Host	smart-be61a9e2-e6ec-4a4d-894b-cfd3faff2117
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354073848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_idle_intersig_mubi.1354073848
Directory	/workspace/6.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.2073473177
Short name	T452
Test name
Test status
Simulation time	60014068 ps
CPU time	0.92 seconds
Started	May 12 01:21:44 PM PDT 24
Finished	May 12 01:21:45 PM PDT 24
Peak memory	200500 kb
Host	smart-b72a4875-33b2-437f-8691-545d97391e76
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073473177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 6.clkmgr_lc_clk_byp_req_intersig_mubi.2073473177
Directory	/workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.1784597417
Short name	T324
Test name
Test status
Simulation time	82667296 ps
CPU time	1.01 seconds
Started	May 12 01:21:43 PM PDT 24
Finished	May 12 01:21:45 PM PDT 24
Peak memory	200532 kb
Host	smart-ccabd0cf-b3fc-4d5b-9ce1-3a02a8218343
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784597417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 6.clkmgr_lc_ctrl_intersig_mubi.1784597417
Directory	/workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/6.clkmgr_peri.3209563076
Short name	T372
Test name
Test status
Simulation time	16113876 ps
CPU time	0.77 seconds
Started	May 12 01:21:45 PM PDT 24
Finished	May 12 01:21:46 PM PDT 24
Peak memory	200296 kb
Host	smart-3894088a-2ad0-4077-af60-7941bba31380
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209563076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.3209563076
Directory	/workspace/6.clkmgr_peri/latest

Test location	/workspace/coverage/default/6.clkmgr_regwen.3176052192
Short name	T470
Test name
Test status
Simulation time	1394765928 ps
CPU time	5.2 seconds
Started	May 12 01:21:44 PM PDT 24
Finished	May 12 01:21:50 PM PDT 24
Peak memory	200656 kb
Host	smart-9a2f6ca7-2af5-4b48-923e-49d2f5f783a5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176052192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.3176052192
Directory	/workspace/6.clkmgr_regwen/latest

Test location	/workspace/coverage/default/6.clkmgr_smoke.1583679659
Short name	T537
Test name
Test status
Simulation time	23593562 ps
CPU time	0.83 seconds
Started	May 12 01:21:46 PM PDT 24
Finished	May 12 01:21:47 PM PDT 24
Peak memory	200480 kb
Host	smart-8e4c44f9-370e-45e3-8ac7-3b7ceafd976c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583679659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.1583679659
Directory	/workspace/6.clkmgr_smoke/latest

Test location	/workspace/coverage/default/6.clkmgr_stress_all.796453893
Short name	T392
Test name
Test status
Simulation time	4726048902 ps
CPU time	19.09 seconds
Started	May 12 01:21:44 PM PDT 24
Finished	May 12 01:22:04 PM PDT 24
Peak memory	200916 kb
Host	smart-5a8aabdb-0c41-48d7-9e55-d8f8ded50709
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796453893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM _TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all.796453893
Directory	/workspace/6.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/6.clkmgr_stress_all_with_rand_reset.1016713315
Short name	T747
Test name
Test status
Simulation time	97972294134 ps
CPU time	901.7 seconds
Started	May 12 01:21:43 PM PDT 24
Finished	May 12 01:36:45 PM PDT 24
Peak memory	216696 kb
Host	smart-abbbc90f-0641-4a4d-ad3b-d4f292d9066d
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1016713315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.1016713315
Directory	/workspace/6.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.clkmgr_trans.949838787
Short name	T83
Test name
Test status
Simulation time	18328125 ps
CPU time	0.81 seconds
Started	May 12 01:21:43 PM PDT 24
Finished	May 12 01:21:44 PM PDT 24
Peak memory	200484 kb
Host	smart-e8f85be4-4eff-41e9-b4ca-0a94e36d8545
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949838787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.949838787
Directory	/workspace/6.clkmgr_trans/latest

Test location	/workspace/coverage/default/7.clkmgr_alert_test.3718400159
Short name	T692
Test name
Test status
Simulation time	59699986 ps
CPU time	0.88 seconds
Started	May 12 01:21:53 PM PDT 24
Finished	May 12 01:21:55 PM PDT 24
Peak memory	200560 kb
Host	smart-49ce1f8f-4367-4e69-b095-33e89c33ed2a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718400159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm gr_alert_test.3718400159
Directory	/workspace/7.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.3330822122
Short name	T509
Test name
Test status
Simulation time	71212556 ps
CPU time	0.98 seconds
Started	May 12 01:21:49 PM PDT 24
Finished	May 12 01:21:50 PM PDT 24
Peak memory	200508 kb
Host	smart-7870054a-9de7-4bb5-a88f-c6cd834b4776
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330822122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_handshake_intersig_mubi.3330822122
Directory	/workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_clk_status.654938981
Short name	T488
Test name
Test status
Simulation time	15431307 ps
CPU time	0.71 seconds
Started	May 12 01:21:49 PM PDT 24
Finished	May 12 01:21:50 PM PDT 24
Peak memory	199524 kb
Host	smart-21e653e4-15c8-48ed-afb1-c81aa3ff1818
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654938981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.654938981
Directory	/workspace/7.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/7.clkmgr_div_intersig_mubi.2706414742
Short name	T631
Test name
Test status
Simulation time	12871609 ps
CPU time	0.72 seconds
Started	May 12 01:21:52 PM PDT 24
Finished	May 12 01:21:53 PM PDT 24
Peak memory	200484 kb
Host	smart-cf17111a-5e6d-4a4e-8ee0-86a555f8b8ad
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706414742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_div_intersig_mubi.2706414742
Directory	/workspace/7.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_extclk.1321222369
Short name	T176
Test name
Test status
Simulation time	92313974 ps
CPU time	1.09 seconds
Started	May 12 01:21:48 PM PDT 24
Finished	May 12 01:21:49 PM PDT 24
Peak memory	200500 kb
Host	smart-b9a79d5d-a298-46e0-9720-860d18881eda
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321222369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.1321222369
Directory	/workspace/7.clkmgr_extclk/latest

Test location	/workspace/coverage/default/7.clkmgr_frequency.332423496
Short name	T543
Test name
Test status
Simulation time	808269235 ps
CPU time	5.05 seconds
Started	May 12 01:21:49 PM PDT 24
Finished	May 12 01:21:55 PM PDT 24
Peak memory	200536 kb
Host	smart-47f874a5-0a5b-4bb3-851d-0a4aa703f0ae
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332423496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.332423496
Directory	/workspace/7.clkmgr_frequency/latest

Test location	/workspace/coverage/default/7.clkmgr_frequency_timeout.1625370242
Short name	T733
Test name
Test status
Simulation time	1961095203 ps
CPU time	8.1 seconds
Started	May 12 01:21:48 PM PDT 24
Finished	May 12 01:21:56 PM PDT 24
Peak memory	200640 kb
Host	smart-6660b1e0-6b6e-4df4-8dcc-9337de0f463c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625370242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti meout.1625370242
Directory	/workspace/7.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/7.clkmgr_idle_intersig_mubi.866186293
Short name	T530
Test name
Test status
Simulation time	24427850 ps
CPU time	0.88 seconds
Started	May 12 01:21:51 PM PDT 24
Finished	May 12 01:21:52 PM PDT 24
Peak memory	200508 kb
Host	smart-134429f7-b5f4-407a-bf8e-d1b37277f9e6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866186293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .clkmgr_idle_intersig_mubi.866186293
Directory	/workspace/7.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.884618030
Short name	T440
Test name
Test status
Simulation time	85224253 ps
CPU time	1.03 seconds
Started	May 12 01:21:48 PM PDT 24
Finished	May 12 01:21:49 PM PDT 24
Peak memory	200452 kb
Host	smart-e3a6e43a-651c-4dcf-9b83-e05adb8f4941
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884618030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.clkmgr_lc_clk_byp_req_intersig_mubi.884618030
Directory	/workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.2761686658
Short name	T329
Test name
Test status
Simulation time	27970105 ps
CPU time	0.91 seconds
Started	May 12 01:21:49 PM PDT 24
Finished	May 12 01:21:51 PM PDT 24
Peak memory	200464 kb
Host	smart-847c330a-5e26-406d-998d-821779664256
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761686658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 7.clkmgr_lc_ctrl_intersig_mubi.2761686658
Directory	/workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/7.clkmgr_peri.831855925
Short name	T267
Test name
Test status
Simulation time	15365778 ps
CPU time	0.72 seconds
Started	May 12 01:21:47 PM PDT 24
Finished	May 12 01:21:49 PM PDT 24
Peak memory	200308 kb
Host	smart-4493b480-25c4-4ef8-8ee9-19508ab488b8
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831855925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.831855925
Directory	/workspace/7.clkmgr_peri/latest

Test location	/workspace/coverage/default/7.clkmgr_regwen.3564667256
Short name	T476
Test name
Test status
Simulation time	1280266453 ps
CPU time	4.91 seconds
Started	May 12 01:21:49 PM PDT 24
Finished	May 12 01:21:55 PM PDT 24
Peak memory	200668 kb
Host	smart-c87185b3-6176-4a49-b260-dd33060ca7c5
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564667256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.3564667256
Directory	/workspace/7.clkmgr_regwen/latest

Test location	/workspace/coverage/default/7.clkmgr_smoke.3863492592
Short name	T155
Test name
Test status
Simulation time	22779420 ps
CPU time	0.86 seconds
Started	May 12 01:21:52 PM PDT 24
Finished	May 12 01:21:53 PM PDT 24
Peak memory	200488 kb
Host	smart-15153e69-b742-4eee-a201-639d74877924
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863492592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.3863492592
Directory	/workspace/7.clkmgr_smoke/latest

Test location	/workspace/coverage/default/7.clkmgr_stress_all.3155801110
Short name	T40
Test name
Test status
Simulation time	4236812769 ps
CPU time	16.64 seconds
Started	May 12 01:21:46 PM PDT 24
Finished	May 12 01:22:04 PM PDT 24
Peak memory	200924 kb
Host	smart-4e009c0c-0809-4c8a-ad20-30bacbcaf5e8
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155801110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all.3155801110
Directory	/workspace/7.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/7.clkmgr_stress_all_with_rand_reset.2255770704
Short name	T82
Test name
Test status
Simulation time	25704991406 ps
CPU time	394.53 seconds
Started	May 12 01:21:45 PM PDT 24
Finished	May 12 01:28:20 PM PDT 24
Peak memory	209204 kb
Host	smart-6728760a-d194-4898-9566-653994d83e76
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2255770704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.2255770704
Directory	/workspace/7.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.clkmgr_trans.1807727450
Short name	T453
Test name
Test status
Simulation time	39015056 ps
CPU time	0.75 seconds
Started	May 12 01:21:47 PM PDT 24
Finished	May 12 01:21:48 PM PDT 24
Peak memory	200360 kb
Host	smart-ee104d93-21a5-4284-a38a-410bdcd416e1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807727450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.1807727450
Directory	/workspace/7.clkmgr_trans/latest

Test location	/workspace/coverage/default/8.clkmgr_alert_test.1813697346
Short name	T759
Test name
Test status
Simulation time	38359331 ps
CPU time	0.76 seconds
Started	May 12 01:21:59 PM PDT 24
Finished	May 12 01:22:01 PM PDT 24
Peak memory	199952 kb
Host	smart-a8e1e99a-e816-41d0-85b0-6c6d1da3ea3a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813697346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm gr_alert_test.1813697346
Directory	/workspace/8.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.4198376397
Short name	T677
Test name
Test status
Simulation time	32543302 ps
CPU time	0.97 seconds
Started	May 12 01:21:55 PM PDT 24
Finished	May 12 01:21:57 PM PDT 24
Peak memory	200512 kb
Host	smart-df189cd6-93c3-4a0e-806f-5e3a02d1fc7d
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198376397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_handshake_intersig_mubi.4198376397
Directory	/workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_clk_status.500803339
Short name	T84
Test name
Test status
Simulation time	15243379 ps
CPU time	0.67 seconds
Started	May 12 01:21:51 PM PDT 24
Finished	May 12 01:21:52 PM PDT 24
Peak memory	199556 kb
Host	smart-74f3a62a-499a-4a3f-91a5-54c8809d6942
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500803339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.500803339
Directory	/workspace/8.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/8.clkmgr_div_intersig_mubi.2335627547
Short name	T441
Test name
Test status
Simulation time	18884406 ps
CPU time	0.75 seconds
Started	May 12 01:21:52 PM PDT 24
Finished	May 12 01:21:53 PM PDT 24
Peak memory	200516 kb
Host	smart-54db63d6-97fc-4b16-8beb-84a169bdef83
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335627547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_div_intersig_mubi.2335627547
Directory	/workspace/8.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_extclk.4233462324
Short name	T720
Test name
Test status
Simulation time	90141804 ps
CPU time	1.07 seconds
Started	May 12 01:21:55 PM PDT 24
Finished	May 12 01:21:57 PM PDT 24
Peak memory	200436 kb
Host	smart-fdd41083-907f-4e46-990a-95bbbfed0b07
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233462324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.4233462324
Directory	/workspace/8.clkmgr_extclk/latest

Test location	/workspace/coverage/default/8.clkmgr_frequency.3949696116
Short name	T256
Test name
Test status
Simulation time	1516797982 ps
CPU time	11.18 seconds
Started	May 12 01:21:52 PM PDT 24
Finished	May 12 01:22:03 PM PDT 24
Peak memory	200508 kb
Host	smart-86174772-49b4-4de1-9370-5099655bbd69
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949696116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.3949696116
Directory	/workspace/8.clkmgr_frequency/latest

Test location	/workspace/coverage/default/8.clkmgr_frequency_timeout.1299202547
Short name	T850
Test name
Test status
Simulation time	865316806 ps
CPU time	4.61 seconds
Started	May 12 01:21:56 PM PDT 24
Finished	May 12 01:22:01 PM PDT 24
Peak memory	200620 kb
Host	smart-c6bcd05e-1689-4957-ac0b-886885dac1a4
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299202547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti meout.1299202547
Directory	/workspace/8.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/8.clkmgr_idle_intersig_mubi.433184927
Short name	T302
Test name
Test status
Simulation time	31471562 ps
CPU time	0.94 seconds
Started	May 12 01:21:52 PM PDT 24
Finished	May 12 01:21:53 PM PDT 24
Peak memory	200504 kb
Host	smart-02959616-77d2-457c-9a8c-392fac755dde
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433184927 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .clkmgr_idle_intersig_mubi.433184927
Directory	/workspace/8.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.402412684
Short name	T629
Test name
Test status
Simulation time	39167454 ps
CPU time	0.81 seconds
Started	May 12 01:21:54 PM PDT 24
Finished	May 12 01:21:55 PM PDT 24
Peak memory	200512 kb
Host	smart-51ae919e-c452-42d7-9ca5-c4eccc3a4ac4
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402412684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.clkmgr_lc_clk_byp_req_intersig_mubi.402412684
Directory	/workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.3089818423
Short name	T563
Test name
Test status
Simulation time	46525638 ps
CPU time	0.83 seconds
Started	May 12 01:21:53 PM PDT 24
Finished	May 12 01:21:54 PM PDT 24
Peak memory	200524 kb
Host	smart-0b720238-ed02-42f0-b461-e0c4453746cb
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089818423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 8.clkmgr_lc_ctrl_intersig_mubi.3089818423
Directory	/workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/8.clkmgr_peri.2301756866
Short name	T357
Test name
Test status
Simulation time	31263424 ps
CPU time	0.76 seconds
Started	May 12 01:21:53 PM PDT 24
Finished	May 12 01:21:55 PM PDT 24
Peak memory	200312 kb
Host	smart-573f44de-05e0-42e0-ae57-17e339802999
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301756866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.2301756866
Directory	/workspace/8.clkmgr_peri/latest

Test location	/workspace/coverage/default/8.clkmgr_regwen.3125141483
Short name	T705
Test name
Test status
Simulation time	1103022493 ps
CPU time	6.54 seconds
Started	May 12 01:21:53 PM PDT 24
Finished	May 12 01:22:00 PM PDT 24
Peak memory	200684 kb
Host	smart-ca0caf9a-25c0-4e5c-ba34-9eb522143b38
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125141483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.3125141483
Directory	/workspace/8.clkmgr_regwen/latest

Test location	/workspace/coverage/default/8.clkmgr_smoke.1932299262
Short name	T635
Test name
Test status
Simulation time	26254669 ps
CPU time	0.91 seconds
Started	May 12 01:21:56 PM PDT 24
Finished	May 12 01:21:57 PM PDT 24
Peak memory	200480 kb
Host	smart-d07bcec0-b280-4bd2-9b40-868df9f02c34
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932299262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.1932299262
Directory	/workspace/8.clkmgr_smoke/latest

Test location	/workspace/coverage/default/8.clkmgr_stress_all.4187804261
Short name	T728
Test name
Test status
Simulation time	7457865765 ps
CPU time	29.97 seconds
Started	May 12 01:22:01 PM PDT 24
Finished	May 12 01:22:31 PM PDT 24
Peak memory	200832 kb
Host	smart-af691862-7926-4527-9429-e612e58b2df7
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187804261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all.4187804261
Directory	/workspace/8.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/8.clkmgr_stress_all_with_rand_reset.2665688717
Short name	T174
Test name
Test status
Simulation time	126287169605 ps
CPU time	734.77 seconds
Started	May 12 01:22:00 PM PDT 24
Finished	May 12 01:34:15 PM PDT 24
Peak memory	212504 kb
Host	smart-92289ac2-d39e-4021-a40f-a167c3ab3e3b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2665688717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.2665688717
Directory	/workspace/8.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/8.clkmgr_trans.2755744526
Short name	T802
Test name
Test status
Simulation time	27003217 ps
CPU time	0.92 seconds
Started	May 12 01:21:51 PM PDT 24
Finished	May 12 01:21:52 PM PDT 24
Peak memory	200420 kb
Host	smart-c7b4dbf2-f89f-4717-984b-2578e2c683a6
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755744526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.2755744526
Directory	/workspace/8.clkmgr_trans/latest

Test location	/workspace/coverage/default/9.clkmgr_alert_test.2454339276
Short name	T508
Test name
Test status
Simulation time	15448537 ps
CPU time	0.75 seconds
Started	May 12 01:21:57 PM PDT 24
Finished	May 12 01:21:58 PM PDT 24
Peak memory	200596 kb
Host	smart-48d2301d-4262-4ec3-95a6-4d2819889ea4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454339276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm gr_alert_test.2454339276
Directory	/workspace/9.clkmgr_alert_test/latest

Test location	/workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.518821957
Short name	T791
Test name
Test status
Simulation time	62513010 ps
CPU time	0.94 seconds
Started	May 12 01:21:55 PM PDT 24
Finished	May 12 01:21:57 PM PDT 24
Peak memory	200488 kb
Host	smart-bf9b5ebe-e1ad-41c3-a324-e404b67a4c6b
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518821957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_handshake_intersig_mubi.518821957
Directory	/workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_clk_status.175642351
Short name	T183
Test name
Test status
Simulation time	14014760 ps
CPU time	0.69 seconds
Started	May 12 01:21:55 PM PDT 24
Finished	May 12 01:21:57 PM PDT 24
Peak memory	199484 kb
Host	smart-8df03860-127e-4e68-9be1-67d13212245d
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175642351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.175642351
Directory	/workspace/9.clkmgr_clk_status/latest

Test location	/workspace/coverage/default/9.clkmgr_div_intersig_mubi.2871135111
Short name	T413
Test name
Test status
Simulation time	33653622 ps
CPU time	0.86 seconds
Started	May 12 01:21:56 PM PDT 24
Finished	May 12 01:21:57 PM PDT 24
Peak memory	200480 kb
Host	smart-3b167501-ef62-4dc9-aef2-d136cbd71823
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871135111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_div_intersig_mubi.2871135111
Directory	/workspace/9.clkmgr_div_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_extclk.2284651322
Short name	T494
Test name
Test status
Simulation time	49763707 ps
CPU time	0.94 seconds
Started	May 12 01:21:53 PM PDT 24
Finished	May 12 01:21:55 PM PDT 24
Peak memory	200512 kb
Host	smart-49dedaa0-dc1f-4694-9a5f-aff7176698a1
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284651322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.2284651322
Directory	/workspace/9.clkmgr_extclk/latest

Test location	/workspace/coverage/default/9.clkmgr_frequency.809626982
Short name	T688
Test name
Test status
Simulation time	2117140706 ps
CPU time	16.01 seconds
Started	May 12 01:21:53 PM PDT 24
Finished	May 12 01:22:09 PM PDT 24
Peak memory	200748 kb
Host	smart-1959f0ef-07e1-4f81-b0c3-bfe3eb650342
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809626982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.809626982
Directory	/workspace/9.clkmgr_frequency/latest

Test location	/workspace/coverage/default/9.clkmgr_frequency_timeout.230655899
Short name	T843
Test name
Test status
Simulation time	500662779 ps
CPU time	3.93 seconds
Started	May 12 01:21:53 PM PDT 24
Finished	May 12 01:21:57 PM PDT 24
Peak memory	200584 kb
Host	smart-5f13606c-8053-43ee-b0d0-04eccba4afaf
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230655899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_tim eout.230655899
Directory	/workspace/9.clkmgr_frequency_timeout/latest

Test location	/workspace/coverage/default/9.clkmgr_idle_intersig_mubi.344485187
Short name	T797
Test name
Test status
Simulation time	34195279 ps
CPU time	0.93 seconds
Started	May 12 01:21:52 PM PDT 24
Finished	May 12 01:21:54 PM PDT 24
Peak memory	200520 kb
Host	smart-c7776c2e-9689-4a8c-9d2d-12a575bea356
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344485187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .clkmgr_idle_intersig_mubi.344485187
Directory	/workspace/9.clkmgr_idle_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.3351236117
Short name	T737
Test name
Test status
Simulation time	45211361 ps
CPU time	0.81 seconds
Started	May 12 01:21:58 PM PDT 24
Finished	May 12 01:21:59 PM PDT 24
Peak memory	200504 kb
Host	smart-70295b2f-ca22-420c-8f6f-9a89e0c7cac6
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351236117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 9.clkmgr_lc_clk_byp_req_intersig_mubi.3351236117
Directory	/workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.3368792414
Short name	T459
Test name
Test status
Simulation time	29181793 ps
CPU time	0.92 seconds
Started	May 12 01:22:00 PM PDT 24
Finished	May 12 01:22:01 PM PDT 24
Peak memory	200500 kb
Host	smart-df9759ec-36b2-441a-8d50-e3bd098260c8
User	root
Command	/workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368792414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 9.clkmgr_lc_ctrl_intersig_mubi.3368792414
Directory	/workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspace/coverage/default/9.clkmgr_peri.644224187
Short name	T829
Test name
Test status
Simulation time	13816048 ps
CPU time	0.74 seconds
Started	May 12 01:21:53 PM PDT 24
Finished	May 12 01:21:54 PM PDT 24
Peak memory	200312 kb
Host	smart-4a8247ea-15b6-4133-a500-5d0221fe041f
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644224187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.644224187
Directory	/workspace/9.clkmgr_peri/latest

Test location	/workspace/coverage/default/9.clkmgr_regwen.2532349670
Short name	T429
Test name
Test status
Simulation time	835137410 ps
CPU time	3.21 seconds
Started	May 12 01:21:57 PM PDT 24
Finished	May 12 01:22:00 PM PDT 24
Peak memory	200720 kb
Host	smart-1da09c3e-fc31-44aa-8adb-4a9582de7dfa
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532349670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.2532349670
Directory	/workspace/9.clkmgr_regwen/latest

Test location	/workspace/coverage/default/9.clkmgr_smoke.4036612709
Short name	T807
Test name
Test status
Simulation time	68246622 ps
CPU time	1 seconds
Started	May 12 01:21:55 PM PDT 24
Finished	May 12 01:21:57 PM PDT 24
Peak memory	200512 kb
Host	smart-d4208d1b-5880-4139-9599-57315c45693c
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036612709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.4036612709
Directory	/workspace/9.clkmgr_smoke/latest

Test location	/workspace/coverage/default/9.clkmgr_stress_all.1112059661
Short name	T2
Test name
Test status
Simulation time	2013687221 ps
CPU time	14.57 seconds
Started	May 12 01:21:58 PM PDT 24
Finished	May 12 01:22:13 PM PDT 24
Peak memory	200812 kb
Host	smart-b40d762b-684b-4982-9ca6-39826cd147fc
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112059661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all.1112059661
Directory	/workspace/9.clkmgr_stress_all/latest

Test location	/workspace/coverage/default/9.clkmgr_trans.418685446
Short name	T388
Test name
Test status
Simulation time	153534647 ps
CPU time	1.27 seconds
Started	May 12 01:22:00 PM PDT 24
Finished	May 12 01:22:01 PM PDT 24
Peak memory	200440 kb
Host	smart-79cdcfbe-2664-47eb-8998-d9fb82547dec
User	root
Command	/workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418685446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.418685446
Directory	/workspace/9.clkmgr_trans/latest

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