Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

340050582

1

T1

284212

T6

3172

T4

12964

auto[1]

446530

1

T1

74

T17

86

T18

664

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

340071642

1

T1

284278

T6

3172

T4

9962

auto[1]

425470

1

T1

8

T4

3002

T17

260

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

339988784

1

T1

284212

T6

3172

T4

9962

auto[1]

508328

1

T1

74

T4

3002

T5

814

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

320387030

1

T1

282596

T6

3172

T4

12964

auto[1]

20110082

1

T1

1690

T17

2752

T2

22660

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

200332678

1

T1

279020

T6

3152

T4

12946

auto[1]

140164434

1

T1

5266

T6

20

T4

18

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

182683458

1

T1

277330

T6

3152

T4

9944

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

137358562

1

T1

5266

T6

20

T4

18

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

32742

1

T18

46

T2

634

T26

230

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7746

1

T18

26

T2

154

T104

12

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

17026806

1

T1

1606

T17

2454

T2

11468

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2685304

1

T17

92

T2

2918

T19

122

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

57018

1

T1

10

T2

1366

T26

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13644

1

T2

258

T29

16

T104

94

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

60690

1

T2

176

T19

16

T10

126

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1660

1

T2

82

T104

10

T10

84

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12010

1

T2

190

T10

166

T11

48

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3154

1

T2

76

T104

72

T10

92

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

13332

1

T17

26

T2

180

T26

38

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3068

1

T2

304

T26

22

T29

18

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

23946

1

T17

44

T2

244

T104

72

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5644

1

T2

104

T29

64

T157

40

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

48734

1

T5

814

T17

8

T18

96

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4160

1

T18

30

T2

90

T19

28

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

32988

1

T18

240

T2

502

T26

130

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

9114

1

T18

128

T2

106

T10

310

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

30538

1

T1

2

T17

16

T2

684

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6858

1

T2

78

T104

38

T10

352

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

60110

1

T1

64

T2

1158

T26

68

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13860

1

T2

168

T104

42

T10

368

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

61180

1

T4

3002

T17

28

T18

92

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6278

1

T18

34

T10

70

T11

218

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

51982

1

T17

42

T18

78

T2

878

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12572

1

T18

146

T10

182

T11

234

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

48352

1

T1

8

T17

112

T2

1232

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11602

1

T17

8

T2

350

T19

46

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

88792

1

T2

1644

T26

82

T104

120

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

21208

1

T2

504

T10

526

T105

80