Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 287904170 1 T5 390478 T7 1704 T8 3170
auto[1] 357246 1 T7 56 T8 666 T1 1030


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 287915536 1 T5 390478 T7 1760 T8 3550
auto[1] 345880 1 T8 286 T1 734 T19 102


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 287836668 1 T5 390478 T7 1626 T8 3238
auto[1] 424748 1 T7 134 T8 598 T1 1146


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 276012442 1 T5 390478 T7 1638 T8 3694
auto[1] 12248974 1 T7 122 T8 142 T1 3476


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 160226270 1 T5 390110 T7 1760 T8 3582
auto[1] 128035146 1 T5 368 T8 254 T1 111228


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 150180812 1 T5 390110 T7 1552 T8 2674
auto[0] auto[0] auto[0] auto[0] auto[1] 125539738 1 T5 368 T8 194 T1 110530
auto[0] auto[0] auto[0] auto[1] auto[0] 25742 1 T8 188 T1 38 T19 24
auto[0] auto[0] auto[0] auto[1] auto[1] 5570 1 T1 10 T21 12 T2 12
auto[0] auto[0] auto[1] auto[0] auto[0] 9540476 1 T7 74 T8 84 T1 2158
auto[0] auto[0] auto[1] auto[0] auto[1] 2394050 1 T1 332 T21 76 T22 210
auto[0] auto[0] auto[1] auto[1] auto[0] 42312 1 T1 146 T21 44 T22 44
auto[0] auto[0] auto[1] auto[1] auto[1] 11308 1 T1 34 T21 16 T22 8
auto[0] auto[1] auto[0] auto[0] auto[0] 48646 1 T8 14 T1 20 T19 20
auto[0] auto[1] auto[0] auto[0] auto[1] 1280 1 T67 8 T12 16 T14 30
auto[0] auto[1] auto[0] auto[1] auto[0] 10476 1 T8 84 T1 44 T2 44
auto[0] auto[1] auto[0] auto[1] auto[1] 2968 1 T12 144 T14 124 T17 62
auto[0] auto[1] auto[1] auto[0] auto[0] 8900 1 T21 6 T22 26 T2 22
auto[0] auto[1] auto[1] auto[0] auto[1] 2562 1 T23 28 T2 16 T12 40
auto[0] auto[1] auto[1] auto[1] auto[0] 16612 1 T21 54 T22 144 T2 108
auto[0] auto[1] auto[1] auto[1] auto[1] 5216 1 T12 172 T14 60 T28 70
auto[1] auto[0] auto[0] auto[0] auto[0] 41852 1 T7 30 T8 94 T1 40
auto[1] auto[0] auto[0] auto[0] auto[1] 3914 1 T8 60 T1 50 T133 2
auto[1] auto[0] auto[0] auto[1] auto[0] 28042 1 T7 56 T8 198 T23 120
auto[1] auto[0] auto[0] auto[1] auto[1] 7668 1 T1 52 T133 60 T135 50
auto[1] auto[0] auto[1] auto[0] auto[0] 26140 1 T7 48 T8 20 T1 50
auto[1] auto[0] auto[1] auto[0] auto[1] 6174 1 T1 44 T22 4 T2 116
auto[1] auto[0] auto[1] auto[1] auto[0] 50026 1 T8 38 T1 124 T21 64
auto[1] auto[0] auto[1] auto[1] auto[1] 11712 1 T1 116 T22 120 T2 364
auto[1] auto[1] auto[0] auto[0] auto[0] 57956 1 T8 30 T1 86 T19 18
auto[1] auto[1] auto[0] auto[0] auto[1] 5600 1 T21 12 T22 28 T2 4
auto[1] auto[1] auto[0] auto[1] auto[0] 42804 1 T8 158 T1 112 T19 64
auto[1] auto[1] auto[0] auto[1] auto[1] 9374 1 T21 74 T2 100 T12 70
auto[1] auto[1] auto[1] auto[0] auto[0] 37460 1 T1 116 T20 36 T21 82
auto[1] auto[1] auto[1] auto[0] auto[1] 8610 1 T1 2 T21 16 T22 8
auto[1] auto[1] auto[1] auto[1] auto[0] 68014 1 T1 296 T21 196 T22 210
auto[1] auto[1] auto[1] auto[1] auto[1] 19402 1 T1 58 T21 70 T2 224

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