Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 306216356 1 T6 4852 T5 75798 T1 176456
auto[1] 429164 1 T20 494 T23 470 T2 862


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 306212742 1 T6 4852 T5 75798 T1 176456
auto[1] 432778 1 T20 272 T23 256 T2 414


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 306134262 1 T6 4852 T5 75798 T1 176456
auto[1] 511258 1 T20 466 T23 538 T2 508


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 285241864 1 T6 4852 T5 75798 T1 176456
auto[1] 21403656 1 T20 3892 T23 3286 T2 2694


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 184981396 1 T6 1676 T5 75798 T1 176456
auto[1] 121664124 1 T6 3176 T16 36 T18 266


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 167077868 1 T6 1676 T5 75798 T1 176456
auto[0] auto[0] auto[0] auto[0] auto[1] 117831926 1 T6 3176 T16 36 T18 266
auto[0] auto[0] auto[0] auto[1] auto[0] 30416 1 T20 10 T23 2 T2 36
auto[0] auto[0] auto[0] auto[1] auto[1] 7618 1 T3 26 T9 144 T70 34
auto[0] auto[0] auto[1] auto[0] auto[0] 17309208 1 T20 3080 T23 2656 T2 1562
auto[0] auto[0] auto[1] auto[0] auto[1] 3706496 1 T20 244 T23 150 T2 184
auto[0] auto[0] auto[1] auto[1] auto[0] 55718 1 T20 136 T23 40 T2 262
auto[0] auto[0] auto[1] auto[1] auto[1] 14520 1 T2 108 T27 2 T97 22
auto[0] auto[1] auto[0] auto[0] auto[0] 44256 1 T20 2 T27 54 T3 8
auto[0] auto[1] auto[0] auto[0] auto[1] 1758 1 T9 38 T15 156 T147 2
auto[0] auto[1] auto[0] auto[1] auto[0] 11024 1 T20 52 T27 72 T9 164
auto[0] auto[1] auto[0] auto[1] auto[1] 3122 1 T9 116 T15 186 T147 52
auto[0] auto[1] auto[1] auto[0] auto[0] 10604 1 T23 20 T2 198 T27 22
auto[0] auto[1] auto[1] auto[0] auto[1] 2872 1 T20 16 T9 28 T70 16
auto[0] auto[1] auto[1] auto[1] auto[0] 20874 1 T23 44 T2 140 T27 156
auto[0] auto[1] auto[1] auto[1] auto[1] 5982 1 T9 84 T70 48 T12 56
auto[1] auto[0] auto[0] auto[0] auto[0] 22884 1 T20 8 T23 28 T2 20
auto[1] auto[0] auto[0] auto[0] auto[1] 4420 1 T20 8 T2 102 T27 38
auto[1] auto[0] auto[0] auto[1] auto[0] 33658 1 T23 60 T2 70 T3 40
auto[1] auto[0] auto[0] auto[1] auto[1] 8098 1 T9 242 T10 84 T12 108
auto[1] auto[0] auto[1] auto[0] auto[0] 28752 1 T20 36 T23 32 T2 36
auto[1] auto[0] auto[1] auto[0] auto[1] 8088 1 T20 6 T23 30 T2 10
auto[1] auto[0] auto[1] auto[1] auto[0] 58494 1 T20 158 T23 60 T2 122
auto[1] auto[0] auto[1] auto[1] auto[1] 14578 1 T20 48 T23 136 T2 72
auto[1] auto[1] auto[0] auto[0] auto[0] 99584 1 T20 34 T23 16 T2 24
auto[1] auto[1] auto[0] auto[0] auto[1] 6698 1 T27 20 T97 14 T3 32
auto[1] auto[1] auto[0] auto[1] auto[0] 45832 1 T23 58 T2 52 T3 54
auto[1] auto[1] auto[0] auto[1] auto[1] 12702 1 T27 76 T97 36 T3 40
auto[1] auto[1] auto[1] auto[0] auto[0] 47782 1 T20 78 T23 48 T27 48
auto[1] auto[1] auto[1] auto[0] auto[1] 13160 1 T27 56 T9 426 T10 32
auto[1] auto[1] auto[1] auto[1] auto[0] 84442 1 T20 90 T23 70 T27 214
auto[1] auto[1] auto[1] auto[1] auto[1] 22086 1 T9 392 T10 190 T70 110

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