Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 302284718 1 T1 755690 T5 3726 T4 363988
auto[1] 405210 1 T1 260 T5 692 T17 368


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 302271398 1 T1 755950 T5 3854 T4 363988
auto[1] 418530 1 T5 564 T17 312 T19 124


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 302197188 1 T1 755638 T5 3748 T4 363988
auto[1] 492740 1 T1 312 T5 670 T17 386


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 279244886 1 T1 754100 T5 2742 T4 363988
auto[1] 23445042 1 T1 1850 T5 1676 T17 128


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 175704036 1 T1 739670 T5 3910 T4 363970
auto[1] 126985892 1 T1 16280 T5 508 T4 18


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 153987354 1 T1 737974 T5 2568 T4 363970
auto[0] auto[0] auto[0] auto[0] auto[1] 124911772 1 T1 16126 T5 18 T4 18
auto[0] auto[0] auto[0] auto[1] auto[0] 31100 1 T5 8 T17 60 T21 12
auto[0] auto[0] auto[0] auto[1] auto[1] 7722 1 T17 48 T38 68 T104 32
auto[0] auto[0] auto[1] auto[0] auto[0] 21131832 1 T1 1460 T5 700 T17 104
auto[0] auto[0] auto[1] auto[0] auto[1] 1963652 1 T1 50 T5 290 T38 232
auto[0] auto[0] auto[1] auto[1] auto[0] 48494 1 T1 6 T5 88 T38 56
auto[0] auto[0] auto[1] auto[1] auto[1] 12086 1 T1 22 T5 76 T38 16
auto[0] auto[1] auto[0] auto[0] auto[0] 48622 1 T17 28 T19 22 T3 48
auto[0] auto[1] auto[0] auto[0] auto[1] 1576 1 T17 12 T62 36 T52 36
auto[0] auto[1] auto[0] auto[1] auto[0] 12924 1 T9 196 T168 64 T134 62
auto[0] auto[1] auto[0] auto[1] auto[1] 2482 1 T17 76 T62 38 T52 104
auto[0] auto[1] auto[1] auto[0] auto[0] 9956 1 T17 24 T19 24 T38 58
auto[0] auto[1] auto[1] auto[0] auto[1] 2808 1 T52 26 T148 2 T138 8
auto[0] auto[1] auto[1] auto[1] auto[0] 20250 1 T38 126 T3 216 T59 62
auto[0] auto[1] auto[1] auto[1] auto[1] 4558 1 T52 46 T148 50 T138 96
auto[1] auto[0] auto[0] auto[0] auto[0] 32688 1 T17 68 T19 8 T38 12
auto[1] auto[0] auto[0] auto[0] auto[1] 4146 1 T17 102 T104 18 T9 84
auto[1] auto[0] auto[0] auto[1] auto[0] 30584 1 T38 68 T3 340 T9 288
auto[1] auto[0] auto[0] auto[1] auto[1] 8562 1 T17 44 T104 52 T9 208
auto[1] auto[0] auto[1] auto[0] auto[0] 28338 1 T1 58 T5 16 T19 32
auto[1] auto[0] auto[1] auto[0] auto[1] 6232 1 T1 22 T38 14 T3 24
auto[1] auto[0] auto[1] auto[1] auto[0] 55016 1 T1 172 T5 90 T2 50
auto[1] auto[0] auto[1] auto[1] auto[1] 11820 1 T1 60 T38 68 T3 122
auto[1] auto[1] auto[0] auto[0] auto[0] 97672 1 T5 22 T17 32 T21 14
auto[1] auto[1] auto[0] auto[0] auto[1] 5382 1 T2 8 T3 140 T60 22
auto[1] auto[1] auto[0] auto[1] auto[0] 50664 1 T5 126 T17 140 T21 64
auto[1] auto[1] auto[0] auto[1] auto[1] 11636 1 T3 108 T60 66 T9 38
auto[1] auto[1] auto[1] auto[0] auto[0] 41940 1 T5 82 T19 78 T38 38
auto[1] auto[1] auto[1] auto[0] auto[1] 10748 1 T5 30 T38 14 T103 6
auto[1] auto[1] auto[1] auto[1] auto[0] 76602 1 T5 210 T38 136 T103 124
auto[1] auto[1] auto[1] auto[1] auto[1] 20710 1 T5 94 T38 124 T103 52

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