Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299071078

1

T6

3002

T4

256192

T7

2172

auto[1]

376156

1

T6

1308

T7

356

T15

252

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299090524

1

T6

3194

T4

256192

T7

2108

auto[1]

356710

1

T6

1116

T7

420

T15

274

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298988402

1

T6

3154

T4

256192

T7

2038

auto[1]

458832

1

T6

1156

T7

490

T15

274

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

284566404

1

T6

1956

T4

256192

T7

378

auto[1]

14880830

1

T6

2354

T7

2150

T15

1600

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

183806148

1

T6

3570

T4

256176

T7

2448

auto[1]

115641086

1

T6

740

T4

16

T7

80

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

170845106

1

T6

1422

T4

256176

T7

254

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

113401458

1

T6

150

T4

16

T22

2950

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

27396

1

T6

66

T2

258

T21

30

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5880

1

T2

26

T27

10

T28

28

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

12411456

1

T6

940

T7

1690

T15

162

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2135430

1

T6

248

T7

72

T15

1112

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

46158

1

T6

176

T7

22

T15

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

11814

1

T6

152

T15

44

T2

92

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

53312

1

T2

50

T80

32

T9

20

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1330

1

T28

10

T140

4

T12

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

11170

1

T2

150

T9

42

T11

42

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3348

1

T140

60

T12

36

T167

56

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

9950

1

T2

80

T3

16

T28

30

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2270

1

T80

18

T166

44

T12

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

17624

1

T2

154

T3

80

T137

86

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4700

1

T80

46

T166

76

T65

44

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

69792

1

T7

8

T2

152

T3

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3332

1

T2

4

T21

18

T80

16

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

29956

1

T2

530

T3

60

T27

54

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6816

1

T2

56

T21

54

T80

66

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

26438

1

T6

40

T7

12

T2

250

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5958

1

T2

38

T80

68

T137

18

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

50788

1

T7

50

T2

720

T21

268

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12746

1

T2

166

T80

204

T137

90

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

50384

1

T6

38

T7

54

T2

82

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

4842

1

T2

56

T27

20

T28

14

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

43044

1

T6

280

T7

62

T2

334

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

9238

1

T2

118

T27

48

T28

52

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

39588

1

T6

126

T7

74

T15

42

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10432

1

T6

38

T7

8

T15

32

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

73986

1

T6

482

T7

222

T15

120

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

21492

1

T6

152

T15

80

T2

404