Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 342776684 1 T4 7620 T6 4578 T7 2654
auto[1] 473642 1 T27 672 T20 1336 T21 456


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 342782080 1 T4 5762 T6 4578 T7 2654
auto[1] 468246 1 T4 1858 T27 542 T20 956


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 342706588 1 T4 5762 T6 4578 T7 2654
auto[1] 543738 1 T4 1858 T27 668 T20 1128


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 318676280 1 T4 7620 T6 4578 T7 2654
auto[1] 24574046 1 T20 3394 T21 2100 T23 1120


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 182565532 1 T4 7620 T6 1556 T7 2654
auto[1] 160684794 1 T6 3022 T25 4334 T5 48


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 165451654 1 T4 5762 T6 1556 T7 2654
auto[0] auto[0] auto[0] auto[0] auto[1] 152854166 1 T6 3022 T25 4334 T5 48
auto[0] auto[0] auto[0] auto[1] auto[0] 34964 1 T27 80 T20 116 T21 34
auto[0] auto[0] auto[0] auto[1] auto[1] 7818 1 T20 18 T23 10 T2 60
auto[0] auto[0] auto[1] auto[0] auto[0] 16444610 1 T20 2208 T21 1634 T23 468
auto[0] auto[0] auto[1] auto[0] auto[1] 7701946 1 T20 188 T21 142 T23 226
auto[0] auto[0] auto[1] auto[1] auto[0] 61802 1 T20 236 T21 24 T23 72
auto[0] auto[0] auto[1] auto[1] auto[1] 16476 1 T21 40 T23 8 T2 62
auto[0] auto[1] auto[0] auto[0] auto[0] 69872 1 T27 2 T20 2 T2 68
auto[0] auto[1] auto[0] auto[0] auto[1] 1692 1 T2 10 T44 18 T70 8
auto[0] auto[1] auto[0] auto[1] auto[0] 14276 1 T27 50 T20 82 T2 50
auto[0] auto[1] auto[0] auto[1] auto[1] 2988 1 T2 66 T70 74 T13 178
auto[0] auto[1] auto[1] auto[0] auto[0] 13388 1 T20 40 T2 30 T42 16
auto[0] auto[1] auto[1] auto[0] auto[1] 2558 1 T10 4 T67 32 T13 72
auto[0] auto[1] auto[1] auto[1] auto[0] 22882 1 T20 120 T2 156 T42 70
auto[0] auto[1] auto[1] auto[1] auto[1] 5496 1 T10 62 T13 132 T28 40
auto[1] auto[0] auto[0] auto[0] auto[0] 38594 1 T27 34 T20 34 T21 18
auto[1] auto[0] auto[0] auto[0] auto[1] 3742 1 T2 64 T103 46 T10 16
auto[1] auto[0] auto[0] auto[1] auto[0] 36214 1 T27 144 T20 142 T21 74
auto[1] auto[0] auto[0] auto[1] auto[1] 8096 1 T2 100 T10 100 T13 378
auto[1] auto[0] auto[1] auto[0] auto[0] 34332 1 T20 26 T23 8 T2 96
auto[1] auto[0] auto[1] auto[0] auto[1] 9474 1 T20 28 T21 16 T23 10
auto[1] auto[0] auto[1] auto[1] auto[0] 63028 1 T20 122 T23 94 T2 454
auto[1] auto[0] auto[1] auto[1] auto[1] 15164 1 T20 64 T21 66 T23 58
auto[1] auto[1] auto[0] auto[0] auto[0] 75696 1 T4 1858 T27 82 T20 70
auto[1] auto[1] auto[0] auto[0] auto[1] 7018 1 T27 10 T20 14 T23 2
auto[1] auto[1] auto[0] auto[1] auto[0] 56276 1 T27 398 T20 130 T21 68
auto[1] auto[1] auto[0] auto[1] auto[1] 13214 1 T20 136 T23 56 T2 118
auto[1] auto[1] auto[1] auto[0] auto[0] 54650 1 T20 150 T21 14 T23 26
auto[1] auto[1] auto[1] auto[0] auto[1] 13292 1 T20 42 T21 14 T23 24
auto[1] auto[1] auto[1] auto[1] auto[0] 93294 1 T20 170 T21 74 T23 62
auto[1] auto[1] auto[1] auto[1] auto[1] 21654 1 T21 76 T23 64 T2 158

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