Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 286775468 1 T7 6328 T8 2492 T5 26984
auto[1] 374012 1 T8 150 T1 4144 T20 686


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 286785980 1 T7 6328 T8 2530 T5 26984
auto[1] 363500 1 T8 112 T1 2982 T20 406


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 286694084 1 T7 6328 T8 2440 T5 26984
auto[1] 455396 1 T8 202 T1 3670 T20 654


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 262764866 1 T7 6328 T8 188 T5 26984
auto[1] 24384614 1 T8 2454 T1 16128 T20 616


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 165291094 1 T7 1468 T8 2484 T5 26964
auto[1] 121858386 1 T7 4860 T8 158 T5 20


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 146021100 1 T7 1468 T8 30 T5 26964
auto[0] auto[0] auto[0] auto[0] auto[1] 116416596 1 T7 4860 T8 104 T5 20
auto[0] auto[0] auto[0] auto[1] auto[0] 28660 1 T1 248 T20 48 T21 52
auto[0] auto[0] auto[0] auto[1] auto[1] 6282 1 T8 12 T1 6 T20 44
auto[0] auto[0] auto[1] auto[0] auto[0] 18723048 1 T8 2294 T1 10548 T20 112
auto[0] auto[0] auto[1] auto[0] auto[1] 5343956 1 T1 2360 T20 216 T24 104
auto[0] auto[0] auto[1] auto[1] auto[0] 43602 1 T1 562 T24 128 T25 160
auto[0] auto[0] auto[1] auto[1] auto[1] 10880 1 T1 104 T20 54 T25 52
auto[0] auto[1] auto[0] auto[0] auto[0] 51402 1 T1 2 T20 6 T104 22
auto[0] auto[1] auto[0] auto[0] auto[1] 1574 1 T189 28 T195 4 T65 32
auto[0] auto[1] auto[0] auto[1] auto[0] 11312 1 T1 44 T20 74 T104 68
auto[0] auto[1] auto[0] auto[1] auto[1] 2808 1 T189 48 T195 80 T196 82
auto[0] auto[1] auto[1] auto[0] auto[0] 8974 1 T1 74 T24 22 T116 68
auto[0] auto[1] auto[1] auto[0] auto[1] 1834 1 T1 2 T25 16 T117 2
auto[0] auto[1] auto[1] auto[1] auto[0] 18512 1 T1 328 T24 148 T116 168
auto[0] auto[1] auto[1] auto[1] auto[1] 3544 1 T1 50 T25 82 T117 50
auto[1] auto[0] auto[0] auto[0] auto[0] 59008 1 T1 90 T20 26 T21 38
auto[1] auto[0] auto[0] auto[0] auto[1] 3098 1 T1 16 T20 8 T116 10
auto[1] auto[0] auto[0] auto[1] auto[0] 30452 1 T1 160 T20 112 T21 272
auto[1] auto[0] auto[0] auto[1] auto[1] 5888 1 T1 114 T20 48 T116 58
auto[1] auto[0] auto[1] auto[0] auto[0] 25680 1 T8 44 T1 210 T24 14
auto[1] auto[0] auto[1] auto[0] auto[1] 6156 1 T1 2 T20 16 T25 22
auto[1] auto[0] auto[1] auto[1] auto[0] 48956 1 T8 46 T1 542 T24 76
auto[1] auto[0] auto[1] auto[1] auto[1] 12618 1 T1 54 T20 118 T25 76
auto[1] auto[1] auto[0] auto[0] auto[0] 62850 1 T1 236 T20 50 T21 32
auto[1] auto[1] auto[0] auto[0] auto[1] 5728 1 T8 2 T1 64 T20 28
auto[1] auto[1] auto[0] auto[1] auto[0] 46200 1 T1 582 T20 106 T21 120
auto[1] auto[1] auto[0] auto[1] auto[1] 11908 1 T8 40 T1 308 T20 42
auto[1] auto[1] auto[1] auto[0] auto[0] 35806 1 T8 18 T1 188 T20 56
auto[1] auto[1] auto[1] auto[0] auto[1] 8658 1 T1 62 T20 4 T24 28
auto[1] auto[1] auto[1] auto[1] auto[0] 75532 1 T8 52 T1 846 T24 64
auto[1] auto[1] auto[1] auto[1] auto[1] 16858 1 T1 196 T20 40 T25 60

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