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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 1010
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T807 /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.117107998 May 30 02:34:23 PM PDT 24 May 30 02:34:26 PM PDT 24 59452050 ps
T808 /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.1035251461 May 30 02:34:11 PM PDT 24 May 30 02:34:13 PM PDT 24 38450853 ps
T809 /workspace/coverage/default/1.clkmgr_frequency.1901937263 May 30 02:33:35 PM PDT 24 May 30 02:33:41 PM PDT 24 471728943 ps
T810 /workspace/coverage/default/45.clkmgr_alert_test.660024152 May 30 02:35:21 PM PDT 24 May 30 02:35:24 PM PDT 24 24113221 ps
T811 /workspace/coverage/default/25.clkmgr_alert_test.1920665563 May 30 02:34:43 PM PDT 24 May 30 02:34:45 PM PDT 24 14287371 ps
T812 /workspace/coverage/default/23.clkmgr_trans.3014314589 May 30 02:34:28 PM PDT 24 May 30 02:34:34 PM PDT 24 38720158 ps
T813 /workspace/coverage/default/0.clkmgr_peri.1953599509 May 30 02:33:18 PM PDT 24 May 30 02:33:24 PM PDT 24 32874652 ps
T814 /workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.918170253 May 30 02:34:45 PM PDT 24 May 30 02:37:33 PM PDT 24 25466800079 ps
T815 /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.1783710642 May 30 02:33:37 PM PDT 24 May 30 02:33:42 PM PDT 24 27578403 ps
T816 /workspace/coverage/default/25.clkmgr_frequency.279949285 May 30 02:34:30 PM PDT 24 May 30 02:34:42 PM PDT 24 1473508650 ps
T817 /workspace/coverage/default/12.clkmgr_frequency_timeout.2317336161 May 30 02:33:55 PM PDT 24 May 30 02:34:06 PM PDT 24 1339686437 ps
T818 /workspace/coverage/default/35.clkmgr_alert_test.1729792135 May 30 02:35:02 PM PDT 24 May 30 02:35:06 PM PDT 24 24784628 ps
T819 /workspace/coverage/default/38.clkmgr_clk_status.1027651893 May 30 02:35:10 PM PDT 24 May 30 02:35:14 PM PDT 24 18444269 ps
T820 /workspace/coverage/default/24.clkmgr_div_intersig_mubi.2943257488 May 30 02:34:26 PM PDT 24 May 30 02:34:29 PM PDT 24 13735876 ps
T821 /workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.2571905956 May 30 02:35:24 PM PDT 24 May 30 02:38:30 PM PDT 24 11543622379 ps
T822 /workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.230854679 May 30 02:35:07 PM PDT 24 May 30 02:49:01 PM PDT 24 63191173643 ps
T823 /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.1875682729 May 30 02:33:54 PM PDT 24 May 30 02:33:58 PM PDT 24 29550709 ps
T824 /workspace/coverage/default/35.clkmgr_peri.127675905 May 30 02:35:03 PM PDT 24 May 30 02:35:07 PM PDT 24 18673353 ps
T825 /workspace/coverage/default/11.clkmgr_peri.1984087160 May 30 02:33:55 PM PDT 24 May 30 02:33:59 PM PDT 24 23279207 ps
T826 /workspace/coverage/default/15.clkmgr_div_intersig_mubi.2465254142 May 30 02:34:11 PM PDT 24 May 30 02:34:13 PM PDT 24 29164704 ps
T827 /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.2978412895 May 30 02:33:59 PM PDT 24 May 30 02:34:04 PM PDT 24 27658519 ps
T828 /workspace/coverage/default/7.clkmgr_alert_test.4215657652 May 30 02:33:49 PM PDT 24 May 30 02:33:54 PM PDT 24 18948148 ps
T829 /workspace/coverage/default/12.clkmgr_frequency.1131589751 May 30 02:33:58 PM PDT 24 May 30 02:34:13 PM PDT 24 2509795757 ps
T830 /workspace/coverage/default/0.clkmgr_frequency_timeout.4004595663 May 30 02:33:20 PM PDT 24 May 30 02:33:33 PM PDT 24 1915815581 ps
T831 /workspace/coverage/default/49.clkmgr_smoke.3397741185 May 30 02:35:26 PM PDT 24 May 30 02:35:29 PM PDT 24 17103889 ps
T832 /workspace/coverage/default/3.clkmgr_frequency_timeout.615534836 May 30 02:33:37 PM PDT 24 May 30 02:33:44 PM PDT 24 409982386 ps
T833 /workspace/coverage/default/38.clkmgr_frequency.377041894 May 30 02:35:17 PM PDT 24 May 30 02:35:31 PM PDT 24 1521778273 ps
T834 /workspace/coverage/default/40.clkmgr_peri.3403719027 May 30 02:35:08 PM PDT 24 May 30 02:35:12 PM PDT 24 16039665 ps
T835 /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.1083976005 May 30 02:35:04 PM PDT 24 May 30 02:35:07 PM PDT 24 79085122 ps
T836 /workspace/coverage/default/43.clkmgr_regwen.1298486623 May 30 02:35:18 PM PDT 24 May 30 02:35:27 PM PDT 24 1154900152 ps
T837 /workspace/coverage/default/2.clkmgr_alert_test.3802678763 May 30 02:33:35 PM PDT 24 May 30 02:33:40 PM PDT 24 34215483 ps
T838 /workspace/coverage/default/8.clkmgr_peri.950226334 May 30 02:33:48 PM PDT 24 May 30 02:33:52 PM PDT 24 23897027 ps
T839 /workspace/coverage/default/20.clkmgr_clk_status.175306915 May 30 02:34:13 PM PDT 24 May 30 02:34:17 PM PDT 24 23202129 ps
T840 /workspace/coverage/default/39.clkmgr_stress_all.3189233216 May 30 02:35:11 PM PDT 24 May 30 02:35:15 PM PDT 24 76342806 ps
T841 /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.2428598817 May 30 02:34:00 PM PDT 24 May 30 02:34:05 PM PDT 24 27251934 ps
T842 /workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.3502726897 May 30 02:34:59 PM PDT 24 May 30 02:41:10 PM PDT 24 60041935978 ps
T843 /workspace/coverage/default/36.clkmgr_frequency_timeout.1647380304 May 30 02:34:59 PM PDT 24 May 30 02:35:20 PM PDT 24 2417119007 ps
T844 /workspace/coverage/default/17.clkmgr_extclk.2256130584 May 30 02:34:10 PM PDT 24 May 30 02:34:13 PM PDT 24 173137564 ps
T845 /workspace/coverage/default/37.clkmgr_frequency_timeout.3443552257 May 30 02:35:09 PM PDT 24 May 30 02:35:24 PM PDT 24 2188009094 ps
T846 /workspace/coverage/default/4.clkmgr_alert_test.230660473 May 30 02:33:38 PM PDT 24 May 30 02:33:45 PM PDT 24 18037750 ps
T847 /workspace/coverage/default/47.clkmgr_div_intersig_mubi.536651530 May 30 02:35:28 PM PDT 24 May 30 02:35:31 PM PDT 24 14602705 ps
T848 /workspace/coverage/default/43.clkmgr_smoke.2498979218 May 30 02:35:14 PM PDT 24 May 30 02:35:18 PM PDT 24 71890336 ps
T849 /workspace/coverage/default/44.clkmgr_extclk.1028217769 May 30 02:35:19 PM PDT 24 May 30 02:35:23 PM PDT 24 141389139 ps
T850 /workspace/coverage/default/30.clkmgr_peri.539535489 May 30 02:34:48 PM PDT 24 May 30 02:34:50 PM PDT 24 20509454 ps
T851 /workspace/coverage/default/11.clkmgr_frequency.522830265 May 30 02:33:55 PM PDT 24 May 30 02:34:01 PM PDT 24 532418275 ps
T852 /workspace/coverage/default/46.clkmgr_trans.3738898862 May 30 02:35:25 PM PDT 24 May 30 02:35:28 PM PDT 24 125682770 ps
T853 /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.1875404703 May 30 02:33:52 PM PDT 24 May 30 02:33:57 PM PDT 24 82250262 ps
T854 /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.39570994 May 30 02:35:11 PM PDT 24 May 30 02:35:16 PM PDT 24 33872786 ps
T855 /workspace/coverage/default/1.clkmgr_div_intersig_mubi.3241886483 May 30 02:33:35 PM PDT 24 May 30 02:33:40 PM PDT 24 97903251 ps
T856 /workspace/coverage/default/48.clkmgr_frequency_timeout.2987111391 May 30 02:35:28 PM PDT 24 May 30 02:35:41 PM PDT 24 1819407815 ps
T857 /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.279057827 May 30 02:34:28 PM PDT 24 May 30 02:34:34 PM PDT 24 93805661 ps
T858 /workspace/coverage/default/30.clkmgr_regwen.854398916 May 30 02:34:40 PM PDT 24 May 30 02:34:44 PM PDT 24 389805900 ps
T859 /workspace/coverage/default/29.clkmgr_div_intersig_mubi.380657663 May 30 02:34:44 PM PDT 24 May 30 02:34:47 PM PDT 24 36558472 ps
T860 /workspace/coverage/default/18.clkmgr_smoke.3962557436 May 30 02:34:17 PM PDT 24 May 30 02:34:20 PM PDT 24 65100293 ps
T861 /workspace/coverage/default/13.clkmgr_clk_status.3210794347 May 30 02:34:01 PM PDT 24 May 30 02:34:05 PM PDT 24 45555605 ps
T56 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.4255857612 May 30 01:48:38 PM PDT 24 May 30 01:48:42 PM PDT 24 136411736 ps
T105 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.2111930319 May 30 01:47:49 PM PDT 24 May 30 01:47:55 PM PDT 24 699421871 ps
T57 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.906991165 May 30 01:47:37 PM PDT 24 May 30 01:47:40 PM PDT 24 59898131 ps
T862 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.839672998 May 30 01:49:02 PM PDT 24 May 30 01:49:04 PM PDT 24 27123844 ps
T106 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3812625444 May 30 01:48:25 PM PDT 24 May 30 01:48:27 PM PDT 24 29067628 ps
T863 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.3767040701 May 30 01:49:21 PM PDT 24 May 30 01:49:22 PM PDT 24 37458834 ps
T74 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3149136520 May 30 01:48:24 PM PDT 24 May 30 01:48:26 PM PDT 24 35819644 ps
T148 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.4032128616 May 30 01:48:02 PM PDT 24 May 30 01:48:04 PM PDT 24 26532122 ps
T864 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.628903995 May 30 01:49:22 PM PDT 24 May 30 01:49:23 PM PDT 24 26351542 ps
T865 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.186832573 May 30 01:48:52 PM PDT 24 May 30 01:48:54 PM PDT 24 13024760 ps
T866 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2068795742 May 30 01:48:02 PM PDT 24 May 30 01:48:03 PM PDT 24 24551243 ps
T75 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.630584782 May 30 01:48:56 PM PDT 24 May 30 01:48:58 PM PDT 24 25285735 ps
T58 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2888017053 May 30 01:48:37 PM PDT 24 May 30 01:48:40 PM PDT 24 116547453 ps
T867 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.1514707223 May 30 01:48:52 PM PDT 24 May 30 01:48:54 PM PDT 24 12977907 ps
T76 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.2763141696 May 30 01:48:41 PM PDT 24 May 30 01:48:43 PM PDT 24 47271323 ps
T868 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.2635638343 May 30 01:49:21 PM PDT 24 May 30 01:49:22 PM PDT 24 39869427 ps
T869 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.1467921791 May 30 01:48:23 PM PDT 24 May 30 01:48:25 PM PDT 24 143128450 ps
T870 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.747274510 May 30 01:48:04 PM PDT 24 May 30 01:48:09 PM PDT 24 237380396 ps
T871 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.865361009 May 30 01:49:04 PM PDT 24 May 30 01:49:05 PM PDT 24 20433085 ps
T62 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2783463669 May 30 01:48:36 PM PDT 24 May 30 01:48:39 PM PDT 24 328923356 ps
T77 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.1015770067 May 30 01:48:08 PM PDT 24 May 30 01:48:09 PM PDT 24 25864250 ps
T872 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.2168092068 May 30 01:47:36 PM PDT 24 May 30 01:47:38 PM PDT 24 27887955 ps
T873 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.1504401539 May 30 01:48:36 PM PDT 24 May 30 01:48:37 PM PDT 24 17375112 ps
T78 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.1574271197 May 30 01:48:40 PM PDT 24 May 30 01:48:42 PM PDT 24 28689373 ps
T61 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.160875774 May 30 01:48:25 PM PDT 24 May 30 01:48:28 PM PDT 24 262443875 ps
T79 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.452324123 May 30 01:48:07 PM PDT 24 May 30 01:48:09 PM PDT 24 15970321 ps
T874 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.1379436232 May 30 01:48:55 PM PDT 24 May 30 01:48:57 PM PDT 24 29018773 ps
T875 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2436134416 May 30 01:48:52 PM PDT 24 May 30 01:48:55 PM PDT 24 30079611 ps
T876 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.1764160319 May 30 01:47:48 PM PDT 24 May 30 01:47:50 PM PDT 24 74399812 ps
T80 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2931467456 May 30 01:48:34 PM PDT 24 May 30 01:48:36 PM PDT 24 19177478 ps
T81 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1343713947 May 30 01:48:03 PM PDT 24 May 30 01:48:05 PM PDT 24 47844993 ps
T877 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.2233093190 May 30 01:48:04 PM PDT 24 May 30 01:48:06 PM PDT 24 17533066 ps
T878 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.3220394909 May 30 01:49:20 PM PDT 24 May 30 01:49:22 PM PDT 24 95941473 ps
T59 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3899501637 May 30 01:48:52 PM PDT 24 May 30 01:48:55 PM PDT 24 159042081 ps
T60 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3678754120 May 30 01:48:51 PM PDT 24 May 30 01:48:54 PM PDT 24 116212596 ps
T82 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3865795990 May 30 01:48:40 PM PDT 24 May 30 01:48:44 PM PDT 24 225899228 ps
T879 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.726186245 May 30 01:49:02 PM PDT 24 May 30 01:49:04 PM PDT 24 43130436 ps
T880 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1338773493 May 30 01:48:03 PM PDT 24 May 30 01:48:05 PM PDT 24 70769298 ps
T881 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.1403564408 May 30 01:49:03 PM PDT 24 May 30 01:49:05 PM PDT 24 27002304 ps
T882 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.2413604204 May 30 01:48:52 PM PDT 24 May 30 01:48:54 PM PDT 24 31994818 ps
T883 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.1251599763 May 30 01:47:48 PM PDT 24 May 30 01:47:50 PM PDT 24 39206392 ps
T63 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.1772972398 May 30 01:48:10 PM PDT 24 May 30 01:48:13 PM PDT 24 138371024 ps
T884 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1840912589 May 30 01:48:25 PM PDT 24 May 30 01:48:26 PM PDT 24 20257999 ps
T885 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.1694251587 May 30 01:49:21 PM PDT 24 May 30 01:49:23 PM PDT 24 13169050 ps
T886 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.1201345211 May 30 01:48:02 PM PDT 24 May 30 01:48:04 PM PDT 24 39679444 ps
T100 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.3044714027 May 30 01:48:38 PM PDT 24 May 30 01:48:41 PM PDT 24 164534585 ps
T887 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.174010413 May 30 01:49:02 PM PDT 24 May 30 01:49:03 PM PDT 24 12109192 ps
T888 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.827999677 May 30 01:48:50 PM PDT 24 May 30 01:48:53 PM PDT 24 24845944 ps
T889 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.3039597270 May 30 01:48:38 PM PDT 24 May 30 01:48:43 PM PDT 24 161150818 ps
T890 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.2234213950 May 30 01:47:48 PM PDT 24 May 30 01:47:50 PM PDT 24 30594013 ps
T891 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.430162329 May 30 01:48:50 PM PDT 24 May 30 01:48:52 PM PDT 24 50928334 ps
T143 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2805645360 May 30 01:48:50 PM PDT 24 May 30 01:48:55 PM PDT 24 139690783 ps
T892 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3739266470 May 30 01:48:08 PM PDT 24 May 30 01:48:10 PM PDT 24 32398480 ps
T893 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.3601459732 May 30 01:48:50 PM PDT 24 May 30 01:48:52 PM PDT 24 38613755 ps
T894 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.3446217729 May 30 01:48:23 PM PDT 24 May 30 01:48:25 PM PDT 24 18315540 ps
T101 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2813228272 May 30 01:48:29 PM PDT 24 May 30 01:48:31 PM PDT 24 124955160 ps
T895 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.97094473 May 30 01:48:09 PM PDT 24 May 30 01:48:11 PM PDT 24 61810766 ps
T896 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.3155400719 May 30 01:48:55 PM PDT 24 May 30 01:48:56 PM PDT 24 17172852 ps
T897 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.3224711410 May 30 01:48:36 PM PDT 24 May 30 01:48:38 PM PDT 24 18290079 ps
T133 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3411846957 May 30 01:47:37 PM PDT 24 May 30 01:47:40 PM PDT 24 86247476 ps
T127 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.4034909310 May 30 01:48:51 PM PDT 24 May 30 01:48:54 PM PDT 24 127789498 ps
T898 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.548376983 May 30 01:48:04 PM PDT 24 May 30 01:48:07 PM PDT 24 57248628 ps
T128 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3227888074 May 30 01:48:08 PM PDT 24 May 30 01:48:12 PM PDT 24 155730985 ps
T899 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.1714756064 May 30 01:48:52 PM PDT 24 May 30 01:48:54 PM PDT 24 21201263 ps
T900 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.3946674718 May 30 01:47:49 PM PDT 24 May 30 01:47:53 PM PDT 24 517076907 ps
T901 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.125044312 May 30 01:48:23 PM PDT 24 May 30 01:48:24 PM PDT 24 78618363 ps
T902 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1079711622 May 30 01:49:21 PM PDT 24 May 30 01:49:23 PM PDT 24 11041947 ps
T903 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.1263045238 May 30 01:48:04 PM PDT 24 May 30 01:48:09 PM PDT 24 40496237 ps
T904 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.316970712 May 30 01:48:36 PM PDT 24 May 30 01:48:38 PM PDT 24 22556298 ps
T905 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1862203472 May 30 01:48:04 PM PDT 24 May 30 01:48:08 PM PDT 24 37782816 ps
T906 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.3732539494 May 30 01:47:50 PM PDT 24 May 30 01:47:51 PM PDT 24 22431671 ps
T907 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.3159400205 May 30 01:49:21 PM PDT 24 May 30 01:49:23 PM PDT 24 34084014 ps
T908 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.4156623742 May 30 01:49:22 PM PDT 24 May 30 01:49:23 PM PDT 24 12745622 ps
T134 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3448754725 May 30 01:47:35 PM PDT 24 May 30 01:47:39 PM PDT 24 163977883 ps
T909 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.60725115 May 30 01:48:39 PM PDT 24 May 30 01:48:44 PM PDT 24 227265541 ps
T135 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.3487607593 May 30 01:48:03 PM PDT 24 May 30 01:48:06 PM PDT 24 143272392 ps
T140 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.3659126637 May 30 01:48:07 PM PDT 24 May 30 01:48:10 PM PDT 24 128442207 ps
T910 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3357935796 May 30 01:48:50 PM PDT 24 May 30 01:48:52 PM PDT 24 23832499 ps
T911 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3277685752 May 30 01:47:48 PM PDT 24 May 30 01:47:49 PM PDT 24 43790124 ps
T912 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.3640756789 May 30 01:48:55 PM PDT 24 May 30 01:48:58 PM PDT 24 96971611 ps
T913 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.429137368 May 30 01:48:35 PM PDT 24 May 30 01:48:37 PM PDT 24 13169542 ps
T914 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3500798333 May 30 01:48:03 PM PDT 24 May 30 01:48:05 PM PDT 24 59174401 ps
T915 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.216792250 May 30 01:48:53 PM PDT 24 May 30 01:48:55 PM PDT 24 19202177 ps
T916 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3141592159 May 30 01:48:03 PM PDT 24 May 30 01:48:05 PM PDT 24 27130164 ps
T917 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.1241499435 May 30 01:48:51 PM PDT 24 May 30 01:48:53 PM PDT 24 13259890 ps
T918 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.2887921010 May 30 01:48:51 PM PDT 24 May 30 01:48:53 PM PDT 24 13798568 ps
T919 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2491446582 May 30 01:47:40 PM PDT 24 May 30 01:47:41 PM PDT 24 17832503 ps
T920 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.721834483 May 30 01:48:50 PM PDT 24 May 30 01:48:51 PM PDT 24 14920823 ps
T921 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2291251658 May 30 01:47:40 PM PDT 24 May 30 01:47:41 PM PDT 24 35845798 ps
T922 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.349500116 May 30 01:48:55 PM PDT 24 May 30 01:48:56 PM PDT 24 12506201 ps
T923 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.2506186190 May 30 01:48:35 PM PDT 24 May 30 01:48:39 PM PDT 24 278266836 ps
T144 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.1407826327 May 30 01:48:34 PM PDT 24 May 30 01:48:38 PM PDT 24 285066521 ps
T145 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.3898832217 May 30 01:48:50 PM PDT 24 May 30 01:48:52 PM PDT 24 122255881 ps
T102 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.1996154259 May 30 01:47:48 PM PDT 24 May 30 01:47:52 PM PDT 24 449805923 ps
T924 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.541973112 May 30 01:48:53 PM PDT 24 May 30 01:48:56 PM PDT 24 36634915 ps
T925 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.1880299107 May 30 01:48:52 PM PDT 24 May 30 01:48:55 PM PDT 24 81998425 ps
T112 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.712490653 May 30 01:48:54 PM PDT 24 May 30 01:48:58 PM PDT 24 228896430 ps
T926 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.1272168235 May 30 01:47:48 PM PDT 24 May 30 01:47:51 PM PDT 24 26209276 ps
T927 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.987246218 May 30 01:48:50 PM PDT 24 May 30 01:48:52 PM PDT 24 34583781 ps
T191 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.2373937991 May 30 01:47:37 PM PDT 24 May 30 01:47:39 PM PDT 24 105426576 ps
T928 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.1056163699 May 30 01:48:50 PM PDT 24 May 30 01:48:53 PM PDT 24 71129577 ps
T129 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2063628292 May 30 01:48:10 PM PDT 24 May 30 01:48:13 PM PDT 24 147641275 ps
T146 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.171567223 May 30 01:48:23 PM PDT 24 May 30 01:48:26 PM PDT 24 120452468 ps
T929 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.2273708627 May 30 01:48:52 PM PDT 24 May 30 01:48:54 PM PDT 24 21979955 ps
T930 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.3602410714 May 30 01:48:52 PM PDT 24 May 30 01:48:58 PM PDT 24 457578712 ps
T931 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.889474976 May 30 01:48:53 PM PDT 24 May 30 01:48:55 PM PDT 24 13767175 ps
T193 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.176219954 May 30 01:48:08 PM PDT 24 May 30 01:48:12 PM PDT 24 322062348 ps
T932 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1100972356 May 30 01:48:05 PM PDT 24 May 30 01:48:07 PM PDT 24 10971835 ps
T136 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2497172028 May 30 01:48:04 PM PDT 24 May 30 01:48:08 PM PDT 24 87375761 ps
T933 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.1717620139 May 30 01:48:04 PM PDT 24 May 30 01:48:06 PM PDT 24 61178693 ps
T934 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.1001887309 May 30 01:47:37 PM PDT 24 May 30 01:47:39 PM PDT 24 26156224 ps
T935 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1428490760 May 30 01:48:50 PM PDT 24 May 30 01:48:52 PM PDT 24 34658735 ps
T936 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2712706418 May 30 01:48:36 PM PDT 24 May 30 01:48:38 PM PDT 24 43716171 ps
T137 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.467959425 May 30 01:48:35 PM PDT 24 May 30 01:48:38 PM PDT 24 64023548 ps
T141 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.2203620866 May 30 01:48:55 PM PDT 24 May 30 01:48:58 PM PDT 24 157527397 ps
T937 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3089364760 May 30 01:47:48 PM PDT 24 May 30 01:47:56 PM PDT 24 672937952 ps
T938 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.119188353 May 30 01:48:05 PM PDT 24 May 30 01:48:18 PM PDT 24 1908728971 ps
T107 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2892703282 May 30 01:48:25 PM PDT 24 May 30 01:48:29 PM PDT 24 218054202 ps
T939 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2130661548 May 30 01:48:52 PM PDT 24 May 30 01:48:55 PM PDT 24 182505529 ps
T940 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.1737469806 May 30 01:48:41 PM PDT 24 May 30 01:48:42 PM PDT 24 16323680 ps
T941 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.4056424878 May 30 01:48:36 PM PDT 24 May 30 01:48:40 PM PDT 24 327939776 ps
T942 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.443519838 May 30 01:48:37 PM PDT 24 May 30 01:48:39 PM PDT 24 31208366 ps
T943 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.112778405 May 30 01:47:38 PM PDT 24 May 30 01:47:41 PM PDT 24 149105462 ps
T108 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.210467628 May 30 01:48:09 PM PDT 24 May 30 01:48:13 PM PDT 24 579328371 ps
T944 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.2446235447 May 30 01:48:24 PM PDT 24 May 30 01:48:26 PM PDT 24 30368463 ps
T147 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.795133103 May 30 01:47:38 PM PDT 24 May 30 01:47:41 PM PDT 24 85371403 ps
T945 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2868219327 May 30 01:49:23 PM PDT 24 May 30 01:49:24 PM PDT 24 32254149 ps
T946 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.1913476445 May 30 01:48:09 PM PDT 24 May 30 01:48:11 PM PDT 24 30694060 ps
T947 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1661140898 May 30 01:48:40 PM PDT 24 May 30 01:48:44 PM PDT 24 197320587 ps
T130 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1655459315 May 30 01:48:06 PM PDT 24 May 30 01:48:09 PM PDT 24 140635457 ps
T131 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.237971479 May 30 01:47:47 PM PDT 24 May 30 01:47:49 PM PDT 24 61486464 ps
T948 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.3151603835 May 30 01:47:48 PM PDT 24 May 30 01:47:49 PM PDT 24 29745669 ps
T949 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.2619289634 May 30 01:48:52 PM PDT 24 May 30 01:48:54 PM PDT 24 13918347 ps
T950 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.1571602901 May 30 01:48:23 PM PDT 24 May 30 01:48:27 PM PDT 24 363137254 ps
T951 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.1236670963 May 30 01:47:40 PM PDT 24 May 30 01:47:42 PM PDT 24 54912586 ps
T952 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2483293683 May 30 01:47:50 PM PDT 24 May 30 01:47:53 PM PDT 24 507469064 ps
T953 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1798901061 May 30 01:48:08 PM PDT 24 May 30 01:48:12 PM PDT 24 596044538 ps
T138 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.2398063540 May 30 01:48:09 PM PDT 24 May 30 01:48:12 PM PDT 24 108290559 ps
T954 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2816115845 May 30 01:48:41 PM PDT 24 May 30 01:48:42 PM PDT 24 61609799 ps
T113 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3500768804 May 30 01:48:42 PM PDT 24 May 30 01:48:46 PM PDT 24 316464764 ps
T955 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1373103680 May 30 01:48:37 PM PDT 24 May 30 01:48:40 PM PDT 24 273510852 ps
T956 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.3641444169 May 30 01:48:41 PM PDT 24 May 30 01:48:43 PM PDT 24 19297151 ps
T957 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.2118574698 May 30 01:48:06 PM PDT 24 May 30 01:48:08 PM PDT 24 50909195 ps
T958 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1730059876 May 30 01:47:46 PM PDT 24 May 30 01:47:48 PM PDT 24 118845272 ps
T959 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.542595974 May 30 01:48:03 PM PDT 24 May 30 01:48:05 PM PDT 24 123185744 ps
T960 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.510107160 May 30 01:48:23 PM PDT 24 May 30 01:48:25 PM PDT 24 140480059 ps
T961 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.100778520 May 30 01:48:51 PM PDT 24 May 30 01:48:54 PM PDT 24 20918379 ps
T962 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.527337354 May 30 01:48:55 PM PDT 24 May 30 01:48:58 PM PDT 24 80838106 ps
T963 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.527055507 May 30 01:48:41 PM PDT 24 May 30 01:48:47 PM PDT 24 1291150841 ps
T964 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.3913493497 May 30 01:48:40 PM PDT 24 May 30 01:48:42 PM PDT 24 44288315 ps
T965 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.3066535603 May 30 01:47:37 PM PDT 24 May 30 01:47:43 PM PDT 24 632057953 ps
T966 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.3852261341 May 30 01:48:39 PM PDT 24 May 30 01:48:42 PM PDT 24 131192056 ps
T967 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1172044856 May 30 01:48:25 PM PDT 24 May 30 01:48:28 PM PDT 24 318860113 ps
T110 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1561974270 May 30 01:47:37 PM PDT 24 May 30 01:47:40 PM PDT 24 73881733 ps
T968 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.899432166 May 30 01:48:52 PM PDT 24 May 30 01:48:54 PM PDT 24 26337965 ps
T142 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.3671087142 May 30 01:48:38 PM PDT 24 May 30 01:48:45 PM PDT 24 1192256814 ps
T969 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3715251424 May 30 01:47:49 PM PDT 24 May 30 01:47:51 PM PDT 24 84400591 ps
T970 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.2691969270 May 30 01:47:38 PM PDT 24 May 30 01:47:40 PM PDT 24 13375354 ps
T971 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2250936826 May 30 01:48:04 PM PDT 24 May 30 01:48:07 PM PDT 24 227243343 ps
T194 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.434885128 May 30 01:48:50 PM PDT 24 May 30 01:48:55 PM PDT 24 213771120 ps
T972 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.4110333155 May 30 01:48:35 PM PDT 24 May 30 01:48:40 PM PDT 24 479622286 ps
T973 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.3402404729 May 30 01:48:10 PM PDT 24 May 30 01:48:12 PM PDT 24 109738419 ps
T974 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.4079099952 May 30 01:47:36 PM PDT 24 May 30 01:47:42 PM PDT 24 499875485 ps
T975 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.2519736531 May 30 01:47:36 PM PDT 24 May 30 01:47:38 PM PDT 24 16106124 ps
T976 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.3671304067 May 30 01:48:34 PM PDT 24 May 30 01:48:36 PM PDT 24 39108763 ps
T103 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.2214091085 May 30 01:48:52 PM PDT 24 May 30 01:48:56 PM PDT 24 233052975 ps
T977 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.223308280 May 30 01:48:36 PM PDT 24 May 30 01:48:38 PM PDT 24 21743006 ps
T978 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.3082873878 May 30 01:49:00 PM PDT 24 May 30 01:49:02 PM PDT 24 12401413 ps
T979 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.412199361 May 30 01:49:20 PM PDT 24 May 30 01:49:21 PM PDT 24 11474741 ps
T980 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.922440020 May 30 01:48:03 PM PDT 24 May 30 01:48:05 PM PDT 24 63014866 ps
T981 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.1223571143 May 30 01:48:18 PM PDT 24 May 30 01:48:22 PM PDT 24 165657212 ps
T982 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.520904859 May 30 01:48:35 PM PDT 24 May 30 01:48:37 PM PDT 24 25104275 ps
T983 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.3434508076 May 30 01:48:03 PM PDT 24 May 30 01:48:08 PM PDT 24 203530518 ps
T984 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.77681832 May 30 01:48:20 PM PDT 24 May 30 01:48:23 PM PDT 24 67792714 ps
T985 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.1535386213 May 30 01:48:42 PM PDT 24 May 30 01:48:44 PM PDT 24 31904941 ps
T139 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.2916988366 May 30 01:48:23 PM PDT 24 May 30 01:48:25 PM PDT 24 77093657 ps
T132 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.1431957812 May 30 01:48:53 PM PDT 24 May 30 01:48:57 PM PDT 24 98592985 ps
T986 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1111288924 May 30 01:47:49 PM PDT 24 May 30 01:47:51 PM PDT 24 140081201 ps
T987 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.779718702 May 30 01:48:04 PM PDT 24 May 30 01:48:06 PM PDT 24 39197763 ps
T988 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.1981333904 May 30 01:48:27 PM PDT 24 May 30 01:48:30 PM PDT 24 82327612 ps
T989 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.4237854658 May 30 01:48:25 PM PDT 24 May 30 01:48:27 PM PDT 24 134707668 ps
T990 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.4052802142 May 30 01:48:08 PM PDT 24 May 30 01:48:12 PM PDT 24 69601315 ps
T991 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1576060039 May 30 01:48:03 PM PDT 24 May 30 01:48:07 PM PDT 24 347776944 ps
T992 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.4029011867 May 30 01:48:52 PM PDT 24 May 30 01:48:54 PM PDT 24 14141956 ps
T111 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.4280712464 May 30 01:48:35 PM PDT 24 May 30 01:48:38 PM PDT 24 187470234 ps
T993 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.560658302 May 30 01:48:54 PM PDT 24 May 30 01:48:56 PM PDT 24 38504962 ps
T994 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.1109259071 May 30 01:48:24 PM PDT 24 May 30 01:48:28 PM PDT 24 207592709 ps
T995 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.1108156689 May 30 01:48:03 PM PDT 24 May 30 01:48:05 PM PDT 24 48794237 ps
T996 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.1346580485 May 30 01:49:02 PM PDT 24 May 30 01:49:04 PM PDT 24 14127622 ps
T997 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1119822624 May 30 01:47:46 PM PDT 24 May 30 01:47:48 PM PDT 24 144834838 ps
T998 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.969358811 May 30 01:47:38 PM PDT 24 May 30 01:47:51 PM PDT 24 1860976917 ps
T999 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2548817550 May 30 01:47:48 PM PDT 24 May 30 01:47:49 PM PDT 24 21012524 ps
T1000 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1259091017 May 30 01:48:50 PM PDT 24 May 30 01:48:53 PM PDT 24 124586894 ps
T1001 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.117124190 May 30 01:47:49 PM PDT 24 May 30 01:47:51 PM PDT 24 66181877 ps
T1002 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.2079149345 May 30 01:48:35 PM PDT 24 May 30 01:48:38 PM PDT 24 23564639 ps
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