Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 314766126 1 T1 402342 T2 116785 T4 2206
auto[1] 420764 1 T1 1072 T2 9398 T3 2252


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 314780940 1 T1 402832 T2 116814 T4 2206
auto[1] 405950 1 T1 582 T2 6532 T3 1444


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 314698914 1 T1 402556 T2 116778 T4 2206
auto[1] 487976 1 T1 858 T2 10058 T3 1856


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 302164984 1 T1 402264 T2 104984 T4 2206
auto[1] 13021906 1 T1 1150 T2 118953 T3 7280


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 180618102 1 T1 394594 T2 523195 T4 2206
auto[1] 134568788 1 T1 8820 T2 645600 T3 524518


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 170220454 1 T1 393184 T2 404319 T4 2206
auto[0] auto[0] auto[0] auto[0] auto[1] 131611300 1 T1 8274 T2 644958 T3 523754
auto[0] auto[0] auto[0] auto[1] auto[0] 30258 1 T1 106 T2 926 T3 180
auto[0] auto[0] auto[0] auto[1] auto[1] 7758 1 T1 72 T2 532 T3 44
auto[0] auto[0] auto[1] auto[0] auto[0] 9806776 1 T1 434 T2 117840 T3 5312
auto[0] auto[0] auto[1] auto[0] auto[1] 2840266 1 T1 202 T2 2534 T3 332
auto[0] auto[0] auto[1] auto[1] auto[0] 52926 1 T1 110 T2 1140 T3 254
auto[0] auto[0] auto[1] auto[1] auto[1] 14534 1 T1 36 T2 294 T3 30
auto[0] auto[1] auto[0] auto[0] auto[0] 59332 1 T1 26 T2 66 T19 22
auto[0] auto[1] auto[0] auto[0] auto[1] 1038 1 T2 218 T39 14 T14 34
auto[0] auto[1] auto[0] auto[1] auto[0] 11670 1 T1 112 T2 178 T19 36
auto[0] auto[1] auto[0] auto[1] auto[1] 2792 1 T2 264 T39 46 T14 48
auto[0] auto[1] auto[1] auto[0] auto[0] 11804 1 T2 94 T3 28 T17 32
auto[0] auto[1] auto[1] auto[0] auto[1] 2792 1 T2 126 T17 104 T10 6
auto[0] auto[1] auto[1] auto[1] auto[0] 20146 1 T2 224 T3 160 T18 54
auto[0] auto[1] auto[1] auto[1] auto[1] 5068 1 T2 116 T10 98 T12 76
auto[1] auto[0] auto[0] auto[0] auto[0] 39328 1 T1 10 T2 444 T3 12
auto[1] auto[0] auto[0] auto[0] auto[1] 4586 1 T1 22 T2 192 T3 2
auto[1] auto[0] auto[0] auto[1] auto[0] 30188 1 T1 76 T2 470 T3 98
auto[1] auto[0] auto[0] auto[1] auto[1] 8754 1 T1 60 T2 260 T3 58
auto[1] auto[0] auto[1] auto[0] auto[0] 31090 1 T1 74 T2 1062 T3 52
auto[1] auto[0] auto[1] auto[0] auto[1] 7664 1 T1 32 T2 238 T3 42
auto[1] auto[0] auto[1] auto[1] auto[0] 61294 1 T1 140 T2 2084 T3 214
auto[1] auto[0] auto[1] auto[1] auto[1] 13764 1 T2 62 T3 122 T70 94
auto[1] auto[1] auto[0] auto[0] auto[0] 69638 1 T1 54 T2 578 T3 32
auto[1] auto[1] auto[0] auto[0] auto[1] 6632 1 T2 296 T3 12 T10 22
auto[1] auto[1] auto[0] auto[1] auto[0] 49492 1 T1 268 T2 1136 T3 356
auto[1] auto[1] auto[0] auto[1] auto[1] 11764 1 T2 80 T3 122 T10 84
auto[1] auto[1] auto[1] auto[0] auto[0] 42720 1 T2 1042 T3 120 T17 244
auto[1] auto[1] auto[1] auto[0] auto[1] 10706 1 T1 30 T2 482 T17 48
auto[1] auto[1] auto[1] auto[1] auto[0] 80986 1 T2 906 T3 614 T19 82
auto[1] auto[1] auto[1] auto[1] auto[1] 19370 1 T1 92 T2 726 T10 270

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